112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich/* 2bd5a793fec23c1ee7f98b9b68001dcee0089ab35Michael Hennerich * AD9833/AD9834/AD9837/AD9838 SPI DDS driver 312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * 4bd5a793fec23c1ee7f98b9b68001dcee0089ab35Michael Hennerich * Copyright 2010-2011 Analog Devices Inc. 512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * 6bd5a793fec23c1ee7f98b9b68001dcee0089ab35Michael Hennerich * Licensed under the GPL-2. 712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich */ 812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#ifndef IIO_DDS_AD9834_H_ 912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define IIO_DDS_AD9834_H_ 1012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 1112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich/* Registers */ 1212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 1312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_REG_CMD (0 << 14) 1412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_REG_FREQ0 (1 << 14) 1512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_REG_FREQ1 (2 << 14) 1612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_REG_PHASE0 (6 << 13) 1712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_REG_PHASE1 (7 << 13) 1812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 1912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich/* Command Control Bits */ 2012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 2112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_B28 (1 << 13) 2212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_HLB (1 << 12) 2312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_FSEL (1 << 11) 2412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_PSEL (1 << 10) 2512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_PIN_SW (1 << 9) 2612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_RESET (1 << 8) 2712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_SLEEP1 (1 << 7) 2812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_SLEEP12 (1 << 6) 2912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_OPBITEN (1 << 5) 3012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_SIGN_PIB (1 << 4) 3112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_DIV2 (1 << 3) 3212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_MODE (1 << 1) 3312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 3412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_FREQ_BITS 28 3512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define AD9834_PHASE_BITS 12 3612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 3712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#define RES_MASK(bits) ((1 << (bits)) - 1) 3812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 3912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich/** 4012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * struct ad9834_state - driver instance specific data 4112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @spi: spi_device 4212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @reg: supply regulator 4312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @mclk: external master clock 4412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @control: cached control word 4512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @xfer: default spi transfer 4612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @msg: default spi message 4712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @freq_xfer: tuning word spi transfer 4812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @freq_msg: tuning word spi message 4912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @data: spi transmit buffer 5012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @freq_data: tuning word spi transmit buffer 5112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich */ 5212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 5312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerichstruct ad9834_state { 5412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich struct spi_device *spi; 5512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich struct regulator *reg; 5612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned int mclk; 5712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned short control; 5812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned short devid; 5912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich struct spi_transfer xfer; 6012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich struct spi_message msg; 6112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich struct spi_transfer freq_xfer[2]; 6212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich struct spi_message freq_msg; 6312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 6412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich /* 6512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * DMA (thus cache coherency maintenance) requires the 6612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * transfer buffers to live in their own cache lines. 6712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich */ 6812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned short data ____cacheline_aligned; 6912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned short freq_data[2] ; 7012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich}; 7112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 7212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 7312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich/* 7412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * TODO: struct ad7887_platform_data needs to go into include/linux/iio 7512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich */ 7612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 7712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich/** 7812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * struct ad9834_platform_data - platform specific information 7912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @mclk: master clock in Hz 8012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @freq0: power up freq0 tuning word in Hz 8112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @freq1: power up freq1 tuning word in Hz 8212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @phase0: power up phase0 value [0..4095] correlates with 0..2PI 8312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @phase1: power up phase1 value [0..4095] correlates with 0..2PI 8412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @en_div2: digital output/2 is passed to the SIGN BIT OUT pin 8512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * @en_signbit_msb_out: the MSB (or MSB/2) of the DAC data is connected to the 8612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * SIGN BIT OUT pin. en_div2 controls whether it is the MSB 8712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * or MSB/2 that is output. if en_signbit_msb_out=false, 8812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * the on-board comparator is connected to SIGN BIT OUT 8912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich */ 9012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 9112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerichstruct ad9834_platform_data { 9212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned int mclk; 9312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned int freq0; 9412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned int freq1; 9512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned short phase0; 9612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich unsigned short phase1; 9712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich bool en_div2; 9812b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich bool en_signbit_msb_out; 9912b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich}; 10012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 10112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich/** 10212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich * ad9834_supported_device_ids: 10312b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich */ 10412b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 10512b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerichenum ad9834_supported_device_ids { 10612b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich ID_AD9833, 10712b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich ID_AD9834, 108bd5a793fec23c1ee7f98b9b68001dcee0089ab35Michael Hennerich ID_AD9837, 109bd5a793fec23c1ee7f98b9b68001dcee0089ab35Michael Hennerich ID_AD9838, 11012b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich}; 11112b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich 11212b9d5bf76bfa20d3207ef24fca9c8254a586a58Michael Hennerich#endif /* IIO_DDS_AD9834_H_ */ 113