1/*
2 *
3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13 * more details.
14 *
15 */
16
17#ifndef _MEI_HW_TYPES_H_
18#define _MEI_HW_TYPES_H_
19
20#include <linux/uuid.h>
21
22/*
23 * Timeouts
24 */
25#define MEI_INTEROP_TIMEOUT    (HZ * 7)
26#define MEI_CONNECT_TIMEOUT		3	/* at least 2 seconds */
27
28#define CONNECT_TIMEOUT        15	/* HPS definition */
29#define INIT_CLIENTS_TIMEOUT   15	/* HPS definition */
30
31#define IAMTHIF_STALL_TIMER		12	/* seconds */
32#define IAMTHIF_READ_TIMER		10000	/* ms */
33
34/*
35 * Internal Clients Number
36 */
37#define MEI_WD_HOST_CLIENT_ID          1
38#define MEI_IAMTHIF_HOST_CLIENT_ID     2
39
40/*
41 * MEI device IDs
42 */
43#define    MEI_DEV_ID_82946GZ	0x2974  /* 82946GZ/GL */
44#define    MEI_DEV_ID_82G35	0x2984  /* 82G35 Express */
45#define    MEI_DEV_ID_82Q965	0x2994  /* 82Q963/Q965 */
46#define    MEI_DEV_ID_82G965	0x29A4  /* 82P965/G965 */
47
48#define    MEI_DEV_ID_82GM965	0x2A04  /* Mobile PM965/GM965 */
49#define    MEI_DEV_ID_82GME965	0x2A14  /* Mobile GME965/GLE960 */
50
51#define    MEI_DEV_ID_ICH9_82Q35 0x29B4  /* 82Q35 Express */
52#define    MEI_DEV_ID_ICH9_82G33 0x29C4  /* 82G33/G31/P35/P31 Express */
53#define    MEI_DEV_ID_ICH9_82Q33 0x29D4  /* 82Q33 Express */
54#define    MEI_DEV_ID_ICH9_82X38 0x29E4  /* 82X38/X48 Express */
55#define    MEI_DEV_ID_ICH9_3200  0x29F4  /* 3200/3210 Server */
56
57#define    MEI_DEV_ID_ICH9_6	0x28B4  /* Bearlake */
58#define    MEI_DEV_ID_ICH9_7	0x28C4  /* Bearlake */
59#define    MEI_DEV_ID_ICH9_8	0x28D4  /* Bearlake */
60#define    MEI_DEV_ID_ICH9_9    0x28E4  /* Bearlake */
61#define    MEI_DEV_ID_ICH9_10	0x28F4  /* Bearlake */
62
63#define    MEI_DEV_ID_ICH9M_1	0x2A44  /* Cantiga */
64#define    MEI_DEV_ID_ICH9M_2	0x2A54  /* Cantiga */
65#define    MEI_DEV_ID_ICH9M_3	0x2A64  /* Cantiga */
66#define    MEI_DEV_ID_ICH9M_4	0x2A74  /* Cantiga */
67
68#define    MEI_DEV_ID_ICH10_1	0x2E04  /* Eaglelake */
69#define    MEI_DEV_ID_ICH10_2	0x2E14  /* Eaglelake */
70#define    MEI_DEV_ID_ICH10_3	0x2E24  /* Eaglelake */
71#define    MEI_DEV_ID_ICH10_4	0x2E34  /* Eaglelake */
72
73#define    MEI_DEV_ID_IBXPK_1	0x3B64  /* Calpella */
74#define    MEI_DEV_ID_IBXPK_2	0x3B65  /* Calpella */
75
76#define    MEI_DEV_ID_CPT_1	0x1C3A    /* Cougerpoint */
77#define    MEI_DEV_ID_PBG_1	0x1D3A    /* PBG */
78
79#define    MEI_DEV_ID_PPT_1	0x1E3A    /* Pantherpoint PPT */
80#define    MEI_DEV_ID_PPT_2	0x1CBA    /* Pantherpoint PPT */
81#define    MEI_DEV_ID_PPT_3	0x1DBA    /* Pantherpoint PPT */
82
83
84/*
85 * MEI HW Section
86 */
87
88/* MEI registers */
89/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
90#define H_CB_WW    0
91/* H_CSR - Host Control Status register */
92#define H_CSR      4
93/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
94#define ME_CB_RW   8
95/* ME_CSR_HA - ME Control Status Host Access register (read only) */
96#define ME_CSR_HA  0xC
97
98
99/* register bits of H_CSR (Host Control Status register) */
100/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
101#define H_CBD             0xFF000000
102/* Host Circular Buffer Write Pointer */
103#define H_CBWP            0x00FF0000
104/* Host Circular Buffer Read Pointer */
105#define H_CBRP            0x0000FF00
106/* Host Reset */
107#define H_RST             0x00000010
108/* Host Ready */
109#define H_RDY             0x00000008
110/* Host Interrupt Generate */
111#define H_IG              0x00000004
112/* Host Interrupt Status */
113#define H_IS              0x00000002
114/* Host Interrupt Enable */
115#define H_IE              0x00000001
116
117
118/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
119/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
120access to ME_CBD */
121#define ME_CBD_HRA        0xFF000000
122/* ME CB Write Pointer HRA - host read only access to ME_CBWP */
123#define ME_CBWP_HRA       0x00FF0000
124/* ME CB Read Pointer HRA - host read only access to ME_CBRP */
125#define ME_CBRP_HRA       0x0000FF00
126/* ME Reset HRA - host read only access to ME_RST */
127#define ME_RST_HRA        0x00000010
128/* ME Ready HRA - host read only access to ME_RDY */
129#define ME_RDY_HRA        0x00000008
130/* ME Interrupt Generate HRA - host read only access to ME_IG */
131#define ME_IG_HRA         0x00000004
132/* ME Interrupt Status HRA - host read only access to ME_IS */
133#define ME_IS_HRA         0x00000002
134/* ME Interrupt Enable HRA - host read only access to ME_IE */
135#define ME_IE_HRA         0x00000001
136
137/*
138 * MEI Version
139 */
140#define HBM_MINOR_VERSION                   0
141#define HBM_MAJOR_VERSION                   1
142#define HBM_TIMEOUT                         1	/* 1 second */
143
144/* Host bus message command opcode */
145#define MEI_HBM_CMD_OP_MSK                  0x7f
146/* Host bus message command RESPONSE */
147#define MEI_HBM_CMD_RES_MSK                 0x80
148
149/*
150 * MEI Bus Message Command IDs
151 */
152#define HOST_START_REQ_CMD                  0x01
153#define HOST_START_RES_CMD                  0x81
154
155#define HOST_STOP_REQ_CMD                   0x02
156#define HOST_STOP_RES_CMD                   0x82
157
158#define ME_STOP_REQ_CMD                     0x03
159
160#define HOST_ENUM_REQ_CMD                   0x04
161#define HOST_ENUM_RES_CMD                   0x84
162
163#define HOST_CLIENT_PROPERTIES_REQ_CMD      0x05
164#define HOST_CLIENT_PROPERTIES_RES_CMD      0x85
165
166#define CLIENT_CONNECT_REQ_CMD              0x06
167#define CLIENT_CONNECT_RES_CMD              0x86
168
169#define CLIENT_DISCONNECT_REQ_CMD           0x07
170#define CLIENT_DISCONNECT_RES_CMD           0x87
171
172#define MEI_FLOW_CONTROL_CMD                0x08
173
174/*
175 * MEI Stop Reason
176 * used by hbm_host_stop_request.reason
177 */
178enum mei_stop_reason_types {
179	DRIVER_STOP_REQUEST = 0x00,
180	DEVICE_D1_ENTRY = 0x01,
181	DEVICE_D2_ENTRY = 0x02,
182	DEVICE_D3_ENTRY = 0x03,
183	SYSTEM_S1_ENTRY = 0x04,
184	SYSTEM_S2_ENTRY = 0x05,
185	SYSTEM_S3_ENTRY = 0x06,
186	SYSTEM_S4_ENTRY = 0x07,
187	SYSTEM_S5_ENTRY = 0x08
188};
189
190/*
191 * Client Connect Status
192 * used by hbm_client_connect_response.status
193 */
194enum client_connect_status_types {
195	CCS_SUCCESS = 0x00,
196	CCS_NOT_FOUND = 0x01,
197	CCS_ALREADY_STARTED = 0x02,
198	CCS_OUT_OF_RESOURCES = 0x03,
199	CCS_MESSAGE_SMALL = 0x04
200};
201
202/*
203 * Client Disconnect Status
204 */
205enum client_disconnect_status_types {
206	CDS_SUCCESS = 0x00
207};
208
209/*
210 *  MEI BUS Interface Section
211 */
212struct mei_msg_hdr {
213	u32 me_addr:8;
214	u32 host_addr:8;
215	u32 length:9;
216	u32 reserved:6;
217	u32 msg_complete:1;
218} __packed;
219
220
221struct mei_bus_message {
222	u8 hbm_cmd;
223	u8 data[0];
224} __packed;
225
226struct hbm_version {
227	u8 minor_version;
228	u8 major_version;
229} __packed;
230
231struct hbm_host_version_request {
232	u8 hbm_cmd;
233	u8 reserved;
234	struct hbm_version host_version;
235} __packed;
236
237struct hbm_host_version_response {
238	u8 hbm_cmd;
239	u8 host_version_supported;
240	struct hbm_version me_max_version;
241} __packed;
242
243struct hbm_host_stop_request {
244	u8 hbm_cmd;
245	u8 reason;
246	u8 reserved[2];
247} __packed;
248
249struct hbm_host_stop_response {
250	u8 hbm_cmd;
251	u8 reserved[3];
252} __packed;
253
254struct hbm_me_stop_request {
255	u8 hbm_cmd;
256	u8 reason;
257	u8 reserved[2];
258} __packed;
259
260struct hbm_host_enum_request {
261	u8 hbm_cmd;
262	u8 reserved[3];
263} __packed;
264
265struct hbm_host_enum_response {
266	u8 hbm_cmd;
267	u8 reserved[3];
268	u8 valid_addresses[32];
269} __packed;
270
271struct mei_client_properties {
272	uuid_le protocol_name;
273	u8 protocol_version;
274	u8 max_number_of_connections;
275	u8 fixed_address;
276	u8 single_recv_buf;
277	u32 max_msg_length;
278} __packed;
279
280struct hbm_props_request {
281	u8 hbm_cmd;
282	u8 address;
283	u8 reserved[2];
284} __packed;
285
286
287struct hbm_props_response {
288	u8 hbm_cmd;
289	u8 address;
290	u8 status;
291	u8 reserved[1];
292	struct mei_client_properties client_properties;
293} __packed;
294
295struct hbm_client_connect_request {
296	u8 hbm_cmd;
297	u8 me_addr;
298	u8 host_addr;
299	u8 reserved;
300} __packed;
301
302struct hbm_client_connect_response {
303	u8 hbm_cmd;
304	u8 me_addr;
305	u8 host_addr;
306	u8 status;
307} __packed;
308
309struct hbm_client_disconnect_request {
310	u8 hbm_cmd;
311	u8 me_addr;
312	u8 host_addr;
313	u8 reserved[1];
314} __packed;
315
316#define MEI_FC_MESSAGE_RESERVED_LENGTH           5
317
318struct hbm_flow_control {
319	u8 hbm_cmd;
320	u8 me_addr;
321	u8 host_addr;
322	u8 reserved[MEI_FC_MESSAGE_RESERVED_LENGTH];
323} __packed;
324
325struct mei_me_client {
326	struct mei_client_properties props;
327	u8 client_id;
328	u8 mei_flow_ctrl_creds;
329} __packed;
330
331
332#endif
333