r819xU_phy.h revision 8fc8598e61f6f384f3eaf1d9b09500c12af47b37 
1#ifndef _R819XU_PHY_H
2#define _R819XU_PHY_H
3
4/* Channel switch:The size of command tables for switch channel*/
5#define MAX_PRECMD_CNT 16
6#define MAX_RFDEPENDCMD_CNT 16
7#define MAX_POSTCMD_CNT 16
8
9typedef enum _SwChnlCmdID{
10	CmdID_End,
11	CmdID_SetTxPowerLevel,
12	CmdID_BBRegWrite10,
13	CmdID_WritePortUlong,
14	CmdID_WritePortUshort,
15	CmdID_WritePortUchar,
16	CmdID_RF_WriteReg,
17}SwChnlCmdID;
18
19/*--------------------------------Define structure--------------------------------*/
20/* 1. Switch channel related */
21typedef struct _SwChnlCmd{
22	SwChnlCmdID	CmdID;
23	u32			Para1;
24	u32			Para2;
25	u32			msDelay;
26}__attribute__ ((packed)) SwChnlCmd;
27
28extern u32 rtl819XMACPHY_Array_PG[];
29extern u32 rtl819XPHY_REG_1T2RArray[];
30extern u32 rtl819XAGCTAB_Array[];
31extern u32 rtl819XRadioA_Array[];
32extern u32 rtl819XRadioB_Array[];
33extern u32 rtl819XRadioC_Array[];
34extern u32 rtl819XRadioD_Array[];
35
36typedef enum _HW90_BLOCK{
37	HW90_BLOCK_MAC = 0,
38	HW90_BLOCK_PHY0 = 1,
39	HW90_BLOCK_PHY1 = 2,
40	HW90_BLOCK_RF = 3,
41	HW90_BLOCK_MAXIMUM = 4, // Never use this
42}HW90_BLOCK_E, *PHW90_BLOCK_E;
43
44typedef enum _RF90_RADIO_PATH{
45	RF90_PATH_A = 0,			//Radio Path A
46	RF90_PATH_B = 1,			//Radio Path B
47	RF90_PATH_C = 2,			//Radio Path C
48	RF90_PATH_D = 3,			//Radio Path D
49	RF90_PATH_MAX				//Max RF number 92 support
50}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
51
52#define bMaskByte0                0xff
53#define bMaskByte1                0xff00
54#define bMaskByte2                0xff0000
55#define bMaskByte3                0xff000000
56#define bMaskHWord                0xffff0000
57#define bMaskLWord                0x0000ffff
58#define bMaskDWord                0xffffffff
59
60//extern u32 rtl8192_CalculateBitShift(u32 dwBitMask);
61extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath);
62extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData);
63extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask);
64//extern u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
65//extern void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
66extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
67extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
68extern void rtl8192_phy_configmac(struct net_device* dev);
69extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType);
70//extern void rtl8192_InitBBRFRegDef(struct net_device* dev);
71extern u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
72//extern void rtl8192_BB_Config_ParaFile(struct net_device* dev);
73extern void rtl8192_BBConfig(struct net_device* dev);
74extern void rtl8192_phy_getTxPower(struct net_device* dev);
75extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
76extern void rtl8192_phy_RFConfig(struct net_device* dev);
77extern void rtl8192_phy_updateInitGain(struct net_device* dev);
78extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E	eRFPath);
79
80extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel);
81extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH	Bandwidth, HT_EXTCHNL_OFFSET Offset);
82extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
83void rtl8192_SetBWModeWorkItem(struct net_device *dev);
84extern bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState);
85//added by amy
86extern void InitialGain819xUsb(struct net_device *dev,	u8 Operation);
87
88#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
89extern void InitialGainOperateWorkItemCallBack(struct work_struct *work);
90#else
91extern void InitialGainOperateWorkItemCallBack(struct net_device *dev);
92#endif
93
94#endif
95