rtsx_chip.c revision 1035117d2a47583f9539c28bf6ce5f677946e172
1/* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * wwang (wei_wang@realsil.com.cn) 20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 21 */ 22 23#include <linux/blkdev.h> 24#include <linux/kthread.h> 25#include <linux/sched.h> 26#include <linux/workqueue.h> 27#include <linux/vmalloc.h> 28 29#include "rtsx.h" 30#include "rtsx_transport.h" 31#include "rtsx_scsi.h" 32#include "rtsx_card.h" 33#include "rtsx_chip.h" 34#include "rtsx_sys.h" 35#include "general.h" 36 37#include "sd.h" 38#include "xd.h" 39#include "ms.h" 40 41static void rtsx_calibration(struct rtsx_chip *chip) 42{ 43 rtsx_write_phy_register(chip, 0x1B, 0x135E); 44 wait_timeout(10); 45 rtsx_write_phy_register(chip, 0x00, 0x0280); 46 rtsx_write_phy_register(chip, 0x01, 0x7112); 47 rtsx_write_phy_register(chip, 0x01, 0x7110); 48 rtsx_write_phy_register(chip, 0x01, 0x7112); 49 rtsx_write_phy_register(chip, 0x01, 0x7113); 50 rtsx_write_phy_register(chip, 0x00, 0x0288); 51} 52 53void rtsx_disable_card_int(struct rtsx_chip *chip) 54{ 55 u32 reg = rtsx_readl(chip, RTSX_BIER); 56 57 reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN); 58 rtsx_writel(chip, RTSX_BIER, reg); 59} 60 61void rtsx_enable_card_int(struct rtsx_chip *chip) 62{ 63 u32 reg = rtsx_readl(chip, RTSX_BIER); 64 int i; 65 66 for (i = 0; i <= chip->max_lun; i++) { 67 if (chip->lun2card[i] & XD_CARD) 68 reg |= XD_INT_EN; 69 if (chip->lun2card[i] & SD_CARD) 70 reg |= SD_INT_EN; 71 if (chip->lun2card[i] & MS_CARD) 72 reg |= MS_INT_EN; 73 } 74 if (chip->hw_bypass_sd) 75 reg &= ~((u32)SD_INT_EN); 76 77 rtsx_writel(chip, RTSX_BIER, reg); 78} 79 80void rtsx_enable_bus_int(struct rtsx_chip *chip) 81{ 82 u32 reg = 0; 83#ifndef DISABLE_CARD_INT 84 int i; 85#endif 86 87 reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN; 88 89#ifndef DISABLE_CARD_INT 90 for (i = 0; i <= chip->max_lun; i++) { 91 RTSX_DEBUGP("lun2card[%d] = 0x%02x\n", i, chip->lun2card[i]); 92 93 if (chip->lun2card[i] & XD_CARD) 94 reg |= XD_INT_EN; 95 if (chip->lun2card[i] & SD_CARD) 96 reg |= SD_INT_EN; 97 if (chip->lun2card[i] & MS_CARD) 98 reg |= MS_INT_EN; 99 } 100 if (chip->hw_bypass_sd) 101 reg &= ~((u32)SD_INT_EN); 102#endif 103 104 if (chip->ic_version >= IC_VER_C) 105 reg |= DELINK_INT_EN; 106#ifdef SUPPORT_OCP 107 if (CHECK_PID(chip, 0x5209)) { 108 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 109 reg |= MS_OC_INT_EN | SD_OC_INT_EN; 110 } else { 111 reg |= SD_OC_INT_EN; 112 } 113 } else { 114 reg |= OC_INT_EN; 115 } 116#endif 117 if (!chip->adma_mode) 118 reg |= DATA_DONE_INT_EN; 119 120 /* Enable Bus Interrupt */ 121 rtsx_writel(chip, RTSX_BIER, reg); 122 123 RTSX_DEBUGP("RTSX_BIER: 0x%08x\n", reg); 124} 125 126void rtsx_disable_bus_int(struct rtsx_chip *chip) 127{ 128 rtsx_writel(chip, RTSX_BIER, 0); 129} 130 131static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip) 132{ 133 if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) { 134 if (chip->asic_code) { 135 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 136 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU); 137 } else { 138 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, FPGA_SD_PULL_CTL_EN); 139 } 140 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD); 141 142 /* Enable SDIO internal clock */ 143 RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01); 144 145 RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF, SDIO_BUS_CTRL | SDIO_CD_CTRL); 146 147 chip->sd_int = 1; 148 chip->sd_io = 1; 149 } else { 150 chip->need_reset |= SD_CARD; 151 } 152 153 return STATUS_SUCCESS; 154} 155 156#ifdef HW_AUTO_SWITCH_SD_BUS 157static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) 158{ 159 u8 tmp; 160 int sw_bypass_sd = 0; 161 int retval; 162 163 if (chip->driver_first_load) { 164 if (CHECK_PID(chip, 0x5288)) { 165 RTSX_READ_REG(chip, 0xFE5A, &tmp); 166 if (tmp & 0x08) 167 sw_bypass_sd = 1; 168 } else if (CHECK_PID(chip, 0x5208)) { 169 RTSX_READ_REG(chip, 0xFE70, &tmp); 170 if (tmp & 0x80) 171 sw_bypass_sd = 1; 172 } else if (CHECK_PID(chip, 0x5209)) { 173 RTSX_READ_REG(chip, SDIO_CFG, &tmp); 174 if (tmp & SDIO_BUS_AUTO_SWITCH) 175 sw_bypass_sd = 1; 176 } 177 } else { 178 if (chip->sdio_in_charge) 179 sw_bypass_sd = 1; 180 } 181 RTSX_DEBUGP("chip->sdio_in_charge = %d\n", chip->sdio_in_charge); 182 RTSX_DEBUGP("chip->driver_first_load = %d\n", chip->driver_first_load); 183 RTSX_DEBUGP("sw_bypass_sd = %d\n", sw_bypass_sd); 184 185 if (sw_bypass_sd) { 186 u8 cd_toggle_mask = 0; 187 188 RTSX_READ_REG(chip, TLPTISTAT, &tmp); 189 if (CHECK_PID(chip, 0x5209)) { 190 cd_toggle_mask = 0x10; 191 } else { 192 cd_toggle_mask = 0x08; 193 } 194 if (tmp & cd_toggle_mask) { 195 /* Disable sdio_bus_auto_switch */ 196 if (CHECK_PID(chip, 0x5288)) { 197 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00); 198 } else if (CHECK_PID(chip, 0x5208)) { 199 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00); 200 } else { 201 RTSX_WRITE_REG(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, 0); 202 } 203 RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp); 204 205 chip->need_reset |= SD_CARD; 206 } else { 207 RTSX_DEBUGP("Chip inserted with SDIO!\n"); 208 209 if (chip->asic_code) { 210 retval = sd_pull_ctl_enable(chip); 211 if (retval != STATUS_SUCCESS) { 212 TRACE_RET(chip, STATUS_FAIL); 213 } 214 } else { 215 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0); 216 } 217 retval = card_share_mode(chip, SD_CARD); 218 if (retval != STATUS_SUCCESS) { 219 TRACE_RET(chip, STATUS_FAIL); 220 } 221 222 /* Enable sdio_bus_auto_switch */ 223 if (CHECK_PID(chip, 0x5288)) { 224 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08); 225 } else if (CHECK_PID(chip, 0x5208)) { 226 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80); 227 } else { 228 RTSX_WRITE_REG(chip, SDIO_CFG, 229 SDIO_BUS_AUTO_SWITCH, SDIO_BUS_AUTO_SWITCH); 230 } 231 chip->chip_insert_with_sdio = 1; 232 chip->sd_io = 1; 233 } 234 } else { 235 if (CHECK_PID(chip, 0x5209)) { 236 RTSX_WRITE_REG(chip, TLPTISTAT, 0x10, 0x10); 237 } else { 238 RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08); 239 } 240 chip->need_reset |= SD_CARD; 241 } 242 243 return STATUS_SUCCESS; 244} 245#endif 246 247int rtsx_reset_chip(struct rtsx_chip *chip) 248{ 249 int retval; 250 251 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr); 252 253 rtsx_disable_aspm(chip); 254 255 if (CHECK_PID(chip, 0x5209) && chip->asic_code) { 256 u16 val; 257 258 /* optimize PHY */ 259 retval = rtsx_write_phy_register(chip, 0x00, 0xB966); 260 if (retval != STATUS_SUCCESS) { 261 TRACE_RET(chip, STATUS_FAIL); 262 } 263 retval = rtsx_write_phy_register(chip, 0x01, 0x713F); 264 if (retval != STATUS_SUCCESS) { 265 TRACE_RET(chip, STATUS_FAIL); 266 } 267 retval = rtsx_write_phy_register(chip, 0x03, 0xA549); 268 if (retval != STATUS_SUCCESS) { 269 TRACE_RET(chip, STATUS_FAIL); 270 } 271 retval = rtsx_write_phy_register(chip, 0x06, 0xB235); 272 if (retval != STATUS_SUCCESS) { 273 TRACE_RET(chip, STATUS_FAIL); 274 } 275 retval = rtsx_write_phy_register(chip, 0x07, 0xEF40); 276 if (retval != STATUS_SUCCESS) { 277 TRACE_RET(chip, STATUS_FAIL); 278 } 279 retval = rtsx_write_phy_register(chip, 0x1E, 0xF8EB); 280 if (retval != STATUS_SUCCESS) { 281 TRACE_RET(chip, STATUS_FAIL); 282 } 283 retval = rtsx_write_phy_register(chip, 0x19, 0xFE6C); 284 if (retval != STATUS_SUCCESS) { 285 TRACE_RET(chip, STATUS_FAIL); 286 } 287 wait_timeout(1); 288 retval = rtsx_write_phy_register(chip, 0x0A, 0x05C0); 289 if (retval != STATUS_SUCCESS) { 290 TRACE_RET(chip, STATUS_FAIL); 291 } 292 293 retval = rtsx_write_cfg_dw(chip, 1, 0x110, 0xFFFF, 0xFFFF); 294 if (retval != STATUS_SUCCESS) { 295 TRACE_RET(chip, STATUS_FAIL); 296 } 297 298 retval = rtsx_read_phy_register(chip, 0x08, &val); 299 if (retval != STATUS_SUCCESS) { 300 TRACE_RET(chip, STATUS_FAIL); 301 } 302 RTSX_DEBUGP("Read from phy 0x08: 0x%04x\n", val); 303 304 if (chip->phy_voltage) { 305 chip->phy_voltage &= 0x3F; 306 RTSX_DEBUGP("chip->phy_voltage = 0x%x\n", chip->phy_voltage); 307 val &= ~0x3F; 308 val |= chip->phy_voltage; 309 RTSX_DEBUGP("Write to phy 0x08: 0x%04x\n", val); 310 retval = rtsx_write_phy_register(chip, 0x08, val); 311 if (retval != STATUS_SUCCESS) { 312 TRACE_RET(chip, STATUS_FAIL); 313 } 314 } else { 315 chip->phy_voltage = (u8)(val & 0x3F); 316 RTSX_DEBUGP("Default, chip->phy_voltage = 0x%x\n", chip->phy_voltage); 317 } 318 } 319 320 RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00); 321 322 /* Disable card clock */ 323 RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0); 324 325#ifdef SUPPORT_OCP 326 /* SSC power on, OCD power on */ 327 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 328 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0); 329 } else { 330 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN); 331 } 332 if (CHECK_PID(chip, 0x5209)) { 333 RTSX_WRITE_REG(chip, OCPPARA1, SD_OCP_TIME_MASK | MS_OCP_TIME_MASK, 334 SD_OCP_TIME_800 | MS_OCP_TIME_800); 335 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK | MS_OCP_THD_MASK, 336 chip->sd_400mA_ocp_thd | (chip->ms_ocp_thd << 4)); 337 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 338 RTSX_WRITE_REG(chip, OCPGLITCH, SD_OCP_GLITCH_MASK | MS_OCP_GLITCH_MASK, 339 SD_OCP_GLITCH_10000 | MS_OCP_GLITCH_10000); 340 } else { 341 RTSX_WRITE_REG(chip, OCPGLITCH, SD_OCP_GLITCH_MASK, SD_OCP_GLITCH_10000); 342 } 343 RTSX_WRITE_REG(chip, OCPCTL, 0xFF, 344 SD_OCP_INT_EN | SD_DETECT_EN | MS_OCP_INT_EN | MS_DETECT_EN); 345 } else { 346 RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800); 347 RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946); 348 RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN); 349 } 350#else 351 /* OC power down */ 352 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN); 353#endif 354 355 if (!CHECK_PID(chip, 0x5288)) { 356 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03); 357 } 358 359 /* Turn off LED */ 360 RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03); 361 362 /* Reset delink mode */ 363 RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0); 364 365 /* Card driving select */ 366 RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel); 367 if (CHECK_PID(chip, 0x5209)) { 368 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3); 369 } 370 371#ifdef LED_AUTO_BLINK 372 RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF, 373 LED_BLINK_SPEED | BLINK_EN | LED_GPIO0); 374#endif 375 376 if (chip->asic_code) { 377 /* Enable SSC Clock */ 378 RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M); 379 RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12); 380 } 381 382 /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0) 383 0xFE5B 384 bit[1] u_cd_rst_core_en rst_value = 0 385 bit[2] u_force_rst_core_en rst_value = 0 386 bit[5] u_mac_phy_rst_n_dbg rst_value = 1 387 bit[4] u_non_sticky_rst_n_dbg rst_value = 0 388 */ 389 RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10); 390 391 /* Enable ASPM */ 392 if (chip->aspm_l0s_l1_en) { 393 if (chip->dynamic_aspm) { 394 if (CHK_SDIO_EXIST(chip)) { 395 if (CHECK_PID(chip, 0x5209)) { 396 retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en); 397 if (retval != STATUS_SUCCESS) { 398 TRACE_RET(chip, STATUS_FAIL); 399 } 400 } else if (CHECK_PID(chip, 0x5288)) { 401 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en); 402 if (retval != STATUS_SUCCESS) { 403 TRACE_RET(chip, STATUS_FAIL); 404 } 405 } 406 } 407 } else { 408 if (CHECK_PID(chip, 0x5208)) { 409 RTSX_WRITE_REG(chip, ASPM_FORCE_CTL, 0xFF, 0x3F); 410 } 411 412 retval = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en); 413 if (retval != STATUS_SUCCESS) { 414 TRACE_RET(chip, STATUS_FAIL); 415 } 416 chip->aspm_level[0] = chip->aspm_l0s_l1_en; 417 if (CHK_SDIO_EXIST(chip)) { 418 chip->aspm_level[1] = chip->aspm_l0s_l1_en; 419 if (CHECK_PID(chip, 0x5288)) { 420 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en); 421 } else { 422 retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en); 423 } 424 if (retval != STATUS_SUCCESS) { 425 TRACE_RET(chip, STATUS_FAIL); 426 } 427 } 428 429 chip->aspm_enabled = 1; 430 } 431 } else { 432 if (chip->asic_code && CHECK_PID(chip, 0x5208)) { 433 retval = rtsx_write_phy_register(chip, 0x07, 0x0129); 434 if (retval != STATUS_SUCCESS) { 435 TRACE_RET(chip, STATUS_FAIL); 436 } 437 } 438 retval = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en); 439 if (retval != STATUS_SUCCESS) { 440 TRACE_RET(chip, STATUS_FAIL); 441 } 442 } 443 444 retval = rtsx_write_config_byte(chip, 0x81, 1); 445 if (retval != STATUS_SUCCESS) { 446 TRACE_RET(chip, STATUS_FAIL); 447 } 448 449 if (CHK_SDIO_EXIST(chip)) { 450 if (CHECK_PID(chip, 0x5288)) { 451 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100); 452 } else { 453 retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100); 454 } 455 if (retval != STATUS_SUCCESS) { 456 TRACE_RET(chip, STATUS_FAIL); 457 } 458 } 459 460 if (CHECK_PID(chip, 0x5209)) { 461 retval = rtsx_write_cfg_dw(chip, 0, 0x70C, 0xFF000000, 0x5B); 462 if (retval != STATUS_SUCCESS) { 463 TRACE_RET(chip, STATUS_FAIL); 464 } 465 } 466 467 if (CHECK_PID(chip, 0x5288)) { 468 if (!CHK_SDIO_EXIST(chip)) { 469 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103); 470 if (retval != STATUS_SUCCESS) { 471 TRACE_RET(chip, STATUS_FAIL); 472 } 473 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03); 474 if (retval != STATUS_SUCCESS) { 475 TRACE_RET(chip, STATUS_FAIL); 476 } 477 } 478 } 479 480 RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); 481 482 RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); 483 484 if (CHECK_PID(chip, 0x5209)) { 485 RTSX_WRITE_REG(chip, PWD_SUSPEND_EN, 0xFF, 0xFF); 486 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, PWR_GATE_EN, PWR_GATE_EN); 487 } 488 489 /* Enable PCIE interrupt */ 490 if (chip->asic_code) { 491 if (CHECK_PID(chip, 0x5208)) { 492 if (chip->phy_debug_mode) { 493 RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0); 494 rtsx_disable_bus_int(chip); 495 } else { 496 rtsx_enable_bus_int(chip); 497 } 498 499 if (chip->ic_version >= IC_VER_D) { 500 u16 reg; 501 retval = rtsx_read_phy_register(chip, 0x00, ®); 502 if (retval != STATUS_SUCCESS) { 503 TRACE_RET(chip, STATUS_FAIL); 504 } 505 reg &= 0xFE7F; 506 reg |= 0x80; 507 retval = rtsx_write_phy_register(chip, 0x00, reg); 508 if (retval != STATUS_SUCCESS) { 509 TRACE_RET(chip, STATUS_FAIL); 510 } 511 retval = rtsx_read_phy_register(chip, 0x1C, ®); 512 if (retval != STATUS_SUCCESS) { 513 TRACE_RET(chip, STATUS_FAIL); 514 } 515 reg &= 0xFFF7; 516 retval = rtsx_write_phy_register(chip, 0x1C, reg); 517 if (retval != STATUS_SUCCESS) { 518 TRACE_RET(chip, STATUS_FAIL); 519 } 520 } 521 522 if (chip->driver_first_load && (chip->ic_version < IC_VER_C)) { 523 rtsx_calibration(chip); 524 } 525 } else { 526 rtsx_enable_bus_int(chip); 527 } 528 } else { 529 rtsx_enable_bus_int(chip); 530 } 531 532#ifdef HW_INT_WRITE_CLR 533 if (CHECK_PID(chip, 0x5209)) { 534 /* Set interrupt write clear */ 535 RTSX_WRITE_REG(chip, NFTS_TX_CTRL, 0x02, 0); 536 } 537#endif 538 539 chip->need_reset = 0; 540 541 chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 542#ifdef HW_INT_WRITE_CLR 543 if (CHECK_PID(chip, 0x5209)) { 544 /* Clear interrupt flag */ 545 rtsx_writel(chip, RTSX_BIPR, chip->int_reg); 546 } 547#endif 548 if (chip->hw_bypass_sd) 549 goto NextCard; 550 RTSX_DEBUGP("In rtsx_reset_chip, chip->int_reg = 0x%x\n", chip->int_reg); 551 if (chip->int_reg & SD_EXIST) { 552#ifdef HW_AUTO_SWITCH_SD_BUS 553 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C)) { 554 retval = rtsx_pre_handle_sdio_old(chip); 555 } else { 556 retval = rtsx_pre_handle_sdio_new(chip); 557 } 558 RTSX_DEBUGP("chip->need_reset = 0x%x (rtsx_reset_chip)\n", (unsigned int)(chip->need_reset)); 559#else /* HW_AUTO_SWITCH_SD_BUS */ 560 retval = rtsx_pre_handle_sdio_old(chip); 561#endif /* HW_AUTO_SWITCH_SD_BUS */ 562 if (retval != STATUS_SUCCESS) { 563 TRACE_RET(chip, STATUS_FAIL); 564 } 565 } else { 566 chip->sd_io = 0; 567 RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL, 0); 568 } 569 570NextCard: 571 if (chip->int_reg & XD_EXIST) 572 chip->need_reset |= XD_CARD; 573 if (chip->int_reg & MS_EXIST) 574 chip->need_reset |= MS_CARD; 575 if (chip->int_reg & CARD_EXIST) { 576 RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB); 577 } 578 579 RTSX_DEBUGP("In rtsx_init_chip, chip->need_reset = 0x%x\n", (unsigned int)(chip->need_reset)); 580 581 RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00); 582 583 if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) { 584 /* Turn off main power when entering S3/S4 state */ 585 RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03); 586 } 587 588 if (chip->remote_wakeup_en && !chip->auto_delink_en) { 589 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07); 590 if (chip->aux_pwr_exist) { 591 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33); 592 } 593 } else { 594 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04); 595 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30); 596 } 597 598 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) { 599 RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14); 600 } else if (CHECK_PID(chip, 0x5209)) { 601 if (chip->force_clkreq_0) { 602 RTSX_WRITE_REG(chip, PETXCFG, 0x08, 0x08); 603 } else { 604 RTSX_WRITE_REG(chip, PETXCFG, 0x08, 0x00); 605 } 606 } 607 608 if (chip->asic_code && CHECK_PID(chip, 0x5208)) { 609 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2); 610 if (retval != STATUS_SUCCESS) { 611 TRACE_RET(chip, STATUS_FAIL); 612 } 613 } 614 615 if (chip->ft2_fast_mode) { 616 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON); 617 udelay(chip->pmos_pwr_on_interval); 618 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, MS_POWER_ON | SD_POWER_ON); 619 620 wait_timeout(200); 621 } 622 623 /* Reset card */ 624 rtsx_reset_detected_cards(chip, 0); 625 626 chip->driver_first_load = 0; 627 628 return STATUS_SUCCESS; 629} 630 631static inline int check_sd_speed_prior(u32 sd_speed_prior) 632{ 633 int i, fake_para = 0; 634 635 for (i = 0; i < 4; i++) { 636 u8 tmp = (u8)(sd_speed_prior >> (i*8)); 637 if ((tmp < 0x01) || (tmp > 0x04)) { 638 fake_para = 1; 639 break; 640 } 641 } 642 643 return !fake_para; 644} 645 646static inline int check_sd_current_prior(u32 sd_current_prior) 647{ 648 int i, fake_para = 0; 649 650 for (i = 0; i < 4; i++) { 651 u8 tmp = (u8)(sd_current_prior >> (i*8)); 652 if (tmp > 0x03) { 653 fake_para = 1; 654 break; 655 } 656 } 657 658 return !fake_para; 659} 660 661static int rts5209_init(struct rtsx_chip *chip) 662{ 663 int retval; 664 u32 lval = 0; 665 u8 val = 0; 666 667 val = rtsx_readb(chip, 0x1C); 668 if ((val & 0x10) == 0) { 669 chip->asic_code = 1; 670 } else { 671 chip->asic_code = 0; 672 } 673 674 chip->ic_version = val & 0x0F; 675 chip->phy_debug_mode = 0; 676 677 chip->aux_pwr_exist = 0; 678 679 chip->ms_power_class_en = 0x03; 680 681 retval = rtsx_read_cfg_dw(chip, 0, 0x724, &lval); 682 if (retval != STATUS_SUCCESS) { 683 TRACE_RET(chip, STATUS_FAIL); 684 } 685 RTSX_DEBUGP("dw in 0x724: 0x%x\n", lval); 686 val = (u8)lval; 687 if (!(val & 0x80)) { 688 if (val & 0x08) 689 chip->lun_mode = DEFAULT_SINGLE; 690 else 691 chip->lun_mode = SD_MS_2LUN; 692 693 if (val & 0x04) { 694 SET_SDIO_EXIST(chip); 695 } else { 696 CLR_SDIO_EXIST(chip); 697 } 698 699 if (val & 0x02) { 700 chip->hw_bypass_sd = 0; 701 } else { 702 chip->hw_bypass_sd = 1; 703 } 704 } else { 705 SET_SDIO_EXIST(chip); 706 chip->hw_bypass_sd = 0; 707 } 708 709 if (chip->use_hw_setting) { 710 u8 clk; 711 712 chip->aspm_l0s_l1_en = (val >> 5) & 0x03; 713 714 val = (u8)(lval >> 8); 715 716 clk = (val >> 5) & 0x07; 717 if (clk != 0x07) { 718 chip->asic_sd_sdr50_clk = 98 - clk * 2; 719 } 720 721 if (val & 0x10) { 722 chip->auto_delink_en = 1; 723 } else { 724 chip->auto_delink_en = 0; 725 } 726 727 if (chip->ss_en == 2) { 728 chip->ss_en = 0; 729 } else { 730 if (val & 0x08) { 731 chip->ss_en = 1; 732 } else { 733 chip->ss_en = 0; 734 } 735 } 736 737 clk = val & 0x07; 738 if (clk != 0x07) 739 chip->asic_ms_hg_clk = (59 - clk) * 2; 740 741 val = (u8)(lval >> 16); 742 743 clk = (val >> 6) & 0x03; 744 if (clk != 0x03) { 745 chip->asic_sd_hs_clk = (49 - clk * 2) * 2; 746 chip->asic_mmc_52m_clk = (49 - clk * 2) * 2; 747 } 748 749 clk = (val >> 4) & 0x03; 750 if (clk != 0x03) 751 chip->asic_sd_ddr50_clk = (48 - clk * 2) * 2; 752 753 if (val & 0x01) { 754 chip->sdr104_en = 1; 755 } else { 756 chip->sdr104_en = 0; 757 } 758 if (val & 0x02) { 759 chip->ddr50_en = 1; 760 } else { 761 chip->ddr50_en = 0; 762 } 763 if (val & 0x04) { 764 chip->sdr50_en = 1; 765 } else { 766 chip->sdr50_en = 0; 767 } 768 769 val = (u8)(lval >> 24); 770 771 clk = (val >> 5) & 0x07; 772 if (clk != 0x07) 773 chip->asic_sd_sdr104_clk = 206 - clk * 3; 774 775 if (val & 0x10) { 776 chip->power_down_in_ss = 1; 777 } else { 778 chip->power_down_in_ss = 0; 779 } 780 781 chip->ms_power_class_en = val & 0x03; 782 } 783 784 if (chip->hp_watch_bios_hotplug && chip->auto_delink_en) { 785 u8 reg58, reg5b; 786 787 retval = rtsx_read_pci_cfg_byte(0x00, 788 0x1C, 0x02, 0x58, ®58); 789 if (retval < 0) { 790 return STATUS_SUCCESS; 791 } 792 retval = rtsx_read_pci_cfg_byte(0x00, 793 0x1C, 0x02, 0x5B, ®5b); 794 if (retval < 0) { 795 return STATUS_SUCCESS; 796 } 797 798 RTSX_DEBUGP("reg58 = 0x%x, reg5b = 0x%x\n", reg58, reg5b); 799 800 if ((reg58 == 0x00) && (reg5b == 0x01)) { 801 chip->auto_delink_en = 0; 802 } 803 } 804 805 return STATUS_SUCCESS; 806} 807 808static int rts5208_init(struct rtsx_chip *chip) 809{ 810 int retval; 811 u16 reg = 0; 812 u8 val = 0; 813 814 RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03); 815 RTSX_READ_REG(chip, CLK_SEL, &val); 816 if (val == 0) { 817 chip->asic_code = 1; 818 } else { 819 chip->asic_code = 0; 820 } 821 822 if (chip->asic_code) { 823 retval = rtsx_read_phy_register(chip, 0x1C, ®); 824 if (retval != STATUS_SUCCESS) { 825 TRACE_RET(chip, STATUS_FAIL); 826 } 827 RTSX_DEBUGP("Value of phy register 0x1C is 0x%x\n", reg); 828 chip->ic_version = (reg >> 4) & 0x07; 829 if (reg & PHY_DEBUG_MODE) { 830 chip->phy_debug_mode = 1; 831 } else { 832 chip->phy_debug_mode = 0; 833 } 834 } else { 835 RTSX_READ_REG(chip, 0xFE80, &val); 836 chip->ic_version = val; 837 chip->phy_debug_mode = 0; 838 } 839 840 RTSX_READ_REG(chip, PDINFO, &val); 841 RTSX_DEBUGP("PDINFO: 0x%x\n", val); 842 if (val & AUX_PWR_DETECTED) { 843 chip->aux_pwr_exist = 1; 844 } else { 845 chip->aux_pwr_exist = 0; 846 } 847 848 RTSX_READ_REG(chip, 0xFE50, &val); 849 if (val & 0x01) { 850 chip->hw_bypass_sd = 1; 851 } else { 852 chip->hw_bypass_sd = 0; 853 } 854 855 rtsx_read_config_byte(chip, 0x0E, &val); 856 if (val & 0x80) { 857 SET_SDIO_EXIST(chip); 858 } else { 859 CLR_SDIO_EXIST(chip); 860 } 861 862 if (chip->use_hw_setting) { 863 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val); 864 if (val & 0x80) { 865 chip->auto_delink_en = 1; 866 } else { 867 chip->auto_delink_en = 0; 868 } 869 } 870 871 return STATUS_SUCCESS; 872} 873 874static int rts5288_init(struct rtsx_chip *chip) 875{ 876 int retval; 877 u8 val = 0, max_func; 878 u32 lval = 0; 879 880 RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03); 881 RTSX_READ_REG(chip, CLK_SEL, &val); 882 if (val == 0) { 883 chip->asic_code = 1; 884 } else { 885 chip->asic_code = 0; 886 } 887 888 chip->ic_version = 0; 889 chip->phy_debug_mode = 0; 890 891 RTSX_READ_REG(chip, PDINFO, &val); 892 RTSX_DEBUGP("PDINFO: 0x%x\n", val); 893 if (val & AUX_PWR_DETECTED) { 894 chip->aux_pwr_exist = 1; 895 } else { 896 chip->aux_pwr_exist = 0; 897 } 898 899 RTSX_READ_REG(chip, CARD_SHARE_MODE, &val); 900 RTSX_DEBUGP("CARD_SHARE_MODE: 0x%x\n", val); 901 if (val & 0x04) { 902 chip->baro_pkg = QFN; 903 } else { 904 chip->baro_pkg = LQFP; 905 } 906 907 RTSX_READ_REG(chip, 0xFE5A, &val); 908 if (val & 0x10) { 909 chip->hw_bypass_sd = 1; 910 } else { 911 chip->hw_bypass_sd = 0; 912 } 913 914 retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval); 915 if (retval != STATUS_SUCCESS) { 916 TRACE_RET(chip, STATUS_FAIL); 917 } 918 max_func = (u8)((lval >> 29) & 0x07); 919 RTSX_DEBUGP("Max function number: %d\n", max_func); 920 if (max_func == 0x02) { 921 SET_SDIO_EXIST(chip); 922 } else { 923 CLR_SDIO_EXIST(chip); 924 } 925 926 if (chip->use_hw_setting) { 927 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val); 928 if (val & 0x80) { 929 chip->auto_delink_en = 1; 930 } else { 931 chip->auto_delink_en = 0; 932 } 933 934 if (CHECK_BARO_PKG(chip, LQFP)) { 935 chip->lun_mode = SD_MS_1LUN; 936 } else { 937 chip->lun_mode = DEFAULT_SINGLE; 938 } 939 } 940 941 return STATUS_SUCCESS; 942} 943 944int rtsx_init_chip(struct rtsx_chip *chip) 945{ 946 struct sd_info *sd_card = &(chip->sd_card); 947 struct xd_info *xd_card = &(chip->xd_card); 948 struct ms_info *ms_card = &(chip->ms_card); 949 int retval; 950 unsigned int i; 951 952 RTSX_DEBUGP("Vendor ID: 0x%04x, Product ID: 0x%04x\n", 953 chip->vendor_id, chip->product_id); 954 955 chip->ic_version = 0; 956 957#ifdef _MSG_TRACE 958 chip->msg_idx = 0; 959#endif 960 961 memset(xd_card, 0, sizeof(struct xd_info)); 962 memset(sd_card, 0, sizeof(struct sd_info)); 963 memset(ms_card, 0, sizeof(struct ms_info)); 964 965 chip->xd_reset_counter = 0; 966 chip->sd_reset_counter = 0; 967 chip->ms_reset_counter = 0; 968 969 chip->xd_show_cnt = MAX_SHOW_CNT; 970 chip->sd_show_cnt = MAX_SHOW_CNT; 971 chip->ms_show_cnt = MAX_SHOW_CNT; 972 973 chip->sd_io = 0; 974 chip->auto_delink_cnt = 0; 975 chip->auto_delink_allowed = 1; 976 rtsx_set_stat(chip, RTSX_STAT_INIT); 977 978 chip->aspm_enabled = 0; 979 chip->chip_insert_with_sdio = 0; 980 chip->sdio_aspm = 0; 981 chip->sdio_idle = 0; 982 chip->sdio_counter = 0; 983 chip->cur_card = 0; 984 chip->phy_debug_mode = 0; 985 chip->sdio_func_exist = 0; 986 memset(chip->sdio_raw_data, 0, 12); 987 988 for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) { 989 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE); 990 chip->rw_fail_cnt[i] = 0; 991 } 992 993 if (!check_sd_speed_prior(chip->sd_speed_prior)) { 994 chip->sd_speed_prior = 0x01040203; 995 } 996 RTSX_DEBUGP("sd_speed_prior = 0x%08x\n", chip->sd_speed_prior); 997 998 if (!check_sd_current_prior(chip->sd_current_prior)) { 999 chip->sd_current_prior = 0x00010203; 1000 } 1001 RTSX_DEBUGP("sd_current_prior = 0x%08x\n", chip->sd_current_prior); 1002 1003 if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0)) { 1004 chip->sd_ddr_tx_phase = 0; 1005 } 1006 if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0)) { 1007 chip->mmc_ddr_tx_phase = 0; 1008 } 1009 1010 RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0); 1011 wait_timeout(200); 1012 RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07); 1013 RTSX_DEBUGP("chip->use_hw_setting = %d\n", chip->use_hw_setting); 1014 1015 if (CHECK_PID(chip, 0x5209)) { 1016 retval = rts5209_init(chip); 1017 if (retval != STATUS_SUCCESS) { 1018 TRACE_RET(chip, STATUS_FAIL); 1019 } 1020 } else if (CHECK_PID(chip, 0x5208)) { 1021 retval = rts5208_init(chip); 1022 if (retval != STATUS_SUCCESS) { 1023 TRACE_RET(chip, STATUS_FAIL); 1024 } 1025 } else if (CHECK_PID(chip, 0x5288)) { 1026 retval = rts5288_init(chip); 1027 if (retval != STATUS_SUCCESS) { 1028 TRACE_RET(chip, STATUS_FAIL); 1029 } 1030 } 1031 1032 if (chip->ss_en == 2) { 1033 chip->ss_en = 0; 1034 } 1035 1036 RTSX_DEBUGP("chip->asic_code = %d\n", chip->asic_code); 1037 RTSX_DEBUGP("chip->ic_version = 0x%x\n", chip->ic_version); 1038 RTSX_DEBUGP("chip->phy_debug_mode = %d\n", chip->phy_debug_mode); 1039 RTSX_DEBUGP("chip->aux_pwr_exist = %d\n", chip->aux_pwr_exist); 1040 RTSX_DEBUGP("chip->sdio_func_exist = %d\n", chip->sdio_func_exist); 1041 RTSX_DEBUGP("chip->hw_bypass_sd = %d\n", chip->hw_bypass_sd); 1042 RTSX_DEBUGP("chip->aspm_l0s_l1_en = %d\n", chip->aspm_l0s_l1_en); 1043 RTSX_DEBUGP("chip->lun_mode = %d\n", chip->lun_mode); 1044 RTSX_DEBUGP("chip->auto_delink_en = %d\n", chip->auto_delink_en); 1045 RTSX_DEBUGP("chip->ss_en = %d\n", chip->ss_en); 1046 RTSX_DEBUGP("chip->baro_pkg = %d\n", chip->baro_pkg); 1047 1048 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 1049 chip->card2lun[SD_CARD] = 0; 1050 chip->card2lun[MS_CARD] = 1; 1051 chip->card2lun[XD_CARD] = 0xFF; 1052 chip->lun2card[0] = SD_CARD; 1053 chip->lun2card[1] = MS_CARD; 1054 chip->max_lun = 1; 1055 SET_SDIO_IGNORED(chip); 1056 } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) { 1057 chip->card2lun[SD_CARD] = 0; 1058 chip->card2lun[MS_CARD] = 0; 1059 chip->card2lun[XD_CARD] = 0xFF; 1060 chip->lun2card[0] = SD_CARD | MS_CARD; 1061 chip->max_lun = 0; 1062 } else { 1063 chip->card2lun[XD_CARD] = 0; 1064 chip->card2lun[SD_CARD] = 0; 1065 chip->card2lun[MS_CARD] = 0; 1066 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD; 1067 chip->max_lun = 0; 1068 } 1069 1070 retval = rtsx_reset_chip(chip); 1071 if (retval != STATUS_SUCCESS) { 1072 TRACE_RET(chip, STATUS_FAIL); 1073 } 1074 1075 return STATUS_SUCCESS; 1076} 1077 1078void rtsx_release_chip(struct rtsx_chip *chip) 1079{ 1080 xd_free_l2p_tbl(chip); 1081 ms_free_l2p_tbl(chip); 1082 chip->card_exist = 0; 1083 chip->card_ready = 0; 1084} 1085 1086#if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 1087static inline void rtsx_blink_led(struct rtsx_chip *chip) 1088{ 1089 if (chip->card_exist && chip->blink_led) { 1090 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) { 1091 chip->led_toggle_counter++; 1092 } else { 1093 chip->led_toggle_counter = 0; 1094 toggle_gpio(chip, LED_GPIO); 1095 } 1096 } 1097} 1098#endif 1099 1100static void rtsx_monitor_aspm_config(struct rtsx_chip *chip) 1101{ 1102 int maybe_support_aspm, reg_changed; 1103 u32 tmp = 0; 1104 u8 reg0 = 0, reg1 = 0; 1105 1106 maybe_support_aspm = 0; 1107 reg_changed = 0; 1108 rtsx_read_config_byte(chip, LCTLR, ®0); 1109 if (chip->aspm_level[0] != reg0) { 1110 reg_changed = 1; 1111 chip->aspm_level[0] = reg0; 1112 } 1113 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { 1114 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp); 1115 reg1 = (u8)tmp; 1116 if (chip->aspm_level[1] != reg1) { 1117 reg_changed = 1; 1118 chip->aspm_level[1] = reg1; 1119 } 1120 1121 if ((reg0 & 0x03) && (reg1 & 0x03)) { 1122 maybe_support_aspm = 1; 1123 } 1124 } else { 1125 if (reg0 & 0x03) { 1126 maybe_support_aspm = 1; 1127 } 1128 } 1129 1130 if (reg_changed) { 1131 if (maybe_support_aspm) { 1132 chip->aspm_l0s_l1_en = 0x03; 1133 } 1134 RTSX_DEBUGP("aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n", 1135 chip->aspm_level[0], chip->aspm_level[1]); 1136 1137 if (chip->aspm_l0s_l1_en) { 1138 chip->aspm_enabled = 1; 1139 } else { 1140 chip->aspm_enabled = 0; 1141 chip->sdio_aspm = 0; 1142 } 1143 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 1144 0x30 | chip->aspm_level[0] | (chip->aspm_level[1] << 2)); 1145 } 1146} 1147 1148void rtsx_polling_func(struct rtsx_chip *chip) 1149{ 1150#ifdef SUPPORT_SD_LOCK 1151 struct sd_info *sd_card = &(chip->sd_card); 1152#endif 1153 int ss_allowed; 1154 1155 if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND)) 1156 return; 1157 1158 if (rtsx_chk_stat(chip, RTSX_STAT_DELINK)) 1159 goto Delink_Stage; 1160 1161 if (chip->polling_config) { 1162 u8 val; 1163 rtsx_read_config_byte(chip, 0, &val); 1164 } 1165 1166 if (rtsx_chk_stat(chip, RTSX_STAT_SS)) 1167 return; 1168 1169#ifdef SUPPORT_OCP 1170 if (chip->ocp_int) { 1171 rtsx_read_register(chip, OCPSTAT, &(chip->ocp_stat)); 1172 1173 if (CHECK_PID(chip, 0x5209) && 1174 CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 1175 if (chip->ocp_int & SD_OC_INT) 1176 sd_power_off_card3v3(chip); 1177 if (chip->ocp_int & MS_OC_INT) 1178 ms_power_off_card3v3(chip); 1179 } else { 1180 if (chip->card_exist & SD_CARD) { 1181 sd_power_off_card3v3(chip); 1182 } else if (chip->card_exist & MS_CARD) { 1183 ms_power_off_card3v3(chip); 1184 } else if (chip->card_exist & XD_CARD) { 1185 xd_power_off_card3v3(chip); 1186 } 1187 } 1188 1189 chip->ocp_int = 0; 1190 } 1191#endif 1192 1193#ifdef SUPPORT_SD_LOCK 1194 if (sd_card->sd_erase_status) { 1195 if (chip->card_exist & SD_CARD) { 1196 u8 val; 1197 if (CHECK_PID(chip, 0x5209)) { 1198 rtsx_read_register(chip, SD_BUS_STAT, &val); 1199 if (val & SD_DAT0_STATUS) { 1200 sd_card->sd_erase_status = SD_NOT_ERASE; 1201 sd_card->sd_lock_notify = 1; 1202 chip->need_reinit |= SD_CARD; 1203 } 1204 } else { 1205 rtsx_read_register(chip, 0xFD30, &val); 1206 if (val & 0x02) { 1207 sd_card->sd_erase_status = SD_NOT_ERASE; 1208 sd_card->sd_lock_notify = 1; 1209 chip->need_reinit |= SD_CARD; 1210 } 1211 } 1212 } else { 1213 sd_card->sd_erase_status = SD_NOT_ERASE; 1214 } 1215 } 1216#endif 1217 1218 rtsx_init_cards(chip); 1219 1220 if (chip->ss_en) { 1221 ss_allowed = 1; 1222 1223 if (CHECK_PID(chip, 0x5288)) { 1224 ss_allowed = 0; 1225 } else { 1226 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { 1227 u32 val; 1228 rtsx_read_cfg_dw(chip, 1, 0x04, &val); 1229 if (val & 0x07) { 1230 ss_allowed = 0; 1231 } 1232 } 1233 } 1234 } else { 1235 ss_allowed = 0; 1236 } 1237 1238 if (ss_allowed && !chip->sd_io) { 1239 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) { 1240 chip->ss_counter = 0; 1241 } else { 1242 if (chip->ss_counter < 1243 (chip->ss_idle_period / POLLING_INTERVAL)) { 1244 chip->ss_counter++; 1245 } else { 1246 rtsx_exclusive_enter_ss(chip); 1247 return; 1248 } 1249 } 1250 } 1251 1252 if (CHECK_PID(chip, 0x5208)) { 1253 rtsx_monitor_aspm_config(chip); 1254 1255#ifdef SUPPORT_SDIO_ASPM 1256 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && 1257 chip->aspm_l0s_l1_en && chip->dynamic_aspm) { 1258 if (chip->sd_io) { 1259 dynamic_configure_sdio_aspm(chip); 1260 } else { 1261 if (!chip->sdio_aspm) { 1262 RTSX_DEBUGP("SDIO enter ASPM!\n"); 1263 rtsx_write_register(chip, 1264 ASPM_FORCE_CTL, 0xFC, 1265 0x30 | (chip->aspm_level[1] << 2)); 1266 chip->sdio_aspm = 1; 1267 } 1268 } 1269 } 1270#endif 1271 } 1272 1273 if (chip->idle_counter < IDLE_MAX_COUNT) { 1274 chip->idle_counter++; 1275 } else { 1276 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) { 1277 RTSX_DEBUGP("Idle state!\n"); 1278 rtsx_set_stat(chip, RTSX_STAT_IDLE); 1279 1280#if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 1281 chip->led_toggle_counter = 0; 1282#endif 1283 rtsx_force_power_on(chip, SSC_PDCTL); 1284 1285 turn_off_led(chip, LED_GPIO); 1286 1287 if (chip->auto_power_down && !chip->card_ready && !chip->sd_io) { 1288 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 1289 } 1290 } 1291 } 1292 1293 switch (rtsx_get_stat(chip)) { 1294 case RTSX_STAT_RUN: 1295#if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 1296 rtsx_blink_led(chip); 1297#endif 1298 do_remaining_work(chip); 1299 break; 1300 1301 case RTSX_STAT_IDLE: 1302 if (chip->sd_io && !chip->sd_int) { 1303 try_to_switch_sdio_ctrl(chip); 1304 } 1305 rtsx_enable_aspm(chip); 1306 break; 1307 1308 default: 1309 break; 1310 } 1311 1312 1313#ifdef SUPPORT_OCP 1314 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 1315#ifdef CONFIG_RTS_PSTOR_DEBUG 1316 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER)) { 1317 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat); 1318 } 1319#endif 1320 1321 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 1322 if (chip->card_exist & SD_CARD) { 1323 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 1324 card_power_off(chip, SD_CARD); 1325 chip->card_fail |= SD_CARD; 1326 } 1327 } 1328 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) { 1329 if (chip->card_exist & MS_CARD) { 1330 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 1331 card_power_off(chip, MS_CARD); 1332 chip->card_fail |= MS_CARD; 1333 } 1334 } 1335 } else { 1336 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 1337 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat); 1338 if (chip->card_exist & SD_CARD) { 1339 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 1340 chip->card_fail |= SD_CARD; 1341 } else if (chip->card_exist & MS_CARD) { 1342 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 1343 chip->card_fail |= MS_CARD; 1344 } else if (chip->card_exist & XD_CARD) { 1345 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); 1346 chip->card_fail |= XD_CARD; 1347 } 1348 card_power_off(chip, SD_CARD); 1349 } 1350 } 1351#endif 1352 1353Delink_Stage: 1354 if (chip->auto_delink_en && chip->auto_delink_allowed && 1355 !chip->card_ready && !chip->card_ejected && !chip->sd_io) { 1356 int enter_L1 = chip->auto_delink_in_L1 && (chip->aspm_l0s_l1_en || chip->ss_en); 1357 int delink_stage1_cnt = chip->delink_stage1_step; 1358 int delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step; 1359 int delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step; 1360 1361 if (chip->auto_delink_cnt <= delink_stage3_cnt) { 1362 if (chip->auto_delink_cnt == delink_stage1_cnt) { 1363 rtsx_set_stat(chip, RTSX_STAT_DELINK); 1364 1365 if (chip->asic_code && CHECK_PID(chip, 0x5208)) { 1366 rtsx_set_phy_reg_bit(chip, 0x1C, 2); 1367 } 1368 if (chip->card_exist) { 1369 RTSX_DEBUGP("False card inserted, do force delink\n"); 1370 1371 if (enter_L1) { 1372 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1); 1373 } 1374 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A); 1375 1376 if (enter_L1) { 1377 rtsx_enter_L1(chip); 1378 } 1379 1380 chip->auto_delink_cnt = delink_stage3_cnt + 1; 1381 } else { 1382 RTSX_DEBUGP("No card inserted, do delink\n"); 1383 1384 if (enter_L1) { 1385 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1); 1386 } 1387#ifdef HW_INT_WRITE_CLR 1388 if (CHECK_PID(chip, 0x5209)) { 1389 rtsx_writel(chip, RTSX_BIPR, 0xFFFFFFFF); 1390 RTSX_DEBUGP("RTSX_BIPR: 0x%x\n", rtsx_readl(chip, RTSX_BIPR)); 1391 } 1392#endif 1393 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0x02); 1394 1395 if (enter_L1) { 1396 rtsx_enter_L1(chip); 1397 } 1398 } 1399 } 1400 1401 if (chip->auto_delink_cnt == delink_stage2_cnt) { 1402 RTSX_DEBUGP("Try to do force delink\n"); 1403 1404 if (enter_L1) { 1405 rtsx_exit_L1(chip); 1406 } 1407 1408 if (chip->asic_code && CHECK_PID(chip, 0x5208)) { 1409 rtsx_set_phy_reg_bit(chip, 0x1C, 2); 1410 } 1411 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A); 1412 } 1413 1414 chip->auto_delink_cnt++; 1415 } 1416 } else { 1417 chip->auto_delink_cnt = 0; 1418 } 1419} 1420 1421void rtsx_undo_delink(struct rtsx_chip *chip) 1422{ 1423 chip->auto_delink_allowed = 0; 1424 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00); 1425} 1426 1427/** 1428 * rtsx_stop_cmd - stop command transfer and DMA transfer 1429 * @chip: Realtek's card reader chip 1430 * @card: flash card type 1431 * 1432 * Stop command transfer and DMA transfer. 1433 * This function is called in error handler. 1434 */ 1435void rtsx_stop_cmd(struct rtsx_chip *chip, int card) 1436{ 1437 int i; 1438 1439 for (i = 0; i <= 8; i++) { 1440 int addr = RTSX_HCBAR + i * 4; 1441 u32 reg; 1442 reg = rtsx_readl(chip, addr); 1443 RTSX_DEBUGP("BAR (0x%02x): 0x%08x\n", addr, reg); 1444 } 1445 rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD); 1446 rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA); 1447 1448 for (i = 0; i < 16; i++) { 1449 u16 addr = 0xFE20 + (u16)i; 1450 u8 val; 1451 rtsx_read_register(chip, addr, &val); 1452 RTSX_DEBUGP("0x%04X: 0x%02x\n", addr, val); 1453 } 1454 1455 rtsx_write_register(chip, DMACTL, 0x80, 0x80); 1456 rtsx_write_register(chip, RBCTL, 0x80, 0x80); 1457} 1458 1459#define MAX_RW_REG_CNT 1024 1460 1461int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data) 1462{ 1463 int i; 1464 u32 val = 3 << 30; 1465 1466 val |= (u32)(addr & 0x3FFF) << 16; 1467 val |= (u32)mask << 8; 1468 val |= (u32)data; 1469 1470 rtsx_writel(chip, RTSX_HAIMR, val); 1471 1472 for (i = 0; i < MAX_RW_REG_CNT; i++) { 1473 val = rtsx_readl(chip, RTSX_HAIMR); 1474 if ((val & (1 << 31)) == 0) { 1475 if (data != (u8)val) { 1476 TRACE_RET(chip, STATUS_FAIL); 1477 } 1478 return STATUS_SUCCESS; 1479 } 1480 } 1481 1482 TRACE_RET(chip, STATUS_TIMEDOUT); 1483} 1484 1485int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data) 1486{ 1487 u32 val = 2 << 30; 1488 int i; 1489 1490 if (data) { 1491 *data = 0; 1492 } 1493 1494 val |= (u32)(addr & 0x3FFF) << 16; 1495 1496 rtsx_writel(chip, RTSX_HAIMR, val); 1497 1498 for (i = 0; i < MAX_RW_REG_CNT; i++) { 1499 val = rtsx_readl(chip, RTSX_HAIMR); 1500 if ((val & (1 << 31)) == 0) { 1501 break; 1502 } 1503 } 1504 1505 if (i >= MAX_RW_REG_CNT) { 1506 TRACE_RET(chip, STATUS_TIMEDOUT); 1507 } 1508 1509 if (data) { 1510 *data = (u8)(val & 0xFF); 1511 } 1512 1513 return STATUS_SUCCESS; 1514} 1515 1516int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val) 1517{ 1518 u8 mode = 0, tmp; 1519 int i; 1520 1521 for (i = 0; i < 4; i++) { 1522 if (mask & 0xFF) { 1523 RTSX_WRITE_REG(chip, CFGDATA0 + i, 1524 0xFF, (u8)(val & mask & 0xFF)); 1525 mode |= (1 << i); 1526 } 1527 mask >>= 8; 1528 val >>= 8; 1529 } 1530 1531 if (mode) { 1532 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr); 1533 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); 1534 1535 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 1536 0x80 | mode | ((func_no & 0x03) << 4)); 1537 1538 for (i = 0; i < MAX_RW_REG_CNT; i++) { 1539 RTSX_READ_REG(chip, CFGRWCTL, &tmp); 1540 if ((tmp & 0x80) == 0) { 1541 break; 1542 } 1543 } 1544 } 1545 1546 return STATUS_SUCCESS; 1547} 1548 1549int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val) 1550{ 1551 int i; 1552 u8 tmp; 1553 u32 data = 0; 1554 1555 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr); 1556 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); 1557 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4)); 1558 1559 for (i = 0; i < MAX_RW_REG_CNT; i++) { 1560 RTSX_READ_REG(chip, CFGRWCTL, &tmp); 1561 if ((tmp & 0x80) == 0) { 1562 break; 1563 } 1564 } 1565 1566 for (i = 0; i < 4; i++) { 1567 RTSX_READ_REG(chip, CFGDATA0 + i, &tmp); 1568 data |= (u32)tmp << (i * 8); 1569 } 1570 1571 if (val) { 1572 *val = data; 1573 } 1574 1575 return STATUS_SUCCESS; 1576} 1577 1578int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len) 1579{ 1580 u32 *data, *mask; 1581 u16 offset = addr % 4; 1582 u16 aligned_addr = addr - offset; 1583 int dw_len, i, j; 1584 int retval; 1585 1586 RTSX_DEBUGP("%s\n", __func__); 1587 1588 if (!buf) { 1589 TRACE_RET(chip, STATUS_NOMEM); 1590 } 1591 1592 if ((len + offset) % 4) { 1593 dw_len = (len + offset) / 4 + 1; 1594 } else { 1595 dw_len = (len + offset) / 4; 1596 } 1597 RTSX_DEBUGP("dw_len = %d\n", dw_len); 1598 1599 data = (u32 *)vmalloc(dw_len * 4); 1600 if (!data) { 1601 TRACE_RET(chip, STATUS_NOMEM); 1602 } 1603 memset(data, 0, dw_len * 4); 1604 1605 mask = (u32 *)vmalloc(dw_len * 4); 1606 if (!mask) { 1607 vfree(data); 1608 TRACE_RET(chip, STATUS_NOMEM); 1609 } 1610 memset(mask, 0, dw_len * 4); 1611 1612 j = 0; 1613 for (i = 0; i < len; i++) { 1614 mask[j] |= 0xFF << (offset * 8); 1615 data[j] |= buf[i] << (offset * 8); 1616 if (++offset == 4) { 1617 j++; 1618 offset = 0; 1619 } 1620 } 1621 1622 RTSX_DUMP(mask, dw_len * 4); 1623 RTSX_DUMP(data, dw_len * 4); 1624 1625 for (i = 0; i < dw_len; i++) { 1626 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4, mask[i], data[i]); 1627 if (retval != STATUS_SUCCESS) { 1628 vfree(data); 1629 vfree(mask); 1630 TRACE_RET(chip, STATUS_FAIL); 1631 } 1632 } 1633 1634 vfree(data); 1635 vfree(mask); 1636 1637 return STATUS_SUCCESS; 1638} 1639 1640int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len) 1641{ 1642 u32 *data; 1643 u16 offset = addr % 4; 1644 u16 aligned_addr = addr - offset; 1645 int dw_len, i, j; 1646 int retval; 1647 1648 RTSX_DEBUGP("%s\n", __func__); 1649 1650 if ((len + offset) % 4) { 1651 dw_len = (len + offset) / 4 + 1; 1652 } else { 1653 dw_len = (len + offset) / 4; 1654 } 1655 RTSX_DEBUGP("dw_len = %d\n", dw_len); 1656 1657 data = (u32 *)vmalloc(dw_len * 4); 1658 if (!data) { 1659 TRACE_RET(chip, STATUS_NOMEM); 1660 } 1661 1662 for (i = 0; i < dw_len; i++) { 1663 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4, data + i); 1664 if (retval != STATUS_SUCCESS) { 1665 vfree(data); 1666 TRACE_RET(chip, STATUS_FAIL); 1667 } 1668 } 1669 1670 if (buf) { 1671 j = 0; 1672 1673 for (i = 0; i < len; i++) { 1674 buf[i] = (u8)(data[j] >> (offset * 8)); 1675 if (++offset == 4) { 1676 j++; 1677 offset = 0; 1678 } 1679 } 1680 } 1681 1682 vfree(data); 1683 1684 return STATUS_SUCCESS; 1685} 1686 1687int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) 1688{ 1689 int i, finished = 0; 1690 u8 tmp; 1691 1692 RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val); 1693 RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); 1694 RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr); 1695 RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81); 1696 1697 for (i = 0; i < 100000; i++) { 1698 RTSX_READ_REG(chip, PHYRWCTL, &tmp); 1699 if (!(tmp & 0x80)) { 1700 finished = 1; 1701 break; 1702 } 1703 } 1704 1705 if (!finished) { 1706 TRACE_RET(chip, STATUS_FAIL); 1707 } 1708 1709 return STATUS_SUCCESS; 1710} 1711 1712int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) 1713{ 1714 int i, finished = 0; 1715 u16 data = 0; 1716 u8 tmp; 1717 1718 RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr); 1719 RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80); 1720 1721 for (i = 0; i < 100000; i++) { 1722 RTSX_READ_REG(chip, PHYRWCTL, &tmp); 1723 if (!(tmp & 0x80)) { 1724 finished = 1; 1725 break; 1726 } 1727 } 1728 1729 if (!finished) { 1730 TRACE_RET(chip, STATUS_FAIL); 1731 } 1732 1733 RTSX_READ_REG(chip, PHYDATA0, &tmp); 1734 data = tmp; 1735 RTSX_READ_REG(chip, PHYDATA1, &tmp); 1736 data |= (u16)tmp << 8; 1737 1738 if (val) 1739 *val = data; 1740 1741 return STATUS_SUCCESS; 1742} 1743 1744int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) 1745{ 1746 int i; 1747 u8 data = 0; 1748 1749 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr); 1750 1751 for (i = 0; i < 100; i++) { 1752 RTSX_READ_REG(chip, EFUSE_CTRL, &data); 1753 if (!(data & 0x80)) 1754 break; 1755 udelay(1); 1756 } 1757 1758 if (data & 0x80) { 1759 TRACE_RET(chip, STATUS_TIMEDOUT); 1760 } 1761 1762 RTSX_READ_REG(chip, EFUSE_DATA, &data); 1763 if (val) 1764 *val = data; 1765 1766 return STATUS_SUCCESS; 1767} 1768 1769int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) 1770{ 1771 int i, j; 1772 u8 data = 0, tmp = 0xFF; 1773 1774 for (i = 0; i < 8; i++) { 1775 if (val & (u8)(1 << i)) 1776 continue; 1777 1778 tmp &= (~(u8)(1 << i)); 1779 RTSX_DEBUGP("Write 0x%x to 0x%x\n", tmp, addr); 1780 1781 RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp); 1782 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr); 1783 1784 for (j = 0; j < 100; j++) { 1785 RTSX_READ_REG(chip, EFUSE_CTRL, &data); 1786 if (!(data & 0x80)) 1787 break; 1788 wait_timeout(3); 1789 } 1790 1791 if (data & 0x80) { 1792 TRACE_RET(chip, STATUS_TIMEDOUT); 1793 } 1794 1795 wait_timeout(5); 1796 } 1797 1798 return STATUS_SUCCESS; 1799} 1800 1801int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) 1802{ 1803 int retval; 1804 u16 value; 1805 1806 retval = rtsx_read_phy_register(chip, reg, &value); 1807 if (retval != STATUS_SUCCESS) { 1808 TRACE_RET(chip, STATUS_FAIL); 1809 } 1810 if (value & (1 << bit)) { 1811 value &= ~(1 << bit); 1812 retval = rtsx_write_phy_register(chip, reg, value); 1813 if (retval != STATUS_SUCCESS) { 1814 TRACE_RET(chip, STATUS_FAIL); 1815 } 1816 } 1817 1818 return STATUS_SUCCESS; 1819} 1820 1821int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) 1822{ 1823 int retval; 1824 u16 value; 1825 1826 retval = rtsx_read_phy_register(chip, reg, &value); 1827 if (retval != STATUS_SUCCESS) { 1828 TRACE_RET(chip, STATUS_FAIL); 1829 } 1830 if (0 == (value & (1 << bit))) { 1831 value |= (1 << bit); 1832 retval = rtsx_write_phy_register(chip, reg, value); 1833 if (retval != STATUS_SUCCESS) { 1834 TRACE_RET(chip, STATUS_FAIL); 1835 } 1836 } 1837 1838 return STATUS_SUCCESS; 1839} 1840 1841int rtsx_check_link_ready(struct rtsx_chip *chip) 1842{ 1843 u8 val; 1844 1845 RTSX_READ_REG(chip, IRQSTAT0, &val); 1846 1847 RTSX_DEBUGP("IRQSTAT0: 0x%x\n", val); 1848 if (val & LINK_RDY_INT) { 1849 RTSX_DEBUGP("Delinked!\n"); 1850 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); 1851 return STATUS_FAIL; 1852 } 1853 1854 return STATUS_SUCCESS; 1855} 1856 1857static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate) 1858{ 1859 u32 ultmp; 1860 1861 RTSX_DEBUGP("%04x set pm_dstate to %d\n", chip->product_id, dstate); 1862 1863 if (CHK_SDIO_EXIST(chip)) { 1864 u8 func_no; 1865 1866 if (CHECK_PID(chip, 0x5288)) { 1867 func_no = 2; 1868 } else { 1869 func_no = 1; 1870 } 1871 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp); 1872 RTSX_DEBUGP("pm_dstate of function %d: 0x%x\n", (int)func_no, ultmp); 1873 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate); 1874 } 1875 1876 rtsx_write_config_byte(chip, 0x44, dstate); 1877 rtsx_write_config_byte(chip, 0x45, 0); 1878} 1879 1880void rtsx_enter_L1(struct rtsx_chip *chip) 1881{ 1882 rtsx_handle_pm_dstate(chip, 2); 1883} 1884 1885void rtsx_exit_L1(struct rtsx_chip *chip) 1886{ 1887 rtsx_write_config_byte(chip, 0x44, 0); 1888 rtsx_write_config_byte(chip, 0x45, 0); 1889} 1890 1891void rtsx_enter_ss(struct rtsx_chip *chip) 1892{ 1893 RTSX_DEBUGP("Enter Selective Suspend State!\n"); 1894 1895 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); 1896 1897 if (chip->power_down_in_ss) { 1898 rtsx_power_off_card(chip); 1899 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 1900 } 1901 1902 if (CHK_SDIO_EXIST(chip)) { 1903 if (CHECK_PID(chip, 0x5288)) { 1904 rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100); 1905 } else { 1906 rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100); 1907 } 1908 } 1909 1910 if (chip->auto_delink_en) { 1911 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01); 1912 } else { 1913 if (!chip->phy_debug_mode) { 1914 u32 tmp; 1915 tmp = rtsx_readl(chip, RTSX_BIER); 1916 tmp |= CARD_INT; 1917 rtsx_writel(chip, RTSX_BIER, tmp); 1918 } 1919 1920 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0); 1921 } 1922 1923 rtsx_enter_L1(chip); 1924 1925 RTSX_CLR_DELINK(chip); 1926 rtsx_set_stat(chip, RTSX_STAT_SS); 1927} 1928 1929void rtsx_exit_ss(struct rtsx_chip *chip) 1930{ 1931 RTSX_DEBUGP("Exit Selective Suspend State!\n"); 1932 1933 rtsx_exit_L1(chip); 1934 1935 if (chip->power_down_in_ss) { 1936 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 1937 udelay(1000); 1938 } 1939 1940 if (RTSX_TST_DELINK(chip)) { 1941 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; 1942 rtsx_reinit_cards(chip, 1); 1943 RTSX_CLR_DELINK(chip); 1944 } else if (chip->power_down_in_ss) { 1945 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; 1946 rtsx_reinit_cards(chip, 0); 1947 } 1948} 1949 1950int rtsx_pre_handle_interrupt(struct rtsx_chip *chip) 1951{ 1952 u32 status, int_enable; 1953 int exit_ss = 0; 1954#ifdef SUPPORT_OCP 1955 u32 ocp_int = 0; 1956 1957 if (CHECK_PID(chip, 0x5209)) { 1958 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 1959 ocp_int = MS_OC_INT | SD_OC_INT; 1960 } else { 1961 ocp_int = SD_OC_INT; 1962 } 1963 } else { 1964 ocp_int = OC_INT; 1965 } 1966#endif 1967 1968 if (chip->ss_en) { 1969 chip->ss_counter = 0; 1970 if (rtsx_get_stat(chip) == RTSX_STAT_SS) { 1971 exit_ss = 1; 1972 rtsx_exit_L1(chip); 1973 rtsx_set_stat(chip, RTSX_STAT_RUN); 1974 } 1975 } 1976 1977 int_enable = rtsx_readl(chip, RTSX_BIER); 1978 chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 1979 1980#ifdef HW_INT_WRITE_CLR 1981 if (CHECK_PID(chip, 0x5209)) { 1982 rtsx_writel(chip, RTSX_BIPR, chip->int_reg); 1983 } 1984#endif 1985 1986 if (((chip->int_reg & int_enable) == 0) || (chip->int_reg == 0xFFFFFFFF)) 1987 return STATUS_FAIL; 1988 1989 if (!chip->msi_en) { 1990 if (CHECK_PID(chip, 0x5209)) { 1991 u8 val; 1992 rtsx_read_config_byte(chip, 0x05, &val); 1993 if (val & 0x04) { 1994 return STATUS_FAIL; 1995 } 1996 } 1997 } 1998 1999 status = chip->int_reg &= (int_enable | 0x7FFFFF); 2000 2001 if (status & CARD_INT) { 2002 chip->auto_delink_cnt = 0; 2003 2004 if (status & SD_INT) { 2005 if (status & SD_EXIST) { 2006 set_bit(SD_NR, &(chip->need_reset)); 2007 } else { 2008 set_bit(SD_NR, &(chip->need_release)); 2009 chip->sd_reset_counter = 0; 2010 chip->sd_show_cnt = 0; 2011 clear_bit(SD_NR, &(chip->need_reset)); 2012 } 2013 } else { 2014 /* If multi-luns, it's possible that 2015 when plugging/unplugging one card 2016 there is another card which still 2017 exists in the slot. In this case, 2018 all existed cards should be reset. 2019 */ 2020 if (exit_ss && (status & SD_EXIST)) 2021 set_bit(SD_NR, &(chip->need_reinit)); 2022 } 2023 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) { 2024 if (status & XD_INT) { 2025 if (status & XD_EXIST) { 2026 set_bit(XD_NR, &(chip->need_reset)); 2027 } else { 2028 set_bit(XD_NR, &(chip->need_release)); 2029 chip->xd_reset_counter = 0; 2030 chip->xd_show_cnt = 0; 2031 clear_bit(XD_NR, &(chip->need_reset)); 2032 } 2033 } else { 2034 if (exit_ss && (status & XD_EXIST)) 2035 set_bit(XD_NR, &(chip->need_reinit)); 2036 } 2037 } 2038 if (status & MS_INT) { 2039 if (status & MS_EXIST) { 2040 set_bit(MS_NR, &(chip->need_reset)); 2041 } else { 2042 set_bit(MS_NR, &(chip->need_release)); 2043 chip->ms_reset_counter = 0; 2044 chip->ms_show_cnt = 0; 2045 clear_bit(MS_NR, &(chip->need_reset)); 2046 } 2047 } else { 2048 if (exit_ss && (status & MS_EXIST)) 2049 set_bit(MS_NR, &(chip->need_reinit)); 2050 } 2051 } 2052 2053#ifdef SUPPORT_OCP 2054 chip->ocp_int = ocp_int & status; 2055#endif 2056 2057 if (chip->sd_io) { 2058 if (chip->int_reg & DATA_DONE_INT) 2059 chip->int_reg &= ~(u32)DATA_DONE_INT; 2060 } 2061 2062 return STATUS_SUCCESS; 2063} 2064 2065void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat) 2066{ 2067 int retval; 2068 2069 RTSX_DEBUGP("rtsx_do_before_power_down, pm_stat = %d\n", pm_stat); 2070 2071 rtsx_set_stat(chip, RTSX_STAT_SUSPEND); 2072 2073 retval = rtsx_force_power_on(chip, SSC_PDCTL); 2074 if (retval != STATUS_SUCCESS) 2075 return; 2076 2077 rtsx_release_cards(chip); 2078 rtsx_disable_bus_int(chip); 2079 turn_off_led(chip, LED_GPIO); 2080 2081#ifdef HW_AUTO_SWITCH_SD_BUS 2082 if (chip->sd_io) { 2083 chip->sdio_in_charge = 1; 2084 if (CHECK_PID(chip, 0x5208)) { 2085 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); 2086 /* Enable sdio_bus_auto_switch */ 2087 rtsx_write_register(chip, 0xFE70, 0x80, 0x80); 2088 } else if (CHECK_PID(chip, 0x5288)) { 2089 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); 2090 /* Enable sdio_bus_auto_switch */ 2091 rtsx_write_register(chip, 0xFE5A, 0x08, 0x08); 2092 } else if (CHECK_PID(chip, 0x5209)) { 2093 rtsx_write_register(chip, TLPTISTAT, 0x10, 0x10); 2094 /* Enable sdio_bus_auto_switch */ 2095 rtsx_write_register(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, SDIO_BUS_AUTO_SWITCH); 2096 } 2097 } 2098#endif 2099 2100 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) { 2101 /* u_force_clkreq_0 */ 2102 rtsx_write_register(chip, PETXCFG, 0x08, 0x08); 2103 } else if (CHECK_PID(chip, 0x5209)) { 2104 /* u_force_clkreq_0 */ 2105 rtsx_write_register(chip, PETXCFG, 0x08, 0x08); 2106 } 2107 2108 if (pm_stat == PM_S1) { 2109 RTSX_DEBUGP("Host enter S1\n"); 2110 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, HOST_ENTER_S1); 2111 } else if (pm_stat == PM_S3) { 2112 if (chip->s3_pwr_off_delay > 0) { 2113 wait_timeout(chip->s3_pwr_off_delay); 2114 } 2115 RTSX_DEBUGP("Host enter S3\n"); 2116 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, HOST_ENTER_S3); 2117 } 2118 2119 if (chip->do_delink_before_power_down && chip->auto_delink_en) { 2120 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2); 2121 } 2122 2123 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 2124 2125 chip->cur_clk = 0; 2126 chip->cur_card = 0; 2127 chip->card_exist = 0; 2128} 2129 2130void rtsx_enable_aspm(struct rtsx_chip *chip) 2131{ 2132 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) { 2133 if (!chip->aspm_enabled) { 2134 RTSX_DEBUGP("Try to enable ASPM\n"); 2135 chip->aspm_enabled = 1; 2136 2137 if (chip->asic_code && CHECK_PID(chip, 0x5208)) 2138 rtsx_write_phy_register(chip, 0x07, 0); 2139 if (CHECK_PID(chip, 0x5208)) { 2140 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, 2141 0x30 | chip->aspm_level[0]); 2142 } else { 2143 rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en); 2144 } 2145 2146 if (CHK_SDIO_EXIST(chip)) { 2147 u16 val = chip->aspm_l0s_l1_en | 0x0100; 2148 if (CHECK_PID(chip, 0x5288)) { 2149 rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, val); 2150 } else { 2151 rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFFFF, val); 2152 } 2153 } 2154 } 2155 } 2156 2157 return; 2158} 2159 2160void rtsx_disable_aspm(struct rtsx_chip *chip) 2161{ 2162 if (CHECK_PID(chip, 0x5208)) 2163 rtsx_monitor_aspm_config(chip); 2164 2165 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) { 2166 if (chip->aspm_enabled) { 2167 RTSX_DEBUGP("Try to disable ASPM\n"); 2168 chip->aspm_enabled = 0; 2169 2170 if (chip->asic_code && CHECK_PID(chip, 0x5208)) 2171 rtsx_write_phy_register(chip, 0x07, 0x0129); 2172 if (CHECK_PID(chip, 0x5208)) { 2173 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, 0x30); 2174 } else { 2175 rtsx_write_config_byte(chip, LCTLR, 0x00); 2176 } 2177 wait_timeout(1); 2178 } 2179 } 2180 2181 return; 2182} 2183 2184int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len) 2185{ 2186 int retval; 2187 int i, j; 2188 u16 reg_addr; 2189 u8 *ptr; 2190 2191 if (!buf) { 2192 TRACE_RET(chip, STATUS_ERROR); 2193 } 2194 2195 ptr = buf; 2196 reg_addr = PPBUF_BASE2; 2197 for (i = 0; i < buf_len/256; i++) { 2198 rtsx_init_cmd(chip); 2199 2200 for (j = 0; j < 256; j++) 2201 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); 2202 2203 retval = rtsx_send_cmd(chip, 0, 250); 2204 if (retval < 0) { 2205 TRACE_RET(chip, STATUS_FAIL); 2206 } 2207 2208 memcpy(ptr, rtsx_get_cmd_data(chip), 256); 2209 ptr += 256; 2210 } 2211 2212 if (buf_len%256) { 2213 rtsx_init_cmd(chip); 2214 2215 for (j = 0; j < buf_len%256; j++) 2216 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); 2217 2218 retval = rtsx_send_cmd(chip, 0, 250); 2219 if (retval < 0) { 2220 TRACE_RET(chip, STATUS_FAIL); 2221 } 2222 } 2223 2224 memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256); 2225 2226 return STATUS_SUCCESS; 2227} 2228 2229int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len) 2230{ 2231 int retval; 2232 int i, j; 2233 u16 reg_addr; 2234 u8 *ptr; 2235 2236 if (!buf) { 2237 TRACE_RET(chip, STATUS_ERROR); 2238 } 2239 2240 ptr = buf; 2241 reg_addr = PPBUF_BASE2; 2242 for (i = 0; i < buf_len/256; i++) { 2243 rtsx_init_cmd(chip); 2244 2245 for (j = 0; j < 256; j++) { 2246 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr); 2247 ptr++; 2248 } 2249 2250 retval = rtsx_send_cmd(chip, 0, 250); 2251 if (retval < 0) { 2252 TRACE_RET(chip, STATUS_FAIL); 2253 } 2254 } 2255 2256 if (buf_len%256) { 2257 rtsx_init_cmd(chip); 2258 2259 for (j = 0; j < buf_len%256; j++) { 2260 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr); 2261 ptr++; 2262 } 2263 2264 retval = rtsx_send_cmd(chip, 0, 250); 2265 if (retval < 0) { 2266 TRACE_RET(chip, STATUS_FAIL); 2267 } 2268 } 2269 2270 return STATUS_SUCCESS; 2271} 2272 2273int rtsx_check_chip_exist(struct rtsx_chip *chip) 2274{ 2275 if (rtsx_readl(chip, 0) == 0xFFFFFFFF) { 2276 TRACE_RET(chip, STATUS_FAIL); 2277 } 2278 2279 return STATUS_SUCCESS; 2280} 2281 2282int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl) 2283{ 2284 int retval; 2285 u8 mask = 0; 2286 2287 if (ctl & SSC_PDCTL) 2288 mask |= SSC_POWER_DOWN; 2289 2290#ifdef SUPPORT_OCP 2291 if (ctl & OC_PDCTL) { 2292 mask |= SD_OC_POWER_DOWN; 2293 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 2294 mask |= MS_OC_POWER_DOWN; 2295 } 2296 } 2297#endif 2298 2299 if (mask) { 2300 retval = rtsx_write_register(chip, FPDCTL, mask, 0); 2301 if (retval != STATUS_SUCCESS) { 2302 TRACE_RET(chip, STATUS_FAIL); 2303 } 2304 2305 if (CHECK_PID(chip, 0x5288)) 2306 wait_timeout(200); 2307 } 2308 2309 return STATUS_SUCCESS; 2310} 2311 2312int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl) 2313{ 2314 int retval; 2315 u8 mask = 0, val = 0; 2316 2317 if (ctl & SSC_PDCTL) 2318 mask |= SSC_POWER_DOWN; 2319 2320#ifdef SUPPORT_OCP 2321 if (ctl & OC_PDCTL) { 2322 mask |= SD_OC_POWER_DOWN; 2323 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 2324 mask |= MS_OC_POWER_DOWN; 2325 } 2326#endif 2327 2328 if (mask) { 2329 val = mask; 2330 retval = rtsx_write_register(chip, FPDCTL, mask, val); 2331 if (retval != STATUS_SUCCESS) { 2332 TRACE_RET(chip, STATUS_FAIL); 2333 } 2334 } 2335 2336 return STATUS_SUCCESS; 2337} 2338