wbhal.h revision bd37b7fddf51431faf9c32cd22356421913cfce8
180aba53616a5f2f97adf386a2a3ccd5fb0dbfdd6Pekka Enberg#ifndef __WINBOND_WBHAL_S_H 280aba53616a5f2f97adf386a2a3ccd5fb0dbfdd6Pekka Enberg#define __WINBOND_WBHAL_S_H 380aba53616a5f2f97adf386a2a3ccd5fb0dbfdd6Pekka Enberg 480aba53616a5f2f97adf386a2a3ccd5fb0dbfdd6Pekka Enberg#include <linux/types.h> 5bd37b7fddf51431faf9c32cd22356421913cfce8Pekka Enberg#include <linux/if_ether.h> /* for ETH_ALEN */ 680aba53616a5f2f97adf386a2a3ccd5fb0dbfdd6Pekka Enberg 79ce922fde7fb44a8690aa37d3c7f4f0cf5d921caPekka Enberg#include "common.h" 880aba53616a5f2f97adf386a2a3ccd5fb0dbfdd6Pekka Enberg 966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//[20040722 WK] 1066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_LED_SET_MASK 0x001c //20060901 Extend 1166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_LED_SET_SHIFT 2 1266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 1366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//supported RF type 1466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_MAXIM_2825 0 1566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_MAXIM_2827 1 1666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_MAXIM_2828 2 1766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_MAXIM_2829 3 1866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_MAXIM_V1 15 1966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_AIROHA_2230 16 2066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_AIROHA_7230 17 2166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_AIROHA_2230S 18 // 20060420 Add this 2266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// #define RF_RFMD_2959 32 // 20060626 Remove all about RFMD 2366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_WB_242 33 2466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_WB_242_1 34 // 20060619.5 Add 2566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define RF_DECIDE_BY_INF 255 2666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 2766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//---------------------------------------------------------------- 2866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// The follow define connect to upper layer 2966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// User must modify for connection between HAL and upper layer 3066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//---------------------------------------------------------------- 3166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 3266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 3366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 3466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 3566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek///////////////////////////////////////////////////////////////////////////////////////////////////// 3666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//================================================================================================ 3766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// Common define 3866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//================================================================================================ 3966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_USB_MODE_BURST( _H ) (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify 4066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 4166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// Scan interval 4266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define SCAN_MAX_CHNL_TIME (50) 4366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 4466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// For TxL2 Frame typr recognise 4566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FRAME_TYPE_802_3_DATA 0 4666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FRAME_TYPE_802_11_MANAGEMENT 1 4766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE 2 4866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FRAME_TYPE_802_11_CONTROL 3 4966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FRAME_TYPE_802_11_DATA 4 5066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FRAME_TYPE_PROMISCUOUS 5 5166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 5266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// The follow definition is used for convert the frame-------------------- 5366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DOT_11_SEQUENCE_OFFSET 22 //Sequence control offset 5466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DOT_3_TYPE_OFFSET 12 5566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DOT_11_MAC_HEADER_SIZE 24 5666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DOT_11_SNAP_SIZE 6 5766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DOT_11_TYPE_OFFSET 30 //The start offset of 802.11 Frame. Type encapsulatuin. 5866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DEFAULT_SIFSTIME 10 5966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DEFAULT_FRAGMENT_THRESHOLD 2346 // No fragment 6066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DEFAULT_MSDU_LIFE_TIME 0xffff 6166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 6266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME (144+48) 6366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME (72+24) 6466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION (16+4+6) 6566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define Tsym 4 6666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 6766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// Frame Type of Bits (2, 3)--------------------------------------------- 6866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MAC_TYPE_MANAGEMENT 0x00 6966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MAC_TYPE_CONTROL 0x04 7066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MAC_TYPE_DATA 0x08 7166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MASK_FRAGMENT_NUMBER 0x000F 7266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define SEQUENCE_NUMBER_SHIFT 4 7366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 7466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_WOL_TYPE_WAKEUP_FRAME 0x01 7566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_WOL_TYPE_MAGIC_PACKET 0x02 7666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 7766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// 20040106 ADDED 7866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_KEYTYPE_WEP40 0 7966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_KEYTYPE_WEP104 1 8066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_KEYTYPE_TKIP 2 // 128 bit key 8166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define HAL_KEYTYPE_AES_CCMP 3 // 128 bit key 8266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 8366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// For VM state 8466101de10957e07a6fd0365d5af9adf650246d14Pavel Machekenum { 8566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek VM_STOP = 0, 8666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek VM_RUNNING, 8766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek VM_COMPLETED 8866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek}; 8966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 9066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// Be used for 802.11 mac header 9166101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _MAC_FRAME_CONTROL { 9266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 mac_frame_info; // this is a combination of the protovl version, type and subtype 9366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 to_ds:1; 9466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 from_ds:1; 9566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 more_frag:1; 9666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 retry:1; 9766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 pwr_mgt:1; 9866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 more_data:1; 9966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 WEP:1; 10066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 order:1; 10166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL; 10266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 10366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//----------------------------------------------------- 10466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// Normal Key table format 10566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//----------------------------------------------------- 10666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX 10766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MAX_KEY_TABLE 24 // 24 entry for storing key data 10866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define GROUP_KEY_START_INDEX 4 10966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MAPPING_KEY_START_INDEX 8 11066101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _KEY_TABLE 11166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek{ 11266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW0_Valid:1; 11366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW0_NullKey:1; 11466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit 11566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW0_WEPON:1; 11666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW0_RESERVED:11; 11766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW0_Address1:16; 11866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 11966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW1_Address2; 12066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 12166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW2_RxSequenceCount1; 12266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 12366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW3_RxSequenceCount2:16; 12466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW3_RESERVED:16; 12566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 12666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW4_TxSequenceCount1; 12766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 12866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW5_TxSequenceCount2:16; 12966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DW5_RESERVED:16; 13066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 13166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} KEY_TABLE, *PKEY_TABLE; 13266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 13366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//-------------------------------------------------------- 13466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// Descriptor 13566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//-------------------------------------------------------- 13666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MAX_DESCRIPTOR_BUFFER_INDEX 8 // Have to multiple of 2 13766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//#define FLAG_ERROR_TX_MASK cpu_to_le32(0x000000bf) //20061009 marked by anson's endian 13866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FLAG_ERROR_TX_MASK 0x000000bf //20061009 anson's endian 13966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//#define FLAG_ERROR_RX_MASK 0x00000c3f 14066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//#define FLAG_ERROR_RX_MASK cpu_to_le32(0x0000083f) //20061009 marked by anson's endian 14166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //Don't care replay error, 14266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //it is handled by S/W 14366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FLAG_ERROR_RX_MASK 0x0000083f //20060926 anson's endian 14466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 14566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define FLAG_BAND_RX_MASK 0x10000000 //Bit 28 14666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 14766101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _R00_DESCRIPTOR 14866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek{ 14966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 15066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 15166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 value; 15266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #ifdef _BIG_ENDIAN_ //20060926 anson's endian 15366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 15466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 15566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_packet_or_buffer_status:1; 15666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_packet_in_fifo:1; 15766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_RESERVED:2; 15866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_receive_byte_count:12; 15966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_receive_time_index:16; 16066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 16166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #else 16266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 16366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 16466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_receive_time_index:16; 16566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_receive_byte_count:12; 16666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_RESERVED:2; 16766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_packet_in_fifo:1; 16866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R00_packet_or_buffer_status:1; 16966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 17066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #endif 17166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 17266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} R00_DESCRIPTOR, *PR00_DESCRIPTOR; 17366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 17466101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _T00_DESCRIPTOR 17566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek{ 17666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 17766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 17866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 value; 17966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #ifdef _BIG_ENDIAN_ //20061009 anson's endian 18066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 18166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 18266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_first_mpdu:1; // for hardware use 18366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_last_mpdu:1; // for hardware use 18466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used 18566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS 18666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_RESERVED_ID:2;//3 bit ID reserved 18766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c 18866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_RESERVED:4; 18966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_header_length:6; 19066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_frame_length:12; 19166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 19266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #else 19366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 19466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 19566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_frame_length:12; 19666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_header_length:6; 19766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_RESERVED:4; 19866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_tx_packet_id:4;//930519.4.e 930810.3.c 19966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_RESERVED_ID:2;//3 bit ID reserved 20066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS 20166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_IsLastMpdu:1;// 0: not 1:Yes for software used 20266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_last_mpdu:1; // for hardware use 20366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T00_first_mpdu:1; // for hardware use 20466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 20566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #endif 20666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 20766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} T00_DESCRIPTOR, *PT00_DESCRIPTOR; 20866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 20966101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _R01_DESCRIPTOR 21066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek{ 21166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 21266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 21366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 value; 21466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian 21566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 21666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 21766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_RESERVED:3; 21866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_mod_type:1; 21966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_pre_type:1; 22066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_data_rate:3; 22166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_AGC_state:8; 22266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_LNA_state:2; 22366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_decryption_method:2; 22466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_mic_error:1; 22566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_replay:1; 22666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_broadcast_frame:1; 22766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_multicast_frame:1; 22866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_directed_frame:1; 22966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_receive_frame_antenna_selection:1; 23066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_frame_receive_during_atim_window:1; 23166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_protocol_version_error:1; 23266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_authentication_frame_icv_error:1; 23366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_null_key_to_authentication_frame:1; 23466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_icv_error:1; 23566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_crc_error:1; 23666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 23766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #else 23866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 23966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 24066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_crc_error:1; 24166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_icv_error:1; 24266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_null_key_to_authentication_frame:1; 24366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_authentication_frame_icv_error:1; 24466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_protocol_version_error:1; 24566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_frame_receive_during_atim_window:1; 24666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_receive_frame_antenna_selection:1; 24766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_directed_frame:1; 24866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_multicast_frame:1; 24966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_broadcast_frame:1; 25066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_replay:1; 25166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_mic_error:1; 25266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_decryption_method:2; 25366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_LNA_state:2; 25466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_AGC_state:8; 25566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_data_rate:3; 25666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_pre_type:1; 25766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_mod_type:1; 25866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R01_RESERVED:3; 25966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 26066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #endif 26166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 26266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} R01_DESCRIPTOR, *PR01_DESCRIPTOR; 26366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 26466101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _T01_DESCRIPTOR 26566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek{ 26666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 26766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 26866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 value; 26966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #ifdef _BIG_ENDIAN_ //20061009 anson's endian 27066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 27166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 27266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_rts_cts_duration:16; 27366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_fall_back_rate:3; 27466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_add_rts:1; 27566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_add_cts:1; 27666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_modulation_type:1; 27766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_plcp_header_length:1; 27866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_transmit_rate:3; 27966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_wep_id:2; 28066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_add_challenge_text:1; 28166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_inhibit_crc:1; 28266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_loop_back_wep_mode:1; 28366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_retry_abort_ebable:1; 28466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 28566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #else 28666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 28766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 28866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_retry_abort_ebable:1; 28966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_loop_back_wep_mode:1; 29066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_inhibit_crc:1; 29166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_add_challenge_text:1; 29266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_wep_id:2; 29366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_transmit_rate:3; 29466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_plcp_header_length:1; 29566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_modulation_type:1; 29666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_add_cts:1; 29766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_add_rts:1; 29866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_fall_back_rate:3; 29966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T01_rts_cts_duration:16; 30066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 30166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #endif 30266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 30366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} T01_DESCRIPTOR, *PT01_DESCRIPTOR; 30466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 30566101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _T02_DESCRIPTOR 30666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek{ 30766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 30866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 30966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 value; 31066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #ifdef _BIG_ENDIAN_ //20061009 add by anson's endian 31166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 31266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 31366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting 31466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS 31566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting 31666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_Tx_PktID:4; 31766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_MPDU_Cnt:4; 31866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_RTS_Cnt:4; 31966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_RESERVED:7; 32066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_complete:1; 32166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_abort_due_to_TBTT:1; 32266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_effective_transmission_rate:1; 32366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_without_encryption_due_to_wep_on_false:1; 32466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_discard_due_to_null_wep_key:1; 32566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_RESERVED_1:1; 32666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_out_of_MaxTxMSDULiftTime:1; 32766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_abort:1; 32866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_fail:1; 32966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 33066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #else 33166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 33266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 33366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_fail:1; 33466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_abort:1; 33566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_out_of_MaxTxMSDULiftTime:1; 33666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_RESERVED_1:1; 33766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_discard_due_to_null_wep_key:1; 33866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_without_encryption_due_to_wep_on_false:1; 33966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_effective_transmission_rate:1; 34066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_abort_due_to_TBTT:1; 34166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_transmit_complete:1; 34266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_RESERVED:7; 34366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_RTS_Cnt:4; 34466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_MPDU_Cnt:4; 34566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_Tx_PktID:4; 34666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_RESERVED_ID:2;// The same mechanism with T00 setting 34766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS 34866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T02_IsLastMpdu:1;// The same mechanism with T00 setting 34966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 35066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek #endif 35166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 35266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} T02_DESCRIPTOR, *PT02_DESCRIPTOR; 35366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 35466101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _DESCRIPTOR { // Skip length = 8 DWORD 35566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition 35666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 Descriptor_ID; 35766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------ 35866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 RESERVED[3]; 35966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 36066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 FragmentThreshold; 36166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 InternalUsed;//Only can be used by operation of descriptor definition 36266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 Type;// 0: 802.3 1:802.11 data frame 2:802.11 management frame 36366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 36466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 PreambleMode;// 0: short 1:long 36566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 TxRate; 36666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 FragmentCount; 36766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 EapFix; // For speed up key install 36866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 36966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For R00 and T00 ---------------------------------------------- 37066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 37166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 37266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek R00_DESCRIPTOR R00; 37366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek T00_DESCRIPTOR T00; 37466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 37566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 37666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For R01 and T01 ---------------------------------------------- 37766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 37866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 37966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek R01_DESCRIPTOR R01; 38066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek T01_DESCRIPTOR T01; 38166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 38266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 38366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For R02 and T02 ---------------------------------------------- 38466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 38566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 38666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R02; 38766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek T02_DESCRIPTOR T02; 38866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 38966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 39066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For R03 and T03 ---------------------------------------------- 39166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For software used 39266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek union 39366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 39466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 R03; 39566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 T03; 39666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek struct 39766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek { 39866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 buffer_number; 39966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 buffer_start_index; 40066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 buffer_total_size; 40166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 40266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek }; 40366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 40466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For storing the buffer 40566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ]; 40666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek void* buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q 40766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 40866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} DESCRIPTOR, *PDESCRIPTOR; 40966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 41066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 41166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define DEFAULT_NULL_PACKET_COUNT 180000 //20060828.1 Add. 180 seconds 41266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 41366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MAX_TXVGA_EEPROM 9 //How many word(u16) of EEPROM will be used for TxVGA 41466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek#define MAX_RF_PARAMETER 32 41566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 41666101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _TXVGA_FOR_50 { 41766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 ChanNo; 41866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 TxVgaValue; 41966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} TXVGA_FOR_50; 42066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 42166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 42266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//===================================================================== 42366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// Device related include 42466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek//===================================================================== 42566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 4269ce922fde7fb44a8690aa37d3c7f4f0cf5d921caPekka Enberg#include "wbusb_s.h" 4279ce922fde7fb44a8690aa37d3c7f4f0cf5d921caPekka Enberg#include "wb35reg_s.h" 4289ce922fde7fb44a8690aa37d3c7f4f0cf5d921caPekka Enberg#include "wb35tx_s.h" 4299ce922fde7fb44a8690aa37d3c7f4f0cf5d921caPekka Enberg#include "wb35rx_s.h" 43066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 43166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// For Hal using ================================================================== 43266101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _HW_DATA_T 43366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek{ 43466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For compatible with 33 43566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 revision; 43666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 BB3c_cal; // The value for Tx calibration comes from EEPROM 43766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 BB54_cal; // The value for Rx calibration comes from EEPROM 43866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 43966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 44066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For surprise remove 44166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 SurpriseRemove; // 0: Normal 1: Surprise remove 44266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 InitialResource; 44366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 IsKeyPreSet; 44466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 CalOneTime; // 20060630.1 44566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 44666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 VCO_trim; 44766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 44866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For Fix 1'st DMA bug 44966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 FragCount; 45066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2. 45166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 45266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //=============================================== 45366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // Definition for MAC address 45466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //=============================================== 455bd37b7fddf51431faf9c32cd22356421913cfce8Pekka Enberg u8 PermanentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are stored in EEPROM. + 2 to 8-byte alignment 456bd37b7fddf51431faf9c32cd22356421913cfce8Pekka Enberg u8 CurrentMacAddress[ETH_ALEN + 2]; // The Enthernet addr that are in used. + 2 to 8-byte alignment 45766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 45866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //===================================================================== 45966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // Definition for 802.11 46066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //===================================================================== 4618b384e0c3f85065a4986013d74d5585ed595cfa0Pekka Enberg u8 *bssid_pointer; // Used by hal_get_bssid for return value 46266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer 46366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 ssid[32];// maximum ssid length is 32 byte 46466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 46566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 AID; 46666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 ssid_length; 46766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 Channel; 46866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 46966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 ListenInterval; 47066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 CapabilityInformation; 47166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 47266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 BeaconPeriod; 47366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 ProbeDelay; 47466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 47566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 bss_type;// 0: IBSS_NET or 1:ESS_NET 47666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 preamble;// 0: short preamble, 1: long preamble 47766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 slot_time_select;// 9 or 20 value 47866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 phy_type;// Phy select 47966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 48066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 phy_para[MAX_RF_PARAMETER]; 48166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 phy_number; 48266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 48366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 CurrentRadioSw; // 20060320.2 0:On 1:Off 48466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 CurrentRadioHw; // 20060825 0:On 1:Off 48566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 4868b384e0c3f85065a4986013d74d5585ed595cfa0Pekka Enberg u8 *power_save_point; // Used by hal_get_power_save_mode for return value 48766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 cwmin; 48866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 desired_power_save; 48966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 dtim;// Is running dtim 49066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r 49166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 49266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 MaxReceiveLifeTime; 49366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 FragmentThreshold; 49466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 FragmentThreshold_tmp; 49566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 cwmax; 49666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 49766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment 49866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit) 49966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 CurrentDefaultKeyIndex; 50066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 CurrentDefaultKeyLength; 50166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 50266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //======================================================================== 50366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // Variable for each module 50466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //======================================================================== 50566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek WBUSB WbUsb; // Need WbUsb.h 50665144de7989badce1782cc3319d9b8b2b5805accPekka Enberg struct wb35_reg reg; // Need Wb35Reg.h 50766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek WB35TX Wb35Tx; // Need Wb35Tx.h 50866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek WB35RX Wb35Rx; // Need Wb35Rx.h 50966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 510deee7c8164e62690aefefb3503bc4c4672b3e020Pekka Enberg struct timer_list LEDTimer;// For LED 51166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 51266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 LEDpoint;// For LED 51366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 51466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 dto_tx_retry_count; // LA20040210_DTO kevin 51566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 dto_tx_frag_count; // LA20040210_DTO kevin 51666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 rx_ok_count[13]; // index=0: total rx ok 51766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //u32 rx_ok_bytes[13]; // index=0, total rx ok bytes 51866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 rx_err_count[13]; // index=0: total rx err 51966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 52066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek //for Tx debug 52166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 tx_TBTT_start_count; 52266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 tx_ETR_count; 52366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 tx_WepOn_false_count; 52466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 tx_Null_key_count; 52566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 tx_retry_count[8]; 52666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 52766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 PowerIndexFromEEPROM; // For 2412MHz 52866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 power_index; 52966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 IsWaitJoinComplete; // TRUE: set join request 53066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 band; 53166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 53266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 SoftwareSet; 53366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 Reserved_s; 53466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 53566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 IsInitOK; // 0: Driver starting 1: Driver init OK 53666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 53766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For Phy calibration 53866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek s32 iq_rsdl_gain_tx_d2; 53966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek s32 iq_rsdl_phase_tx_d2; 54066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 txvga_setting_for_cal; // 20060703.1 Add 54166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 54266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value 54366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u8 TxVgaFor24[16]; // Max is 14, 2 for alignment 54466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek TXVGA_FOR_50 TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments 54566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 54666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 Scan_Interval; 54766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u16 RESERVED6; 54866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 54966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // LED control 55066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 LED_control; 55166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // LED_control 4 byte: Gray_Led_1[3] Gray_Led_0[2] Led[1] Led[0] 55266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // Gray_Led 55366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For Led gray setting 55466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // Led 55566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // 0: normal control, LED behavior will decide by EEPROM setting 55666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // 1: Turn off specific LED 55766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // 2: Always on specific LED 55866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // 3: slow blinking specific LED 55966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // 4: fast blinking specific LED 56066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // 5: WPS led control is set. Led0 is Red, Led1 id Green 56166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // Led[1] is parameter for WPS LED mode 56266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // // 1:InProgress 2: Error 3: Session overlap 4: Success 20061108 control 56366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 56466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 LED_LinkOn; //Turn LED on control 56566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 LED_Scanning; // Let LED in scan process control 56666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 LED_Blinking; // Temp variable for shining 56766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 RxByteCountLast; 56866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 TxByteCountLast; 56966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 57044e8541c5e14b40a773e830df339eddbcd0cb7ecPekka Enberg atomic_t SurpriseRemoveCount; 57166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 57266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For global timer 57366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 time_count;//TICK_TIME_100ms 1 = 100ms 57466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 57566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // For error recover 57666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 HwStop; 57766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 57866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // 20060828.1 for avoid AP disconnect 57966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NullPacketCount; 58066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 58166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} hw_data_t, *phw_data_t; 58266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 58366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek// The mapping of Rx and Tx descriptor field 58466101de10957e07a6fd0365d5af9adf650246d14Pavel Machektypedef struct _HAL_RATE 58566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek{ 58666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // DSSS 58766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 RESERVED_0; 58866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate2MS; 58966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate55MS; 59066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate11MS; 59166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 59266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 RESERVED_1[4]; 59366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 59466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate1M; 59566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate2ML; 59666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate55ML; 59766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate11ML; 59866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 59966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 RESERVED_2[4]; 60066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 60166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek // OFDM 60266101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate6M; 60366101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate9M; 60466101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate12M; 60566101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate18M; 60666101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate24M; 60766101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate36M; 60866101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate48M; 60966101de10957e07a6fd0365d5af9adf650246d14Pavel Machek u32 NumRate54M; 61066101de10957e07a6fd0365d5af9adf650246d14Pavel Machek} HAL_RATE, *PHAL_RATE; 61166101de10957e07a6fd0365d5af9adf650246d14Pavel Machek 61280aba53616a5f2f97adf386a2a3ccd5fb0dbfdd6Pekka Enberg#endif 613