1b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* 2b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang * Freescale USB device/endpoint management registers 3b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang */ 4b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#ifndef __FSL_USB2_UDC_H 5b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define __FSL_USB2_UDC_H 6b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 7b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* ### define USB registers here 8b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang */ 9b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_MAX_CTRL_PAYLOAD 64 10b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_DR_SYS_OFFSET 0x400 11b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 12b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* USB DR device mode registers (Little Endian) */ 13b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstruct usb_dr_device { 14b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* Capability register */ 15b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res1[256]; 16b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u16 caplength; /* Capability Register Length */ 17b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u16 hciversion; /* Host Controller Interface Version */ 1825985edcedea6396277003854657b5f3cb31a628Lucas De Marchi u32 hcsparams; /* Host Controller Structural Parameters */ 19b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 hccparams; /* Host Controller Capability Parameters */ 20b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res2[20]; 21b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 dciversion; /* Device Controller Interface Version */ 22b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 dccparams; /* Device Controller Capability Parameters */ 23b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res3[24]; 24b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* Operation register */ 25b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usbcmd; /* USB Command Register */ 26b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usbsts; /* USB Status Register */ 27b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usbintr; /* USB Interrupt Enable Register */ 28b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 frindex; /* Frame Index Register */ 29b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res4[4]; 30b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 deviceaddr; /* Device Address */ 31b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endpointlistaddr; /* Endpoint List Address Register */ 32b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res5[4]; 33b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 burstsize; /* Master Interface Data Burst Size Register */ 34b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ 35b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res6[24]; 36b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 configflag; /* Configure Flag Register */ 37b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 portsc1; /* Port 1 Status and Control Register */ 38b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res7[28]; 39b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 otgsc; /* On-The-Go Status and Control */ 40b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usbmode; /* USB Mode Register */ 41b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptsetupstat; /* Endpoint Setup Status Register */ 42b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endpointprime; /* Endpoint Initialization Register */ 43b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptflush; /* Endpoint Flush Register */ 44b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptstatus; /* Endpoint Status Register */ 45b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptcomplete; /* Endpoint Complete Register */ 46b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptctrl[6]; /* Endpoint Control Registers */ 47b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang}; 48b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 49b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* USB DR host mode registers (Little Endian) */ 50b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstruct usb_dr_host { 51b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* Capability register */ 52b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res1[256]; 53b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u16 caplength; /* Capability Register Length */ 54b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u16 hciversion; /* Host Controller Interface Version */ 5525985edcedea6396277003854657b5f3cb31a628Lucas De Marchi u32 hcsparams; /* Host Controller Structural Parameters */ 56b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 hccparams; /* Host Controller Capability Parameters */ 57b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res2[20]; 58b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 dciversion; /* Device Controller Interface Version */ 59b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 dccparams; /* Device Controller Capability Parameters */ 60b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res3[24]; 61b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* Operation register */ 62b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usbcmd; /* USB Command Register */ 63b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usbsts; /* USB Status Register */ 64b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usbintr; /* USB Interrupt Enable Register */ 65b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 frindex; /* Frame Index Register */ 66b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res4[4]; 67b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 periodiclistbase; /* Periodic Frame List Base Address Register */ 68b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 asynclistaddr; /* Current Asynchronous List Address Register */ 69b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res5[4]; 70b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 burstsize; /* Master Interface Data Burst Size Register */ 71b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ 72b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res6[24]; 73b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 configflag; /* Configure Flag Register */ 74b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 portsc1; /* Port 1 Status and Control Register */ 75b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res7[28]; 76b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 otgsc; /* On-The-Go Status and Control */ 77b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usbmode; /* USB Mode Register */ 78b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptsetupstat; /* Endpoint Setup Status Register */ 79b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endpointprime; /* Endpoint Initialization Register */ 80b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptflush; /* Endpoint Flush Register */ 81b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptstatus; /* Endpoint Status Register */ 82b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptcomplete; /* Endpoint Complete Register */ 83b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 endptctrl[6]; /* Endpoint Control Registers */ 84b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang}; 85b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 86b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* non-EHCI USB system interface registers (Big Endian) */ 87b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstruct usb_sys_interface { 88b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 snoop1; 89b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 snoop2; 90b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 age_cnt_thresh; /* Age Count Threshold Register */ 91b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 pri_ctrl; /* Priority Control Register */ 92b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 si_ctrl; /* System Interface Control Register */ 93b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 res[236]; 94b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 control; /* General Purpose Control Register */ 95b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang}; 96b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 97b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* ep0 transfer state */ 98b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define WAIT_FOR_SETUP 0 99b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DATA_STATE_XMIT 1 100b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DATA_STATE_NEED_ZLP 2 101b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define WAIT_FOR_OUT_STATUS 3 102b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DATA_STATE_RECV 4 103b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 1044365831dadfeeeb4c9f8c4944e48ccf78c27f845Li Yang/* Device Controller Capability Parameter register */ 1054365831dadfeeeb4c9f8c4944e48ccf78c27f845Li Yang#define DCCPARAMS_DC 0x00000080 1064365831dadfeeeb4c9f8c4944e48ccf78c27f845Li Yang#define DCCPARAMS_DEN_MASK 0x0000001f 1074365831dadfeeeb4c9f8c4944e48ccf78c27f845Li Yang 108b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Frame Index Register Bit Masks */ 109b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_FRINDEX_MASKS 0x3fff 110b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* USB CMD Register Bit Masks */ 111b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_RUN_STOP 0x00000001 112b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_CTRL_RESET 0x00000002 113b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010 114b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020 115b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_INT_AA_DOORBELL 0x00000040 116b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ASP 0x00000300 117b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800 118b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_SUTW 0x00002000 119b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ATDTW 0x00004000 120b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC 0x00FF0000 121b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 122b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 15,3,2 are frame list size */ 123b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_FRAME_SIZE_1024 0x00000000 124b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_FRAME_SIZE_512 0x00000004 125b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_FRAME_SIZE_256 0x00000008 126b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_FRAME_SIZE_128 0x0000000C 127b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_FRAME_SIZE_64 0x00008000 128b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_FRAME_SIZE_32 0x00008004 129b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_FRAME_SIZE_16 0x00008008 130b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_FRAME_SIZE_8 0x0000800C 131b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 132b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 9-8 are async schedule park mode count */ 133b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ASP_00 0x00000000 134b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ASP_01 0x00000100 135b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ASP_10 0x00000200 136b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ASP_11 0x00000300 137b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ASP_BIT_POS 8 138b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 139b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 23-16 are interrupt threshold control */ 140b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_NO_THRESHOLD 0x00000000 141b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_1_MICRO_FRM 0x00010000 142b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_2_MICRO_FRM 0x00020000 143b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_4_MICRO_FRM 0x00040000 144b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_8_MICRO_FRM 0x00080000 145b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_16_MICRO_FRM 0x00100000 146b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_32_MICRO_FRM 0x00200000 147b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_64_MICRO_FRM 0x00400000 148b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CMD_ITC_BIT_POS 16 149b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 150b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* USB STS Register Bit Masks */ 151b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_INT 0x00000001 152b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_ERR 0x00000002 153b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_PORT_CHANGE 0x00000004 154b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_FRM_LST_ROLL 0x00000008 155b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_SYS_ERR 0x00000010 156b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_IAA 0x00000020 157b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_RESET 0x00000040 158b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_SOF 0x00000080 159b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_SUSPEND 0x00000100 160b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_HC_HALTED 0x00001000 161b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_RCL 0x00002000 162b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_PERIODIC_SCHEDULE 0x00004000 163b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_STS_ASYNC_SCHEDULE 0x00008000 164b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 165b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* USB INTR Register Bit Masks */ 166b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_INT_EN 0x00000001 167b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_ERR_INT_EN 0x00000002 168b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_PTC_DETECT_EN 0x00000004 169b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_FRM_LST_ROLL_EN 0x00000008 170b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_SYS_ERR_EN 0x00000010 171b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_ASYN_ADV_EN 0x00000020 172b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_RESET_EN 0x00000040 173b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_SOF_EN 0x00000080 174b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_INTR_DEVICE_SUSPEND 0x00000100 175b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 176b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Device Address bit masks */ 177b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_DEVICE_ADDRESS_MASK 0xFE000000 178b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_DEVICE_ADDRESS_BIT_POS 25 179b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 180b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* endpoint list address bit masks */ 181b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_EP_LIST_ADDRESS_MASK 0xfffff800 182b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 183b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* PORTSCX Register Bit Masks */ 184b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001 185b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002 186b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_ENABLE 0x00000004 187b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008 188b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_OVER_CURRENT_ACT 0x00000010 189b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_OVER_CURRENT_CHG 0x00000020 190b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_FORCE_RESUME 0x00000040 191b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_SUSPEND 0x00000080 192b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_RESET 0x00000100 193b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_LINE_STATUS_BITS 0x00000C00 194b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_POWER 0x00001000 195b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000 196b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_TEST_CTRL 0x000F0000 197b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000 198b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000 199b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000 200b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PHY_LOW_POWER_SPD 0x00800000 201b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000 202b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_SPEED_MASK 0x0C000000 203b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_WIDTH 0x10000000 204b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PHY_TYPE_SEL 0xC0000000 205b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 206b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 11-10 are line status */ 207b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_LINE_STATUS_SE0 0x00000000 208b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_LINE_STATUS_JSTATE 0x00000400 209b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_LINE_STATUS_KSTATE 0x00000800 210b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_LINE_STATUS_UNDEF 0x00000C00 211b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_LINE_STATUS_BIT_POS 10 212b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 213b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 15-14 are port indicator control */ 214b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PIC_OFF 0x00000000 215b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PIC_AMBER 0x00004000 216b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PIC_GREEN 0x00008000 217b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PIC_UNDEF 0x0000C000 218b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PIC_BIT_POS 14 219b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 220b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 19-16 are port test control */ 221b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTC_DISABLE 0x00000000 222b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTC_JSTATE 0x00010000 223b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTC_KSTATE 0x00020000 224b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTC_SEQNAK 0x00030000 225b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTC_PACKET 0x00040000 226b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTC_FORCE_EN 0x00050000 227b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTC_BIT_POS 16 228b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 229b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 27-26 are port speed */ 230b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_SPEED_FULL 0x00000000 231b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_SPEED_LOW 0x04000000 232b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_SPEED_HIGH 0x08000000 233b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PORT_SPEED_UNDEF 0x0C000000 234b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_SPEED_BIT_POS 26 235b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 236b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 28 is parallel transceiver width for UTMI interface */ 237b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTW 0x10000000 238b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTW_8BIT 0x00000000 239b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTW_16BIT 0x10000000 240b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 241b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 31-30 are port transceiver select */ 242b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTS_UTMI 0x00000000 243b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTS_ULPI 0x80000000 244b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTS_FSLS 0xC0000000 245b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PORTSCX_PTS_BIT_POS 30 246b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 247b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* otgsc Register Bit Masks */ 248b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 249b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_CTRL_VUSB_CHARGE 0x00000002 250b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_CTRL_OTG_TERM 0x00000008 251b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_CTRL_DATA_PULSING 0x00000010 252b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_STS_USB_ID 0x00000100 253b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_STS_A_VBUS_VALID 0x00000200 254b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_STS_A_SESSION_VALID 0x00000400 255b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_STS_B_SESSION_VALID 0x00000800 256b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_STS_B_SESSION_END 0x00001000 257b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_STS_1MS_TOGGLE 0x00002000 258b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_STS_DATA_PULSING 0x00004000 259b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTSTS_USB_ID 0x00010000 260b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTSTS_A_VBUS_VALID 0x00020000 261b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTSTS_A_SESSION_VALID 0x00040000 262b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTSTS_B_SESSION_VALID 0x00080000 263b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTSTS_B_SESSION_END 0x00100000 264b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTSTS_1MS 0x00200000 265b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTSTS_DATA_PULSING 0x00400000 266b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTR_USB_ID 0x01000000 267b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTR_A_VBUS_VALID 0x02000000 268b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTR_A_SESSION_VALID 0x04000000 269b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTR_B_SESSION_VALID 0x08000000 270b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTR_B_SESSION_END 0x10000000 271b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTR_1MS_TIMER 0x20000000 272b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define OTGSC_INTR_DATA_PULSING 0x40000000 273b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 274b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* USB MODE Register Bit Masks */ 275b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_MODE_CTRL_MODE_IDLE 0x00000000 276b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_MODE_CTRL_MODE_DEVICE 0x00000002 277b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_MODE_CTRL_MODE_HOST 0x00000003 2782ea6698d7b9266da53044dddc5f6743adf097fb5Anatolij Gustschin#define USB_MODE_CTRL_MODE_MASK 0x00000003 279b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_MODE_CTRL_MODE_RSV 0x00000001 2802ea6698d7b9266da53044dddc5f6743adf097fb5Anatolij Gustschin#define USB_MODE_ES 0x00000004 /* Endian Select */ 281b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_MODE_SETUP_LOCK_OFF 0x00000008 282b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_MODE_STREAM_DISABLE 0x00000010 283b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Endpoint Flush Register */ 284b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPFLUSH_TX_OFFSET 0x00010000 285b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPFLUSH_RX_OFFSET 0x00000000 286b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 287b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Endpoint Setup Status bit masks */ 288b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_SETUP_STATUS_MASK 0x0000003F 289b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_SETUP_STATUS_EP0 0x00000001 290b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 291b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* ENDPOINTCTRLx Register Bit Masks */ 292b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_TX_ENABLE 0x00800000 293b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */ 294b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */ 295b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_TX_TYPE 0x000C0000 296b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */ 297b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_TX_EP_STALL 0x00010000 298b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_RX_ENABLE 0x00000080 299b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */ 300b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */ 301b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_RX_TYPE 0x0000000C 302b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */ 303b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_RX_EP_STALL 0x00000001 304b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 305b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* bit 19-18 and 3-2 are endpoint type */ 306b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_EP_TYPE_CONTROL 0 307b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_EP_TYPE_ISO 1 308b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_EP_TYPE_BULK 2 309b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_EP_TYPE_INTERRUPT 3 310b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_TX_EP_TYPE_SHIFT 18 311b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EPCTRL_RX_EP_TYPE_SHIFT 2 312b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 313b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* SNOOPn Register Bit Masks */ 314b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_ADDRESS_MASK 0xFFFFF000 315b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_ZERO 0x00 /* snooping disable */ 316b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */ 317b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_8KB 0x0C 318b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_16KB 0x0D 319b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_32KB 0x0E 320b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_64KB 0x0F 321b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_128KB 0x10 322b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_256KB 0x11 323b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_512KB 0x12 324b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_1MB 0x13 325b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_2MB 0x14 326b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_4MB 0x15 327b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_8MB 0x16 328b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_16MB 0x17 329b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_32MB 0x18 330b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_64MB 0x19 331b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_128MB 0x1A 332b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_256MB 0x1B 333b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_512MB 0x1C 334b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_1GB 0x1D 335b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */ 336b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 337b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* pri_ctrl Register Bit Masks */ 338b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PRI_CTRL_PRI_LVL1 0x0000000C 339b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define PRI_CTRL_PRI_LVL0 0x00000003 340b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 341b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* si_ctrl Register Bit Masks */ 342b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SI_CTRL_ERR_DISABLE 0x00000010 343b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SI_CTRL_IDRC_DISABLE 0x00000008 344b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SI_CTRL_RD_SAFE_EN 0x00000004 345b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002 346b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001 347b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 348b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* control Register Bit Masks */ 349b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CTRL_IOENB 0x00000004 350b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_CTRL_ULPI_INT0EN 0x00000001 351b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 352b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Endpoint Queue Head data struct 353b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang * Rem: all the variables of qh are LittleEndian Mode 354b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr 355b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang */ 356b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstruct ep_queue_head { 357b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len 358b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang and IOS(15) */ 359b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */ 360b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */ 361b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15), 362b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang MultO(11-10), STS (7-0) */ 363b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */ 364b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */ 365b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */ 366b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */ 367b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */ 368b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 res1; 369b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 setup_buffer[8]; /* Setup data 8 bytes */ 370b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 res2[4]; 371b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang}; 372b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 373b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Endpoint Queue Head Bit Masks */ 374b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_MULT_POS 30 375b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_ZLT_SEL 0x20000000 376b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16 377b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff) 378b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_IOS 0x00008000 379b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001 380b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_IOC 0x00008000 381b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_MULTO 0x00000C00 382b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_STATUS_HALT 0x00000040 383b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080 384b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF 385b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0 386b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_QUEUE_FRINDEX_MASK 0x000007FF 387b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_MAX_LENGTH_TRANSFER 0x4000 388b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 389b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Endpoint Transfer Descriptor data struct */ 390b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Rem: all the variables of td are LittleEndian Mode */ 391b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstruct ep_td_struct { 392b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set 393b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang indicate invalid */ 394b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 size_ioc_sts; /* Total bytes (30-16), IOC (15), 395b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang MultO(11-10), STS (7-0) */ 396b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr0; /* Buffer pointer Page 0 */ 397b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr1; /* Buffer pointer Page 1 */ 398b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr2; /* Buffer pointer Page 2 */ 399b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr3; /* Buffer pointer Page 3 */ 400b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 buff_ptr4; /* Buffer pointer Page 4 */ 401b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 res; 402b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* 32 bytes */ 403b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang dma_addr_t td_dma; /* dma address for this td */ 404b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* virtual address of next td specified in next_td_ptr */ 405b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct ep_td_struct *next_td_virt; 406b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang}; 407b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 408b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Endpoint Transfer Descriptor bit Masks */ 409b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_NEXT_TERMINATE 0x00000001 410b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_IOC 0x00008000 411b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_STATUS_ACTIVE 0x00000080 412b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_STATUS_HALTED 0x00000040 413b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_STATUS_DATA_BUFF_ERR 0x00000020 414b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_STATUS_TRANSACTION_ERR 0x00000008 415b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_RESERVED_FIELDS 0x80007300 416b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_ADDR_MASK 0xFFFFFFE0 417b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_PACKET_SIZE 0x7FFF0000 418b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_LENGTH_BIT_POS 16 419b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_ERROR_MASK (DTD_STATUS_HALTED | \ 420b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang DTD_STATUS_DATA_BUFF_ERR | \ 421b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang DTD_STATUS_TRANSACTION_ERR) 422b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Alignment requirements; must be a power of two */ 423b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DTD_ALIGNMENT 0x20 424b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define QH_ALIGNMENT 2048 425b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 426b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* Controller dma boundary */ 427b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define UDC_DMA_BOUNDARY 0x1000 428b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 429b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/*-------------------------------------------------------------------------*/ 430b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 431b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* ### driver private data 432b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang */ 433b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstruct fsl_req { 434b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct usb_request req; 435b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct list_head queue; 436b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang /* ep_queue() func will add 437b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang a request->queue into a udc_ep->queue 'd tail */ 438b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct fsl_ep *ep; 439b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned mapped:1; 440b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 441b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct ep_td_struct *head, *tail; /* For dTD List 442b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang cpu endian Virtual addr */ 443b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned int dtd_count; 444b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang}; 445b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 446b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define REQ_UNCOMPLETE 1 447b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 448b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstruct fsl_ep { 449b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct usb_ep ep; 450b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct list_head queue; 451b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct fsl_udc *udc; 452b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct ep_queue_head *qh; 453b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang const struct usb_endpoint_descriptor *desc; 454b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct usb_gadget *gadget; 455b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 456b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang char name[14]; 457b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned stopped:1; 458b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang}; 459b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 460b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_DIR_IN 1 461b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define EP_DIR_OUT 0 462b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 463b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstruct fsl_udc { 464b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct usb_gadget gadget; 465b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct usb_gadget_driver *driver; 46609ba0def9aefc16c1c8a6d166f024c9d704f0ab0Anatolij Gustschin struct fsl_usb2_platform_data *pdata; 4677483cff8a3ea4c31a677a6ac1a4eb3d78adcb9ccWill Newton struct completion *done; /* to make sure release() is done */ 468b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct fsl_ep *eps; 469b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned int max_ep; 470b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned int irq; 471b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 472b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct usb_ctrlrequest local_setup_buff; 473b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang spinlock_t lock; 4748675381109b0eb1c948a423c2b35e3f4509cb25eHeikki Krogerus struct usb_phy *transceiver; 475b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned softconnect:1; 476b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned vbus_active:1; 477b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned stopped:1; 478b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned remote_wakeup:1; 47983722bc9430424de1614ff31696f73a40b3d81a9Anatolij Gustschin unsigned already_stopped:1; 48009ba0def9aefc16c1c8a6d166f024c9d704f0ab0Anatolij Gustschin unsigned big_endian_desc:1; 481b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 482b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */ 483b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct fsl_req *status_req; /* ep0 status request */ 484b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang struct dma_pool *td_pool; /* dma pool for DTD */ 485b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang enum fsl_usb2_phy_modes phy_mode; 486b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 487b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang size_t ep_qh_size; /* size after alignment adjustment*/ 488b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang dma_addr_t ep_qh_dma; /* dma address of QH */ 489b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 4907483cff8a3ea4c31a677a6ac1a4eb3d78adcb9ccWill Newton u32 max_pipes; /* Device max pipes */ 49183722bc9430424de1614ff31696f73a40b3d81a9Anatolij Gustschin u32 bus_reset; /* Device is bus resetting */ 492b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 resume_state; /* USB state to resume */ 493b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 usb_state; /* USB current state */ 494b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 ep0_state; /* Endpoint zero state */ 495b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u32 ep0_dir; /* Endpoint zero direction: can be 496b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang USB_DIR_IN or USB_DIR_OUT */ 497b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang u8 device_address; /* Device USB address */ 498b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang}; 499b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 500b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/*-------------------------------------------------------------------------*/ 501b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 502b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#ifdef DEBUG 503b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \ 504441b62c1edb986827154768d89bbac0ba779984fHarvey Harrison __func__, ## args) 505b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#else 506b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define DBG(fmt, args...) do{}while(0) 507b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#endif 508b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 509b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#if 0 510b504882da539c17ce6fee9da2a97f2fafabd495dLi Yangstatic void dump_msg(const char *label, const u8 * buf, unsigned int length) 511b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang{ 512b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang unsigned int start, num, i; 513b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang char line[52], *p; 514b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 515b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang if (length >= 512) 516b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang return; 517b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang DBG("%s, length %u:\n", label, length); 518b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang start = 0; 519b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang while (length > 0) { 520b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang num = min(length, 16u); 521b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang p = line; 522b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang for (i = 0; i < num; ++i) { 523b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang if (i == 8) 524b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang *p++ = ' '; 525b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang sprintf(p, " %02x", buf[i]); 526b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang p += 3; 527b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang } 528b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang *p = 0; 529b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang printk(KERN_DEBUG "%6x: %s\n", start, line); 530b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang buf += num; 531b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang start += num; 532b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang length -= num; 533b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang } 534b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang} 535b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#endif 536b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 537b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#ifdef VERBOSE 538b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define VDBG DBG 539b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#else 540b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define VDBG(stuff...) do{}while(0) 541b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#endif 542b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 54300274921a052d3232d9f00856387fb269ac0af11David Brownell#define ERR(stuff...) pr_err("udc: " stuff) 544b6c63937001889af6fe431aaba97e59d04e028e7Arjan van de Ven#define WARNING(stuff...) pr_warning("udc: " stuff) 54500274921a052d3232d9f00856387fb269ac0af11David Brownell#define INFO(stuff...) pr_info("udc: " stuff) 546b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 547b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/*-------------------------------------------------------------------------*/ 548b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 549b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* ### Add board specific defines here 550b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang */ 551b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 552b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* 553b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang * ### pipe direction macro from device view 554b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang */ 555b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_RECV 0 /* OUT EP */ 556b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define USB_SEND 1 /* IN EP */ 557b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 558b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang/* 559b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang * ### internal used help routines. 560b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang */ 561b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define ep_index(EP) ((EP)->desc->bEndpointAddress&0xF) 562b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define ep_maxpacket(EP) ((EP)->ep.maxpacket) 563b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \ 564b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang USB_DIR_IN ):((EP)->desc->bEndpointAddress \ 565b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang & USB_DIR_IN)==USB_DIR_IN) 566b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \ 567b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang &udc->eps[pipe]) 568b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \ 569b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang * 2 + ((windex & USB_DIR_IN) ? 1 : 0)) 570b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP)) 571b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang 5726414e94c203d92b163ca61b5f51a25b80a621dbeLi Yangstatic inline struct ep_queue_head *get_qh_by_ep(struct fsl_ep *ep) 5736414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang{ 5746414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang /* we only have one ep0 structure but two queue heads */ 5756414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang if (ep_index(ep) != 0) 5766414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang return ep->qh; 5776414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang else 5786414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang return &ep->udc->ep_qh[(ep->udc->ep0_dir == 5796414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang USB_DIR_IN) ? 1 : 0]; 5806414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang} 5816414e94c203d92b163ca61b5f51a25b80a621dbeLi Yang 58254e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetskistruct platform_device; 58354e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski#ifdef CONFIG_ARCH_MXC 58454e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetskiint fsl_udc_clk_init(struct platform_device *pdev); 58554e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetskivoid fsl_udc_clk_finalize(struct platform_device *pdev); 58654e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetskivoid fsl_udc_clk_release(void); 58754e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski#else 58854e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetskistatic inline int fsl_udc_clk_init(struct platform_device *pdev) 58954e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski{ 59054e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski return 0; 59154e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski} 59254e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetskistatic inline void fsl_udc_clk_finalize(struct platform_device *pdev) 59354e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski{ 59454e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski} 59554e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetskistatic inline void fsl_udc_clk_release(void) 59654e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski{ 59754e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski} 59854e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski#endif 59954e4026b64a970303349b952866641a7804ef594Guennadi Liakhovetski 600b504882da539c17ce6fee9da2a97f2fafabd495dLi Yang#endif 601