goku_udc.h revision 1da177e4c3f41524e886b7f1b8a0c1fc7321cac 
1/*
2 * Toshiba TC86C001 ("Goku-S") USB Device Controller driver
3 *
4 * Copyright (C) 2000-2002 Lineo
5 *      by Stuart Lynne, Tom Rushworth, and Bruce Balden
6 * Copyright (C) 2002 Toshiba Corporation
7 * Copyright (C) 2003 MontaVista Software (source@mvista.com)
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2.  This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14/*
15 * PCI BAR 0 points to these registers.
16 */
17struct goku_udc_regs {
18	/* irq management */
19	u32	int_status;		/* 0x000 */
20	u32	int_enable;
21#define INT_SUSPEND		0x00001		/* or resume */
22#define INT_USBRESET		0x00002
23#define INT_ENDPOINT0		0x00004
24#define INT_SETUP		0x00008
25#define INT_STATUS		0x00010
26#define INT_STATUSNAK		0x00020
27#define INT_EPxDATASET(n)	(0x00020 << (n))	/* 0 < n < 4 */
28#	define INT_EP1DATASET		0x00040
29#	define INT_EP2DATASET		0x00080
30#	define INT_EP3DATASET		0x00100
31#define INT_EPnNAK(n)		(0x00100 < (n))		/* 0 < n < 4 */
32#	define INT_EP1NAK		0x00200
33#	define INT_EP2NAK		0x00400
34#	define INT_EP3NAK		0x00800
35#define INT_SOF			0x01000
36#define INT_ERR			0x02000
37#define INT_MSTWRSET		0x04000
38#define INT_MSTWREND		0x08000
39#define INT_MSTWRTMOUT		0x10000
40#define INT_MSTRDEND		0x20000
41#define INT_SYSERROR		0x40000
42#define INT_PWRDETECT		0x80000
43
44#define	INT_DEVWIDE		(INT_PWRDETECT|INT_SYSERROR/*|INT_ERR*/|INT_USBRESET|INT_SUSPEND)
45#define	INT_EP0 		(INT_SETUP|INT_ENDPOINT0/*|INT_STATUS*/|INT_STATUSNAK)
46
47	u32	dma_master;
48#define MST_EOPB_DIS		0x0800
49#define MST_EOPB_ENA		0x0400
50#define MST_TIMEOUT_DIS		0x0200
51#define MST_TIMEOUT_ENA		0x0100
52#define MST_RD_EOPB		0x0080		/* write-only */
53#define MST_RD_RESET		0x0040
54#define MST_WR_RESET		0x0020
55#define MST_RD_ENA		0x0004		/* 1:start, 0:ignore */
56#define MST_WR_ENA		0x0002		/* 1:start, 0:ignore */
57#define MST_CONNECTION		0x0001		/* 0 for ep1out/ep2in */
58
59#define MST_R_BITS		(MST_EOPB_DIS|MST_EOPB_ENA \
60					|MST_RD_ENA|MST_RD_RESET)
61#define MST_W_BITS		(MST_TIMEOUT_DIS|MST_TIMEOUT_ENA \
62					|MST_WR_ENA|MST_WR_RESET)
63#define MST_RW_BITS		(MST_R_BITS|MST_W_BITS \
64					|MST_CONNECTION)
65
66/* these values assume (dma_master & MST_CONNECTION) == 0 */
67#define UDC_MSTWR_ENDPOINT        1
68#define UDC_MSTRD_ENDPOINT        2
69
70	/* dma master write */
71	u32	out_dma_start;
72	u32	out_dma_end;
73	u32	out_dma_current;
74
75	/* dma master read */
76	u32	in_dma_start;
77	u32	in_dma_end;
78	u32	in_dma_current;
79
80	u32	power_detect;
81#define PW_DETECT		0x04
82#define PW_RESETB		0x02
83#define PW_PULLUP		0x01
84
85	u8	_reserved0 [0x1d8];
86
87	/* endpoint registers */
88	u32	ep_fifo [4];		/* 0x200 */
89	u8	_reserved1 [0x10];
90	u32	ep_mode [4];		/* only 1-3 valid */
91	u8	_reserved2 [0x10];
92
93	u32	ep_status [4];
94#define EPxSTATUS_TOGGLE	0x40
95#define EPxSTATUS_SUSPEND	0x20
96#define EPxSTATUS_EP_MASK	(0x07<<2)
97#	define EPxSTATUS_EP_READY	(0<<2)
98#	define EPxSTATUS_EP_DATAIN	(1<<2)
99#	define EPxSTATUS_EP_FULL	(2<<2)
100#	define EPxSTATUS_EP_TX_ERR	(3<<2)
101#	define EPxSTATUS_EP_RX_ERR	(4<<2)
102#	define EPxSTATUS_EP_BUSY	(5<<2)
103#	define EPxSTATUS_EP_STALL	(6<<2)
104#	define EPxSTATUS_EP_INVALID	(7<<2)
105#define EPxSTATUS_FIFO_DISABLE	0x02
106#define EPxSTATUS_STAGE_ERROR	0x01
107
108	u8	_reserved3 [0x10];
109	u32	EPxSizeLA[4];
110#define PACKET_ACTIVE		(1<<7)
111#define DATASIZE		0x7f
112	u8	_reserved3a [0x10];
113	u32	EPxSizeLB[4];		/* only 1,2 valid */
114	u8	_reserved3b [0x10];
115	u32	EPxSizeHA[4];		/* only 1-3 valid */
116	u8	_reserved3c [0x10];
117	u32	EPxSizeHB[4];		/* only 1,2 valid */
118	u8	_reserved4[0x30];
119
120	/* SETUP packet contents */
121	u32	bRequestType;		/* 0x300 */
122	u32	bRequest;
123	u32	wValueL;
124	u32	wValueH;
125	u32	wIndexL;
126	u32	wIndexH;
127	u32	wLengthL;
128	u32	wLengthH;
129
130	/* command interaction/handshaking */
131	u32	SetupRecv;		/* 0x320 */
132	u32	CurrConfig;
133	u32	StdRequest;
134	u32	Request;
135	u32	DataSet;
136#define DATASET_A(epnum)	(1<<(2*(epnum)))
137#define DATASET_B(epnum)	(2<<(2*(epnum)))
138#define DATASET_AB(epnum)	(3<<(2*(epnum)))
139	u8	_reserved5[4];
140
141	u32	UsbState;
142#define USBSTATE_CONFIGURED	0x04
143#define USBSTATE_ADDRESSED	0x02
144#define USBSTATE_DEFAULT	0x01
145
146	u32	EOP;
147
148	u32	Command;		/* 0x340 */
149#define COMMAND_SETDATA0	2
150#define COMMAND_RESET		3
151#define COMMAND_STALL		4
152#define COMMAND_INVALID		5
153#define COMMAND_FIFO_DISABLE	7
154#define COMMAND_FIFO_ENABLE	8
155#define COMMAND_INIT_DESCRIPTOR	9
156#define COMMAND_FIFO_CLEAR	10	/* also stall */
157#define COMMAND_STALL_CLEAR	11
158#define COMMAND_EP(n)		((n) << 4)
159
160	u32	EPxSingle;
161	u8	_reserved6[4];
162	u32	EPxBCS;
163	u8	_reserved7[8];
164	u32	IntControl;
165#define ICONTROL_STATUSNAK	1
166	u8	_reserved8[4];
167
168	u32	reqmode;	// 0x360 standard request mode, low 8 bits
169#define G_REQMODE_SET_INTF	(1<<7)
170#define G_REQMODE_GET_INTF	(1<<6)
171#define G_REQMODE_SET_CONF	(1<<5)
172#define G_REQMODE_GET_CONF	(1<<4)
173#define G_REQMODE_GET_DESC	(1<<3)
174#define G_REQMODE_SET_FEAT	(1<<2)
175#define G_REQMODE_CLEAR_FEAT	(1<<1)
176#define G_REQMODE_GET_STATUS	(1<<0)
177
178	u32	ReqMode;
179	u8	_reserved9[0x18];
180	u32	PortStatus;		/* 0x380 */
181	u8	_reserved10[8];
182	u32	address;
183	u32	buff_test;
184	u8	_reserved11[4];
185	u32	UsbReady;
186	u8	_reserved12[4];
187	u32	SetDescStall;		/* 0x3a0 */
188	u8	_reserved13[0x45c];
189
190	/* hardware could handle limited GET_DESCRIPTOR duties */
191#define	DESC_LEN	0x80
192	u32	descriptors[DESC_LEN];	/* 0x800 */
193	u8	_reserved14[0x600];
194
195} __attribute__ ((packed));
196
197#define	MAX_FIFO_SIZE	64
198#define	MAX_EP0_SIZE	8		/* ep0 fifo is bigger, though */
199
200
201/*-------------------------------------------------------------------------*/
202
203/* DRIVER DATA STRUCTURES and UTILITIES */
204
205struct goku_ep {
206	struct usb_ep				ep;
207	struct goku_udc				*dev;
208	unsigned long				irqs;
209
210	unsigned				num:8,
211						dma:1,
212						is_in:1,
213						stopped:1;
214
215	/* analogous to a host-side qh */
216	struct list_head			queue;
217	const struct usb_endpoint_descriptor	*desc;
218
219	u32 __iomem				*reg_fifo;
220	u32 __iomem				*reg_mode;
221	u32 __iomem				*reg_status;
222};
223
224struct goku_request {
225	struct usb_request		req;
226	struct list_head		queue;
227
228	unsigned			mapped:1;
229};
230
231enum ep0state {
232	EP0_DISCONNECT,		/* no host */
233	EP0_IDLE,		/* between STATUS ack and SETUP report */
234	EP0_IN, EP0_OUT, 	/* data stage */
235	EP0_STATUS,		/* status stage */
236	EP0_STALL,		/* data or status stages */
237	EP0_SUSPEND,		/* usb suspend */
238};
239
240struct goku_udc {
241	/* each pci device provides one gadget, several endpoints */
242	struct usb_gadget		gadget;
243	spinlock_t			lock;
244	struct goku_ep			ep[4];
245	struct usb_gadget_driver 	*driver;
246
247	enum ep0state			ep0state;
248	unsigned			got_irq:1,
249					got_region:1,
250					req_config:1,
251					configured:1,
252					enabled:1;
253
254	/* pci state used to access those endpoints */
255	struct pci_dev			*pdev;
256	struct goku_udc_regs __iomem	*regs;
257	u32				int_enable;
258
259	/* statistics... */
260	unsigned long			irqs;
261};
262
263/*-------------------------------------------------------------------------*/
264
265#define xprintk(dev,level,fmt,args...) \
266	printk(level "%s %s: " fmt , driver_name , \
267			pci_name(dev->pdev) , ## args)
268
269#ifdef DEBUG
270#define DBG(dev,fmt,args...) \
271	xprintk(dev , KERN_DEBUG , fmt , ## args)
272#else
273#define DBG(dev,fmt,args...) \
274	do { } while (0)
275#endif /* DEBUG */
276
277#ifdef VERBOSE
278#define VDBG DBG
279#else
280#define VDBG(dev,fmt,args...) \
281	do { } while (0)
282#endif	/* VERBOSE */
283
284#define ERROR(dev,fmt,args...) \
285	xprintk(dev , KERN_ERR , fmt , ## args)
286#define WARN(dev,fmt,args...) \
287	xprintk(dev , KERN_WARNING , fmt , ## args)
288#define INFO(dev,fmt,args...) \
289	xprintk(dev , KERN_INFO , fmt , ## args)
290
291