net2280.h revision 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2
1/* 2 * NetChip 2280 high/full speed USB device controller. 3 * Unlike many such controllers, this one talks PCI. 4 */ 5 6/* 7 * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com) 8 * Copyright (C) 2003 David Brownell 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 */ 24 25/*-------------------------------------------------------------------------*/ 26 27/* NET2280 MEMORY MAPPED REGISTERS 28 * 29 * The register layout came from the chip documentation, and the bit 30 * number definitions were extracted from chip specification. 31 * 32 * Use the shift operator ('<<') to build bit masks, with readl/writel 33 * to access the registers through PCI. 34 */ 35 36/* main registers, BAR0 + 0x0000 */ 37struct net2280_regs { 38 // offset 0x0000 39 u32 devinit; 40#define LOCAL_CLOCK_FREQUENCY 8 41#define FORCE_PCI_RESET 7 42#define PCI_ID 6 43#define PCI_ENABLE 5 44#define FIFO_SOFT_RESET 4 45#define CFG_SOFT_RESET 3 46#define PCI_SOFT_RESET 2 47#define USB_SOFT_RESET 1 48#define M8051_RESET 0 49 u32 eectl; 50#define EEPROM_ADDRESS_WIDTH 23 51#define EEPROM_CHIP_SELECT_ACTIVE 22 52#define EEPROM_PRESENT 21 53#define EEPROM_VALID 20 54#define EEPROM_BUSY 19 55#define EEPROM_CHIP_SELECT_ENABLE 18 56#define EEPROM_BYTE_READ_START 17 57#define EEPROM_BYTE_WRITE_START 16 58#define EEPROM_READ_DATA 8 59#define EEPROM_WRITE_DATA 0 60 u32 eeclkfreq; 61 u32 _unused0; 62 // offset 0x0010 63 64 u32 pciirqenb0; /* interrupt PCI master ... */ 65#define SETUP_PACKET_INTERRUPT_ENABLE 7 66#define ENDPOINT_F_INTERRUPT_ENABLE 6 67#define ENDPOINT_E_INTERRUPT_ENABLE 5 68#define ENDPOINT_D_INTERRUPT_ENABLE 4 69#define ENDPOINT_C_INTERRUPT_ENABLE 3 70#define ENDPOINT_B_INTERRUPT_ENABLE 2 71#define ENDPOINT_A_INTERRUPT_ENABLE 1 72#define ENDPOINT_0_INTERRUPT_ENABLE 0 73 u32 pciirqenb1; 74#define PCI_INTERRUPT_ENABLE 31 75#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 76#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 77#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 78#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 79#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 80#define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18 81#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 82#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 83#define GPIO_INTERRUPT_ENABLE 13 84#define DMA_D_INTERRUPT_ENABLE 12 85#define DMA_C_INTERRUPT_ENABLE 11 86#define DMA_B_INTERRUPT_ENABLE 10 87#define DMA_A_INTERRUPT_ENABLE 9 88#define EEPROM_DONE_INTERRUPT_ENABLE 8 89#define VBUS_INTERRUPT_ENABLE 7 90#define CONTROL_STATUS_INTERRUPT_ENABLE 6 91#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 92#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 93#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 94#define RESUME_INTERRUPT_ENABLE 1 95#define SOF_INTERRUPT_ENABLE 0 96 u32 cpu_irqenb0; /* ... or onboard 8051 */ 97#define SETUP_PACKET_INTERRUPT_ENABLE 7 98#define ENDPOINT_F_INTERRUPT_ENABLE 6 99#define ENDPOINT_E_INTERRUPT_ENABLE 5 100#define ENDPOINT_D_INTERRUPT_ENABLE 4 101#define ENDPOINT_C_INTERRUPT_ENABLE 3 102#define ENDPOINT_B_INTERRUPT_ENABLE 2 103#define ENDPOINT_A_INTERRUPT_ENABLE 1 104#define ENDPOINT_0_INTERRUPT_ENABLE 0 105 u32 cpu_irqenb1; 106#define CPU_INTERRUPT_ENABLE 31 107#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 108#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 109#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 110#define PCI_INTA_INTERRUPT_ENABLE 24 111#define PCI_PME_INTERRUPT_ENABLE 23 112#define PCI_SERR_INTERRUPT_ENABLE 22 113#define PCI_PERR_INTERRUPT_ENABLE 21 114#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 115#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 116#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 117#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 118#define GPIO_INTERRUPT_ENABLE 13 119#define DMA_D_INTERRUPT_ENABLE 12 120#define DMA_C_INTERRUPT_ENABLE 11 121#define DMA_B_INTERRUPT_ENABLE 10 122#define DMA_A_INTERRUPT_ENABLE 9 123#define EEPROM_DONE_INTERRUPT_ENABLE 8 124#define VBUS_INTERRUPT_ENABLE 7 125#define CONTROL_STATUS_INTERRUPT_ENABLE 6 126#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 127#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 128#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 129#define RESUME_INTERRUPT_ENABLE 1 130#define SOF_INTERRUPT_ENABLE 0 131 132 // offset 0x0020 133 u32 _unused1; 134 u32 usbirqenb1; 135#define USB_INTERRUPT_ENABLE 31 136#define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27 137#define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26 138#define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25 139#define PCI_INTA_INTERRUPT_ENABLE 24 140#define PCI_PME_INTERRUPT_ENABLE 23 141#define PCI_SERR_INTERRUPT_ENABLE 22 142#define PCI_PERR_INTERRUPT_ENABLE 21 143#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20 144#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19 145#define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17 146#define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16 147#define GPIO_INTERRUPT_ENABLE 13 148#define DMA_D_INTERRUPT_ENABLE 12 149#define DMA_C_INTERRUPT_ENABLE 11 150#define DMA_B_INTERRUPT_ENABLE 10 151#define DMA_A_INTERRUPT_ENABLE 9 152#define EEPROM_DONE_INTERRUPT_ENABLE 8 153#define VBUS_INTERRUPT_ENABLE 7 154#define CONTROL_STATUS_INTERRUPT_ENABLE 6 155#define ROOT_PORT_RESET_INTERRUPT_ENABLE 4 156#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 157#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2 158#define RESUME_INTERRUPT_ENABLE 1 159#define SOF_INTERRUPT_ENABLE 0 160 u32 irqstat0; 161#define INTA_ASSERTED 12 162#define SETUP_PACKET_INTERRUPT 7 163#define ENDPOINT_F_INTERRUPT 6 164#define ENDPOINT_E_INTERRUPT 5 165#define ENDPOINT_D_INTERRUPT 4 166#define ENDPOINT_C_INTERRUPT 3 167#define ENDPOINT_B_INTERRUPT 2 168#define ENDPOINT_A_INTERRUPT 1 169#define ENDPOINT_0_INTERRUPT 0 170 u32 irqstat1; 171#define POWER_STATE_CHANGE_INTERRUPT 27 172#define PCI_ARBITER_TIMEOUT_INTERRUPT 26 173#define PCI_PARITY_ERROR_INTERRUPT 25 174#define PCI_INTA_INTERRUPT 24 175#define PCI_PME_INTERRUPT 23 176#define PCI_SERR_INTERRUPT 22 177#define PCI_PERR_INTERRUPT 21 178#define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20 179#define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19 180#define PCI_RETRY_ABORT_INTERRUPT 17 181#define PCI_MASTER_CYCLE_DONE_INTERRUPT 16 182#define GPIO_INTERRUPT 13 183#define DMA_D_INTERRUPT 12 184#define DMA_C_INTERRUPT 11 185#define DMA_B_INTERRUPT 10 186#define DMA_A_INTERRUPT 9 187#define EEPROM_DONE_INTERRUPT 8 188#define VBUS_INTERRUPT 7 189#define CONTROL_STATUS_INTERRUPT 6 190#define ROOT_PORT_RESET_INTERRUPT 4 191#define SUSPEND_REQUEST_INTERRUPT 3 192#define SUSPEND_REQUEST_CHANGE_INTERRUPT 2 193#define RESUME_INTERRUPT 1 194#define SOF_INTERRUPT 0 195 // offset 0x0030 196 u32 idxaddr; 197 u32 idxdata; 198 u32 fifoctl; 199#define PCI_BASE2_RANGE 16 200#define IGNORE_FIFO_AVAILABILITY 3 201#define PCI_BASE2_SELECT 2 202#define FIFO_CONFIGURATION_SELECT 0 203 u32 _unused2; 204 // offset 0x0040 205 u32 memaddr; 206#define START 28 207#define DIRECTION 27 208#define FIFO_DIAGNOSTIC_SELECT 24 209#define MEMORY_ADDRESS 0 210 u32 memdata0; 211 u32 memdata1; 212 u32 _unused3; 213 // offset 0x0050 214 u32 gpioctl; 215#define GPIO3_LED_SELECT 12 216#define GPIO3_INTERRUPT_ENABLE 11 217#define GPIO2_INTERRUPT_ENABLE 10 218#define GPIO1_INTERRUPT_ENABLE 9 219#define GPIO0_INTERRUPT_ENABLE 8 220#define GPIO3_OUTPUT_ENABLE 7 221#define GPIO2_OUTPUT_ENABLE 6 222#define GPIO1_OUTPUT_ENABLE 5 223#define GPIO0_OUTPUT_ENABLE 4 224#define GPIO3_DATA 3 225#define GPIO2_DATA 2 226#define GPIO1_DATA 1 227#define GPIO0_DATA 0 228 u32 gpiostat; 229#define GPIO3_INTERRUPT 3 230#define GPIO2_INTERRUPT 2 231#define GPIO1_INTERRUPT 1 232#define GPIO0_INTERRUPT 0 233} __attribute__ ((packed)); 234 235/* usb control, BAR0 + 0x0080 */ 236struct net2280_usb_regs { 237 // offset 0x0080 238 u32 stdrsp; 239#define STALL_UNSUPPORTED_REQUESTS 31 240#define SET_TEST_MODE 16 241#define GET_OTHER_SPEED_CONFIGURATION 15 242#define GET_DEVICE_QUALIFIER 14 243#define SET_ADDRESS 13 244#define ENDPOINT_SET_CLEAR_HALT 12 245#define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11 246#define GET_STRING_DESCRIPTOR_2 10 247#define GET_STRING_DESCRIPTOR_1 9 248#define GET_STRING_DESCRIPTOR_0 8 249#define GET_SET_INTERFACE 6 250#define GET_SET_CONFIGURATION 5 251#define GET_CONFIGURATION_DESCRIPTOR 4 252#define GET_DEVICE_DESCRIPTOR 3 253#define GET_ENDPOINT_STATUS 2 254#define GET_INTERFACE_STATUS 1 255#define GET_DEVICE_STATUS 0 256 u32 prodvendid; 257#define PRODUCT_ID 16 258#define VENDOR_ID 0 259 u32 relnum; 260 u32 usbctl; 261#define SERIAL_NUMBER_INDEX 16 262#define PRODUCT_ID_STRING_ENABLE 13 263#define VENDOR_ID_STRING_ENABLE 12 264#define USB_ROOT_PORT_WAKEUP_ENABLE 11 265#define VBUS_PIN 10 266#define TIMED_DISCONNECT 9 267#define SUSPEND_IMMEDIATELY 7 268#define SELF_POWERED_USB_DEVICE 6 269#define REMOTE_WAKEUP_SUPPORT 5 270#define PME_POLARITY 4 271#define USB_DETECT_ENABLE 3 272#define PME_WAKEUP_ENABLE 2 273#define DEVICE_REMOTE_WAKEUP_ENABLE 1 274#define SELF_POWERED_STATUS 0 275 // offset 0x0090 276 u32 usbstat; 277#define HIGH_SPEED 7 278#define FULL_SPEED 6 279#define GENERATE_RESUME 5 280#define GENERATE_DEVICE_REMOTE_WAKEUP 4 281 u32 xcvrdiag; 282#define FORCE_HIGH_SPEED_MODE 31 283#define FORCE_FULL_SPEED_MODE 30 284#define USB_TEST_MODE 24 285#define LINE_STATE 16 286#define TRANSCEIVER_OPERATION_MODE 2 287#define TRANSCEIVER_SELECT 1 288#define TERMINATION_SELECT 0 289 u32 setup0123; 290 u32 setup4567; 291 // offset 0x0090 292 u32 _unused0; 293 u32 ouraddr; 294#define FORCE_IMMEDIATE 7 295#define OUR_USB_ADDRESS 0 296 u32 ourconfig; 297} __attribute__ ((packed)); 298 299/* pci control, BAR0 + 0x0100 */ 300struct net2280_pci_regs { 301 // offset 0x0100 302 u32 pcimstctl; 303#define PCI_ARBITER_PARK_SELECT 13 304#define PCI_MULTI LEVEL_ARBITER 12 305#define PCI_RETRY_ABORT_ENABLE 11 306#define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10 307#define DMA_READ_MULTIPLE_ENABLE 9 308#define DMA_READ_LINE_ENABLE 8 309#define PCI_MASTER_COMMAND_SELECT 6 310#define MEM_READ_OR_WRITE 0 311#define IO_READ_OR_WRITE 1 312#define CFG_READ_OR_WRITE 2 313#define PCI_MASTER_START 5 314#define PCI_MASTER_READ_WRITE 4 315#define PCI_MASTER_WRITE 0 316#define PCI_MASTER_READ 1 317#define PCI_MASTER_BYTE_WRITE_ENABLES 0 318 u32 pcimstaddr; 319 u32 pcimstdata; 320 u32 pcimststat; 321#define PCI_ARBITER_CLEAR 2 322#define PCI_EXTERNAL_ARBITER 1 323#define PCI_HOST_MODE 0 324} __attribute__ ((packed)); 325 326/* dma control, BAR0 + 0x0180 ... array of four structs like this, 327 * for channels 0..3. see also struct net2280_dma: descriptor 328 * that can be loaded into some of these registers. 329 */ 330struct net2280_dma_regs { /* [11.7] */ 331 // offset 0x0180, 0x01a0, 0x01c0, 0x01e0, 332 u32 dmactl; 333#define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25 334#define DMA_CLEAR_COUNT_ENABLE 21 335#define DESCRIPTOR_POLLING_RATE 19 336#define POLL_CONTINUOUS 0 337#define POLL_1_USEC 1 338#define POLL_100_USEC 2 339#define POLL_1_MSEC 3 340#define DMA_VALID_BIT_POLLING_ENABLE 18 341#define DMA_VALID_BIT_ENABLE 17 342#define DMA_SCATTER_GATHER_ENABLE 16 343#define DMA_OUT_AUTO_START_ENABLE 4 344#define DMA_PREEMPT_ENABLE 3 345#define DMA_FIFO_VALIDATE 2 346#define DMA_ENABLE 1 347#define DMA_ADDRESS_HOLD 0 348 u32 dmastat; 349#define DMA_SCATTER_GATHER_DONE_INTERRUPT 25 350#define DMA_TRANSACTION_DONE_INTERRUPT 24 351#define DMA_ABORT 1 352#define DMA_START 0 353 u32 _unused0 [2]; 354 // offset 0x0190, 0x01b0, 0x01d0, 0x01f0, 355 u32 dmacount; 356#define VALID_BIT 31 357#define DMA_DIRECTION 30 358#define DMA_DONE_INTERRUPT_ENABLE 29 359#define END_OF_CHAIN 28 360#define DMA_BYTE_COUNT_MASK ((1<<24)-1) 361#define DMA_BYTE_COUNT 0 362 u32 dmaaddr; 363 u32 dmadesc; 364 u32 _unused1; 365} __attribute__ ((packed)); 366 367/* dedicated endpoint registers, BAR0 + 0x0200 */ 368 369struct net2280_dep_regs { /* [11.8] */ 370 // offset 0x0200, 0x0210, 0x220, 0x230, 0x240 371 u32 dep_cfg; 372 // offset 0x0204, 0x0214, 0x224, 0x234, 0x244 373 u32 dep_rsp; 374 u32 _unused [2]; 375} __attribute__ ((packed)); 376 377/* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs 378 * like this, for ep0 then the configurable endpoints A..F 379 * ep0 reserved for control; E and F have only 64 bytes of fifo 380 */ 381struct net2280_ep_regs { /* [11.9] */ 382 // offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 383 u32 ep_cfg; 384#define ENDPOINT_BYTE_COUNT 16 385#define ENDPOINT_ENABLE 10 386#define ENDPOINT_TYPE 8 387#define ENDPOINT_DIRECTION 7 388#define ENDPOINT_NUMBER 0 389 u32 ep_rsp; 390#define SET_NAK_OUT_PACKETS 15 391#define SET_EP_HIDE_STATUS_PHASE 14 392#define SET_EP_FORCE_CRC_ERROR 13 393#define SET_INTERRUPT_MODE 12 394#define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11 395#define SET_NAK_OUT_PACKETS_MODE 10 396#define SET_ENDPOINT_TOGGLE 9 397#define SET_ENDPOINT_HALT 8 398#define CLEAR_NAK_OUT_PACKETS 7 399#define CLEAR_EP_HIDE_STATUS_PHASE 6 400#define CLEAR_EP_FORCE_CRC_ERROR 5 401#define CLEAR_INTERRUPT_MODE 4 402#define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3 403#define CLEAR_NAK_OUT_PACKETS_MODE 2 404#define CLEAR_ENDPOINT_TOGGLE 1 405#define CLEAR_ENDPOINT_HALT 0 406 u32 ep_irqenb; 407#define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6 408#define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5 409#define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3 410#define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2 411#define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1 412#define DATA_IN_TOKEN_INTERRUPT_ENABLE 0 413 u32 ep_stat; 414#define FIFO_VALID_COUNT 24 415#define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22 416#define TIMEOUT 21 417#define USB_STALL_SENT 20 418#define USB_IN_NAK_SENT 19 419#define USB_IN_ACK_RCVD 18 420#define USB_OUT_PING_NAK_SENT 17 421#define USB_OUT_ACK_SENT 16 422#define FIFO_OVERFLOW 13 423#define FIFO_UNDERFLOW 12 424#define FIFO_FULL 11 425#define FIFO_EMPTY 10 426#define FIFO_FLUSH 9 427#define SHORT_PACKET_OUT_DONE_INTERRUPT 6 428#define SHORT_PACKET_TRANSFERRED_INTERRUPT 5 429#define NAK_OUT_PACKETS 4 430#define DATA_PACKET_RECEIVED_INTERRUPT 3 431#define DATA_PACKET_TRANSMITTED_INTERRUPT 2 432#define DATA_OUT_PING_TOKEN_INTERRUPT 1 433#define DATA_IN_TOKEN_INTERRUPT 0 434 // offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 435 u32 ep_avail; 436 u32 ep_data; 437 u32 _unused0 [2]; 438} __attribute__ ((packed)); 439 440/*-------------------------------------------------------------------------*/ 441 442#ifdef __KERNEL__ 443 444/* indexed registers [11.10] are accessed indirectly 445 * caller must own the device lock. 446 */ 447 448static inline u32 449get_idx_reg (struct net2280_regs __iomem *regs, u32 index) 450{ 451 writel (index, ®s->idxaddr); 452 /* NOTE: synchs device/cpu memory views */ 453 return readl (®s->idxdata); 454} 455 456static inline void 457set_idx_reg (struct net2280_regs __iomem *regs, u32 index, u32 value) 458{ 459 writel (index, ®s->idxaddr); 460 writel (value, ®s->idxdata); 461 /* posted, may not be visible yet */ 462} 463 464#endif /* __KERNEL__ */ 465 466 467#define REG_DIAG 0x0 468#define RETRY_COUNTER 16 469#define FORCE_PCI_SERR 11 470#define FORCE_PCI_INTERRUPT 10 471#define FORCE_USB_INTERRUPT 9 472#define FORCE_CPU_INTERRUPT 8 473#define ILLEGAL_BYTE_ENABLES 5 474#define FAST_TIMES 4 475#define FORCE_RECEIVE_ERROR 2 476#define FORCE_TRANSMIT_CRC_ERROR 0 477#define REG_FRAME 0x02 /* from last sof */ 478#define REG_CHIPREV 0x03 /* in bcd */ 479#define REG_HS_NAK_RATE 0x0a /* NAK per N uframes */ 480 481#define CHIPREV_1 0x0100 482#define CHIPREV_1A 0x0110 483 484#ifdef __KERNEL__ 485 486/* ep a-f highspeed and fullspeed maxpacket, addresses 487 * computed from ep->num 488 */ 489#define REG_EP_MAXPKT(dev,num) (((num) + 1) * 0x10 + \ 490 (((dev)->gadget.speed == USB_SPEED_HIGH) ? 0 : 1)) 491 492/*-------------------------------------------------------------------------*/ 493 494/* [8.3] for scatter/gather i/o 495 * use struct net2280_dma_regs bitfields 496 */ 497struct net2280_dma { 498 __le32 dmacount; 499 __le32 dmaaddr; /* the buffer */ 500 __le32 dmadesc; /* next dma descriptor */ 501 __le32 _reserved; 502} __attribute__ ((aligned (16))); 503 504/*-------------------------------------------------------------------------*/ 505 506/* DRIVER DATA STRUCTURES and UTILITIES */ 507 508struct net2280_ep { 509 struct usb_ep ep; 510 struct net2280_ep_regs __iomem *regs; 511 struct net2280_dma_regs __iomem *dma; 512 struct net2280_dma *dummy; 513 dma_addr_t td_dma; /* of dummy */ 514 struct net2280 *dev; 515 unsigned long irqs; 516 517 /* analogous to a host-side qh */ 518 struct list_head queue; 519 const struct usb_endpoint_descriptor *desc; 520 unsigned num : 8, 521 fifo_size : 12, 522 in_fifo_validate : 1, 523 out_overflow : 1, 524 stopped : 1, 525 is_in : 1, 526 is_iso : 1; 527}; 528 529static inline void allow_status (struct net2280_ep *ep) 530{ 531 /* ep0 only */ 532 writel ( (1 << CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) 533 | (1 << CLEAR_NAK_OUT_PACKETS) 534 | (1 << CLEAR_NAK_OUT_PACKETS_MODE) 535 , &ep->regs->ep_rsp); 536 ep->stopped = 1; 537} 538 539/* count (<= 4) bytes in the next fifo write will be valid */ 540static inline void set_fifo_bytecount (struct net2280_ep *ep, unsigned count) 541{ 542 writeb (count, 2 + (u8 __iomem *) &ep->regs->ep_cfg); 543} 544 545struct net2280_request { 546 struct usb_request req; 547 struct net2280_dma *td; 548 dma_addr_t td_dma; 549 struct list_head queue; 550 unsigned mapped : 1, 551 valid : 1; 552}; 553 554struct net2280 { 555 /* each pci device provides one gadget, several endpoints */ 556 struct usb_gadget gadget; 557 spinlock_t lock; 558 struct net2280_ep ep [7]; 559 struct usb_gadget_driver *driver; 560 unsigned enabled : 1, 561 protocol_stall : 1, 562 softconnect : 1, 563 got_irq : 1, 564 region : 1; 565 u16 chiprev; 566 567 /* pci state used to access those endpoints */ 568 struct pci_dev *pdev; 569 struct net2280_regs __iomem *regs; 570 struct net2280_usb_regs __iomem *usb; 571 struct net2280_pci_regs __iomem *pci; 572 struct net2280_dma_regs __iomem *dma; 573 struct net2280_dep_regs __iomem *dep; 574 struct net2280_ep_regs __iomem *epregs; 575 576 struct pci_pool *requests; 577 // statistics... 578}; 579 580static inline void set_halt (struct net2280_ep *ep) 581{ 582 /* ep0 and bulk/intr endpoints */ 583 writel ( (1 << CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) 584 /* set NAK_OUT for erratum 0114 */ 585 | ((ep->dev->chiprev == CHIPREV_1) << SET_NAK_OUT_PACKETS) 586 | (1 << SET_ENDPOINT_HALT) 587 , &ep->regs->ep_rsp); 588} 589 590static inline void clear_halt (struct net2280_ep *ep) 591{ 592 /* ep0 and bulk/intr endpoints */ 593 writel ( (1 << CLEAR_ENDPOINT_HALT) 594 | (1 << CLEAR_ENDPOINT_TOGGLE) 595 /* unless the gadget driver left a short packet in the 596 * fifo, this reverses the erratum 0114 workaround. 597 */ 598 | ((ep->dev->chiprev == CHIPREV_1) << CLEAR_NAK_OUT_PACKETS) 599 , &ep->regs->ep_rsp); 600} 601 602#ifdef USE_RDK_LEDS 603 604static inline void net2280_led_init (struct net2280 *dev) 605{ 606 /* LED3 (green) is on during USB activity. note erratum 0113. */ 607 writel ((1 << GPIO3_LED_SELECT) 608 | (1 << GPIO3_OUTPUT_ENABLE) 609 | (1 << GPIO2_OUTPUT_ENABLE) 610 | (1 << GPIO1_OUTPUT_ENABLE) 611 | (1 << GPIO0_OUTPUT_ENABLE) 612 , &dev->regs->gpioctl); 613} 614 615/* indicate speed with bi-color LED 0/1 */ 616static inline 617void net2280_led_speed (struct net2280 *dev, enum usb_device_speed speed) 618{ 619 u32 val = readl (&dev->regs->gpioctl); 620 switch (speed) { 621 case USB_SPEED_HIGH: /* green */ 622 val &= ~(1 << GPIO0_DATA); 623 val |= (1 << GPIO1_DATA); 624 break; 625 case USB_SPEED_FULL: /* red */ 626 val &= ~(1 << GPIO1_DATA); 627 val |= (1 << GPIO0_DATA); 628 break; 629 default: /* (off/black) */ 630 val &= ~((1 << GPIO1_DATA) | (1 << GPIO0_DATA)); 631 break; 632 } 633 writel (val, &dev->regs->gpioctl); 634} 635 636/* indicate power with LED 2 */ 637static inline void net2280_led_active (struct net2280 *dev, int is_active) 638{ 639 u32 val = readl (&dev->regs->gpioctl); 640 641 // FIXME this LED never seems to turn on. 642 if (is_active) 643 val |= GPIO2_DATA; 644 else 645 val &= ~GPIO2_DATA; 646 writel (val, &dev->regs->gpioctl); 647} 648static inline void net2280_led_shutdown (struct net2280 *dev) 649{ 650 /* turn off all four GPIO*_DATA bits */ 651 writel (readl (&dev->regs->gpioctl) & ~0x0f, 652 &dev->regs->gpioctl); 653} 654 655#else 656 657#define net2280_led_init(dev) do { } while (0) 658#define net2280_led_speed(dev, speed) do { } while (0) 659#define net2280_led_shutdown(dev) do { } while (0) 660 661#endif 662 663/*-------------------------------------------------------------------------*/ 664 665#define xprintk(dev,level,fmt,args...) \ 666 printk(level "%s %s: " fmt , driver_name , \ 667 pci_name(dev->pdev) , ## args) 668 669#ifdef DEBUG 670#undef DEBUG 671#define DEBUG(dev,fmt,args...) \ 672 xprintk(dev , KERN_DEBUG , fmt , ## args) 673#else 674#define DEBUG(dev,fmt,args...) \ 675 do { } while (0) 676#endif /* DEBUG */ 677 678#ifdef VERBOSE 679#define VDEBUG DEBUG 680#else 681#define VDEBUG(dev,fmt,args...) \ 682 do { } while (0) 683#endif /* VERBOSE */ 684 685#define ERROR(dev,fmt,args...) \ 686 xprintk(dev , KERN_ERR , fmt , ## args) 687#define WARN(dev,fmt,args...) \ 688 xprintk(dev , KERN_WARNING , fmt , ## args) 689#define INFO(dev,fmt,args...) \ 690 xprintk(dev , KERN_INFO , fmt , ## args) 691 692/*-------------------------------------------------------------------------*/ 693 694static inline void start_out_naking (struct net2280_ep *ep) 695{ 696 /* NOTE: hardware races lurk here, and PING protocol issues */ 697 writel ((1 << SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); 698 /* synch with device */ 699 readl (&ep->regs->ep_rsp); 700} 701 702#ifdef DEBUG 703static inline void assert_out_naking (struct net2280_ep *ep, const char *where) 704{ 705 u32 tmp = readl (&ep->regs->ep_stat); 706 707 if ((tmp & (1 << NAK_OUT_PACKETS)) == 0) { 708 DEBUG (ep->dev, "%s %s %08x !NAK\n", 709 ep->ep.name, where, tmp); 710 writel ((1 << SET_NAK_OUT_PACKETS), 711 &ep->regs->ep_rsp); 712 } 713} 714#define ASSERT_OUT_NAKING(ep) assert_out_naking(ep,__FUNCTION__) 715#else 716#define ASSERT_OUT_NAKING(ep) do {} while (0) 717#endif 718 719static inline void stop_out_naking (struct net2280_ep *ep) 720{ 721 u32 tmp; 722 723 tmp = readl (&ep->regs->ep_stat); 724 if ((tmp & (1 << NAK_OUT_PACKETS)) != 0) 725 writel ((1 << CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp); 726} 727 728#endif /* __KERNEL__ */ 729