ehci-hcd.c revision 10f6524a8ef1413a8cbd952673997013183fe2a9
1/* 2 * Copyright (c) 2000-2004 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#include <linux/config.h> 20 21#ifdef CONFIG_USB_DEBUG 22 #define DEBUG 23#else 24 #undef DEBUG 25#endif 26 27#include <linux/module.h> 28#include <linux/pci.h> 29#include <linux/dmapool.h> 30#include <linux/kernel.h> 31#include <linux/delay.h> 32#include <linux/ioport.h> 33#include <linux/sched.h> 34#include <linux/slab.h> 35#include <linux/smp_lock.h> 36#include <linux/errno.h> 37#include <linux/init.h> 38#include <linux/timer.h> 39#include <linux/list.h> 40#include <linux/interrupt.h> 41#include <linux/reboot.h> 42#include <linux/usb.h> 43#include <linux/moduleparam.h> 44#include <linux/dma-mapping.h> 45 46#include "../core/hcd.h" 47 48#include <asm/byteorder.h> 49#include <asm/io.h> 50#include <asm/irq.h> 51#include <asm/system.h> 52#include <asm/unaligned.h> 53 54 55/*-------------------------------------------------------------------------*/ 56 57/* 58 * EHCI hc_driver implementation ... experimental, incomplete. 59 * Based on the final 1.0 register interface specification. 60 * 61 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 62 * First was PCMCIA, like ISA; then CardBus, which is PCI. 63 * Next comes "CardBay", using USB 2.0 signals. 64 * 65 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 66 * Special thanks to Intel and VIA for providing host controllers to 67 * test this driver on, and Cypress (including In-System Design) for 68 * providing early devices for those host controllers to talk to! 69 * 70 * HISTORY: 71 * 72 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db) 73 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net) 74 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka, 75 * <sojkam@centrum.cz>, updates by DB). 76 * 77 * 2002-11-29 Correct handling for hw async_next register. 78 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared; 79 * only scheduling is different, no arbitrary limitations. 80 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support, 81 * clean up HC run state handshaking. 82 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts 83 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other 84 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM. 85 * 2002-05-07 Some error path cleanups to report better errors; wmb(); 86 * use non-CVS version id; better iso bandwidth claim. 87 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on 88 * errors in submit path. Bugfixes to interrupt scheduling/processing. 89 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift 90 * more checking to generic hcd framework (db). Make it work with 91 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt). 92 * 2002-01-14 Minor cleanup; version synch. 93 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers. 94 * 2002-01-04 Control/Bulk queuing behaves. 95 * 96 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel. 97 * 2001-June Works with usb-storage and NEC EHCI on 2.4 98 */ 99 100#define DRIVER_VERSION "10 Dec 2004" 101#define DRIVER_AUTHOR "David Brownell" 102#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 103 104static const char hcd_name [] = "ehci_hcd"; 105 106 107#undef EHCI_VERBOSE_DEBUG 108#undef EHCI_URB_TRACE 109 110#ifdef DEBUG 111#define EHCI_STATS 112#endif 113 114/* magic numbers that can affect system performance */ 115#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 116#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 117#define EHCI_TUNE_RL_TT 0 118#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 119#define EHCI_TUNE_MULT_TT 1 120#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 121 122#define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */ 123#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 124#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 125#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ 126 127/* Initial IRQ latency: faster than hw default */ 128static int log2_irq_thresh = 0; // 0 to 6 129module_param (log2_irq_thresh, int, S_IRUGO); 130MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 131 132/* initial park setting: slower than hw default */ 133static unsigned park = 0; 134module_param (park, uint, S_IRUGO); 135MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 136 137#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 138 139/*-------------------------------------------------------------------------*/ 140 141#include "ehci.h" 142#include "ehci-dbg.c" 143 144/*-------------------------------------------------------------------------*/ 145 146/* 147 * handshake - spin reading hc until handshake completes or fails 148 * @ptr: address of hc register to be read 149 * @mask: bits to look at in result of read 150 * @done: value of those bits when handshake succeeds 151 * @usec: timeout in microseconds 152 * 153 * Returns negative errno, or zero on success 154 * 155 * Success happens when the "mask" bits have the specified value (hardware 156 * handshake done). There are two failure modes: "usec" have passed (major 157 * hardware flakeout), or the register reads as all-ones (hardware removed). 158 * 159 * That last failure should_only happen in cases like physical cardbus eject 160 * before driver shutdown. But it also seems to be caused by bugs in cardbus 161 * bridge shutdown: shutting down the bridge before the devices using it. 162 */ 163static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec) 164{ 165 u32 result; 166 167 do { 168 result = readl (ptr); 169 if (result == ~(u32)0) /* card removed */ 170 return -ENODEV; 171 result &= mask; 172 if (result == done) 173 return 0; 174 udelay (1); 175 usec--; 176 } while (usec > 0); 177 return -ETIMEDOUT; 178} 179 180/* force HC to halt state from unknown (EHCI spec section 2.3) */ 181static int ehci_halt (struct ehci_hcd *ehci) 182{ 183 u32 temp = readl (&ehci->regs->status); 184 185 if ((temp & STS_HALT) != 0) 186 return 0; 187 188 temp = readl (&ehci->regs->command); 189 temp &= ~CMD_RUN; 190 writel (temp, &ehci->regs->command); 191 return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125); 192} 193 194/* put TDI/ARC silicon into EHCI mode */ 195static void tdi_reset (struct ehci_hcd *ehci) 196{ 197 u32 __iomem *reg_ptr; 198 u32 tmp; 199 200 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68); 201 tmp = readl (reg_ptr); 202 tmp |= 0x3; 203 writel (tmp, reg_ptr); 204} 205 206/* reset a non-running (STS_HALT == 1) controller */ 207static int ehci_reset (struct ehci_hcd *ehci) 208{ 209 int retval; 210 u32 command = readl (&ehci->regs->command); 211 212 command |= CMD_RESET; 213 dbg_cmd (ehci, "reset", command); 214 writel (command, &ehci->regs->command); 215 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 216 ehci->next_statechange = jiffies; 217 retval = handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000); 218 219 if (retval) 220 return retval; 221 222 if (ehci_is_TDI(ehci)) 223 tdi_reset (ehci); 224 225 return retval; 226} 227 228/* idle the controller (from running) */ 229static void ehci_quiesce (struct ehci_hcd *ehci) 230{ 231 u32 temp; 232 233#ifdef DEBUG 234 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) 235 BUG (); 236#endif 237 238 /* wait for any schedule enables/disables to take effect */ 239 temp = readl (&ehci->regs->command) << 10; 240 temp &= STS_ASS | STS_PSS; 241 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS, 242 temp, 16 * 125) != 0) { 243 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 244 return; 245 } 246 247 /* then disable anything that's still active */ 248 temp = readl (&ehci->regs->command); 249 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 250 writel (temp, &ehci->regs->command); 251 252 /* hardware can take 16 microframes to turn off ... */ 253 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS, 254 0, 16 * 125) != 0) { 255 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 256 return; 257 } 258} 259 260/*-------------------------------------------------------------------------*/ 261 262static void ehci_work(struct ehci_hcd *ehci, struct pt_regs *regs); 263 264#include "ehci-hub.c" 265#include "ehci-mem.c" 266#include "ehci-q.c" 267#include "ehci-sched.c" 268 269/*-------------------------------------------------------------------------*/ 270 271static void ehci_watchdog (unsigned long param) 272{ 273 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 274 unsigned long flags; 275 276 spin_lock_irqsave (&ehci->lock, flags); 277 278 /* lost IAA irqs wedge things badly; seen with a vt8235 */ 279 if (ehci->reclaim) { 280 u32 status = readl (&ehci->regs->status); 281 282 if (status & STS_IAA) { 283 ehci_vdbg (ehci, "lost IAA\n"); 284 COUNT (ehci->stats.lost_iaa); 285 writel (STS_IAA, &ehci->regs->status); 286 ehci->reclaim_ready = 1; 287 } 288 } 289 290 /* stop async processing after it's idled a bit */ 291 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 292 start_unlink_async (ehci, ehci->async); 293 294 /* ehci could run by timer, without IRQs ... */ 295 ehci_work (ehci, NULL); 296 297 spin_unlock_irqrestore (&ehci->lock, flags); 298} 299 300#ifdef CONFIG_PCI 301 302/* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/... 303 * off the controller (maybe it can boot from highspeed USB disks). 304 */ 305static int bios_handoff (struct ehci_hcd *ehci, int where, u32 cap) 306{ 307 struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller); 308 309 /* always say Linux will own the hardware */ 310 pci_write_config_byte(pdev, where + 3, 1); 311 312 /* maybe wait a while for BIOS to respond */ 313 if (cap & (1 << 16)) { 314 int msec = 5000; 315 316 do { 317 msleep(10); 318 msec -= 10; 319 pci_read_config_dword(pdev, where, &cap); 320 } while ((cap & (1 << 16)) && msec); 321 if (cap & (1 << 16)) { 322 ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n", 323 where, cap); 324 // some BIOS versions seem buggy... 325 // return 1; 326 ehci_warn (ehci, "continuing after BIOS bug...\n"); 327 /* disable all SMIs, and clear "BIOS owns" flag */ 328 pci_write_config_dword(pdev, where + 4, 0); 329 pci_write_config_byte(pdev, where + 2, 0); 330 } else 331 ehci_dbg(ehci, "BIOS handoff succeeded\n"); 332 } 333 return 0; 334} 335 336#endif 337 338static int 339ehci_reboot (struct notifier_block *self, unsigned long code, void *null) 340{ 341 struct ehci_hcd *ehci; 342 343 ehci = container_of (self, struct ehci_hcd, reboot_notifier); 344 345 /* make BIOS/etc use companion controller during reboot */ 346 writel (0, &ehci->regs->configured_flag); 347 return 0; 348} 349 350static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 351{ 352 unsigned port; 353 354 if (!HCS_PPC (ehci->hcs_params)) 355 return; 356 357 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 358 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 359 (void) ehci_hub_control(ehci_to_hcd(ehci), 360 is_on ? SetPortFeature : ClearPortFeature, 361 USB_PORT_FEAT_POWER, 362 port--, NULL, 0); 363 msleep(20); 364} 365 366 367/* called by khubd or root hub init threads */ 368 369static int ehci_hc_reset (struct usb_hcd *hcd) 370{ 371 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 372 u32 temp; 373 unsigned count = 256/4; 374 375 spin_lock_init (&ehci->lock); 376 377 ehci->caps = hcd->regs; 378 ehci->regs = hcd->regs + HC_LENGTH (readl (&ehci->caps->hc_capbase)); 379 dbg_hcs_params (ehci, "reset"); 380 dbg_hcc_params (ehci, "reset"); 381 382 /* cache this readonly data; minimize chip reads */ 383 ehci->hcs_params = readl (&ehci->caps->hcs_params); 384 385#ifdef CONFIG_PCI 386 if (hcd->self.controller->bus == &pci_bus_type) { 387 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 388 389 switch (pdev->vendor) { 390 case PCI_VENDOR_ID_TDI: 391 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 392 ehci->is_tdi_rh_tt = 1; 393 tdi_reset (ehci); 394 } 395 break; 396 case PCI_VENDOR_ID_AMD: 397 /* AMD8111 EHCI doesn't work, according to AMD errata */ 398 if (pdev->device == 0x7463) { 399 ehci_info (ehci, "ignoring AMD8111 (errata)\n"); 400 return -EIO; 401 } 402 break; 403 } 404 405 /* optional debug port, normally in the first BAR */ 406 temp = pci_find_capability (pdev, 0x0a); 407 if (temp) { 408 pci_read_config_dword(pdev, temp, &temp); 409 temp >>= 16; 410 if ((temp & (3 << 13)) == (1 << 13)) { 411 temp &= 0x1fff; 412 ehci->debug = hcd->regs + temp; 413 temp = readl (&ehci->debug->control); 414 ehci_info (ehci, "debug port %d%s\n", 415 HCS_DEBUG_PORT(ehci->hcs_params), 416 (temp & DBGP_ENABLED) 417 ? " IN USE" 418 : ""); 419 if (!(temp & DBGP_ENABLED)) 420 ehci->debug = NULL; 421 } 422 } 423 424 temp = HCC_EXT_CAPS (readl (&ehci->caps->hcc_params)); 425 } else 426 temp = 0; 427 428 /* EHCI 0.96 and later may have "extended capabilities" */ 429 while (temp && count--) { 430 u32 cap; 431 432 pci_read_config_dword (to_pci_dev(hcd->self.controller), 433 temp, &cap); 434 ehci_dbg (ehci, "capability %04x at %02x\n", cap, temp); 435 switch (cap & 0xff) { 436 case 1: /* BIOS/SMM/... handoff */ 437 if (bios_handoff (ehci, temp, cap) != 0) 438 return -EOPNOTSUPP; 439 break; 440 case 0: /* illegal reserved capability */ 441 ehci_warn (ehci, "illegal capability!\n"); 442 cap = 0; 443 /* FALLTHROUGH */ 444 default: /* unknown */ 445 break; 446 } 447 temp = (cap >> 8) & 0xff; 448 } 449 if (!count) { 450 ehci_err (ehci, "bogus capabilities ... PCI problems!\n"); 451 return -EIO; 452 } 453 if (ehci_is_TDI(ehci)) 454 ehci_reset (ehci); 455#endif 456 457 ehci_port_power (ehci, 0); 458 459 /* at least the Genesys GL880S needs fixup here */ 460 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 461 temp &= 0x0f; 462 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 463 ehci_dbg (ehci, "bogus port configuration: " 464 "cc=%d x pcc=%d < ports=%d\n", 465 HCS_N_CC(ehci->hcs_params), 466 HCS_N_PCC(ehci->hcs_params), 467 HCS_N_PORTS(ehci->hcs_params)); 468 469#ifdef CONFIG_PCI 470 if (hcd->self.controller->bus == &pci_bus_type) { 471 struct pci_dev *pdev; 472 473 pdev = to_pci_dev(hcd->self.controller); 474 switch (pdev->vendor) { 475 case 0x17a0: /* GENESYS */ 476 /* GL880S: should be PORTS=2 */ 477 temp |= (ehci->hcs_params & ~0xf); 478 ehci->hcs_params = temp; 479 break; 480 case PCI_VENDOR_ID_NVIDIA: 481 /* NF4: should be PCC=10 */ 482 break; 483 } 484 } 485#endif 486 } 487 488 /* force HC to halt state */ 489 return ehci_halt (ehci); 490} 491 492static int ehci_start (struct usb_hcd *hcd) 493{ 494 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 495 u32 temp; 496 int retval; 497 u32 hcc_params; 498 u8 sbrn = 0; 499 int first; 500 501 /* skip some things on restart paths */ 502 first = (ehci->watchdog.data == 0); 503 if (first) { 504 init_timer (&ehci->watchdog); 505 ehci->watchdog.function = ehci_watchdog; 506 ehci->watchdog.data = (unsigned long) ehci; 507 } 508 509 /* 510 * hw default: 1K periodic list heads, one per frame. 511 * periodic_size can shrink by USBCMD update if hcc_params allows. 512 */ 513 ehci->periodic_size = DEFAULT_I_TDPS; 514 if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0) 515 return retval; 516 517 /* controllers may cache some of the periodic schedule ... */ 518 hcc_params = readl (&ehci->caps->hcc_params); 519 if (HCC_ISOC_CACHE (hcc_params)) // full frame cache 520 ehci->i_thresh = 8; 521 else // N microframes cached 522 ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params); 523 524 ehci->reclaim = NULL; 525 ehci->reclaim_ready = 0; 526 ehci->next_uframe = -1; 527 528 /* controller state: unknown --> reset */ 529 530 /* EHCI spec section 4.1 */ 531 if ((retval = ehci_reset (ehci)) != 0) { 532 ehci_mem_cleanup (ehci); 533 return retval; 534 } 535 writel (ehci->periodic_dma, &ehci->regs->frame_list); 536 537#ifdef CONFIG_PCI 538 if (hcd->self.controller->bus == &pci_bus_type) { 539 struct pci_dev *pdev; 540 u16 port_wake; 541 542 pdev = to_pci_dev(hcd->self.controller); 543 544 /* Serial Bus Release Number is at PCI 0x60 offset */ 545 pci_read_config_byte(pdev, 0x60, &sbrn); 546 547 /* port wake capability, reported by boot firmware */ 548 pci_read_config_word(pdev, 0x62, &port_wake); 549 hcd->can_wakeup = (port_wake & 1) != 0; 550 551 /* help hc dma work well with cachelines */ 552 retval = pci_set_mwi(pdev); 553 if (retval) 554 ehci_dbg(ehci, "unable to enable MWI - not fatal.\n"); 555 } 556#endif 557 558 /* 559 * dedicate a qh for the async ring head, since we couldn't unlink 560 * a 'real' qh without stopping the async schedule [4.8]. use it 561 * as the 'reclamation list head' too. 562 * its dummy is used in hw_alt_next of many tds, to prevent the qh 563 * from automatically advancing to the next td after short reads. 564 */ 565 if (first) { 566 ehci->async->qh_next.qh = NULL; 567 ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma); 568 ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD); 569 ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT); 570 ehci->async->hw_qtd_next = EHCI_LIST_END; 571 ehci->async->qh_state = QH_STATE_LINKED; 572 ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma); 573 } 574 writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next); 575 576 /* 577 * hcc_params controls whether ehci->regs->segment must (!!!) 578 * be used; it constrains QH/ITD/SITD and QTD locations. 579 * pci_pool consistent memory always uses segment zero. 580 * streaming mappings for I/O buffers, like pci_map_single(), 581 * can return segments above 4GB, if the device allows. 582 * 583 * NOTE: the dma mask is visible through dma_supported(), so 584 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 585 * Scsi_Host.highmem_io, and so forth. It's readonly to all 586 * host side drivers though. 587 */ 588 if (HCC_64BIT_ADDR (hcc_params)) { 589 writel (0, &ehci->regs->segment); 590#if 0 591// this is deeply broken on almost all architectures 592 if (!dma_set_mask (hcd->self.controller, DMA_64BIT_MASK)) 593 ehci_info (ehci, "enabled 64bit DMA\n"); 594#endif 595 } 596 597 /* clear interrupt enables, set irq latency */ 598 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 599 log2_irq_thresh = 0; 600 temp = 1 << (16 + log2_irq_thresh); 601 if (HCC_CANPARK(hcc_params)) { 602 /* HW default park == 3, on hardware that supports it (like 603 * NVidia and ALI silicon), maximizes throughput on the async 604 * schedule by avoiding QH fetches between transfers. 605 * 606 * With fast usb storage devices and NForce2, "park" seems to 607 * make problems: throughput reduction (!), data errors... 608 */ 609 if (park) { 610 park = min (park, (unsigned) 3); 611 temp |= CMD_PARK; 612 temp |= park << 8; 613 } 614 ehci_info (ehci, "park %d\n", park); 615 } 616 if (HCC_PGM_FRAMELISTLEN (hcc_params)) { 617 /* periodic schedule size can be smaller than default */ 618 temp &= ~(3 << 2); 619 temp |= (EHCI_TUNE_FLS << 2); 620 switch (EHCI_TUNE_FLS) { 621 case 0: ehci->periodic_size = 1024; break; 622 case 1: ehci->periodic_size = 512; break; 623 case 2: ehci->periodic_size = 256; break; 624 default: BUG (); 625 } 626 } 627 // Philips, Intel, and maybe others need CMD_RUN before the 628 // root hub will detect new devices (why?); NEC doesn't 629 temp |= CMD_RUN; 630 writel (temp, &ehci->regs->command); 631 dbg_cmd (ehci, "init", temp); 632 633 /* set async sleep time = 10 us ... ? */ 634 635 /* 636 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 637 * are explicitly handed to companion controller(s), so no TT is 638 * involved with the root hub. (Except where one is integrated, 639 * and there's no companion controller unless maybe for USB OTG.) 640 */ 641 if (first) { 642 ehci->reboot_notifier.notifier_call = ehci_reboot; 643 register_reboot_notifier (&ehci->reboot_notifier); 644 } 645 646 hcd->state = HC_STATE_RUNNING; 647 writel (FLAG_CF, &ehci->regs->configured_flag); 648 readl (&ehci->regs->command); /* unblock posted write */ 649 650 temp = HC_VERSION(readl (&ehci->caps->hc_capbase)); 651 ehci_info (ehci, 652 "USB %x.%x %s, EHCI %x.%02x, driver %s\n", 653 ((sbrn & 0xf0)>>4), (sbrn & 0x0f), 654 first ? "initialized" : "restarted", 655 temp >> 8, temp & 0xff, DRIVER_VERSION); 656 657 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */ 658 659 if (first) 660 create_debug_files (ehci); 661 662 return 0; 663} 664 665/* always called by thread; normally rmmod */ 666 667static void ehci_stop (struct usb_hcd *hcd) 668{ 669 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 670 671 ehci_dbg (ehci, "stop\n"); 672 673 /* Turn off port power on all root hub ports. */ 674 ehci_port_power (ehci, 0); 675 676 /* no more interrupts ... */ 677 del_timer_sync (&ehci->watchdog); 678 679 spin_lock_irq(&ehci->lock); 680 if (HC_IS_RUNNING (hcd->state)) 681 ehci_quiesce (ehci); 682 683 ehci_reset (ehci); 684 writel (0, &ehci->regs->intr_enable); 685 spin_unlock_irq(&ehci->lock); 686 687 /* let companion controllers work when we aren't */ 688 writel (0, &ehci->regs->configured_flag); 689 unregister_reboot_notifier (&ehci->reboot_notifier); 690 691 remove_debug_files (ehci); 692 693 /* root hub is shut down separately (first, when possible) */ 694 spin_lock_irq (&ehci->lock); 695 if (ehci->async) 696 ehci_work (ehci, NULL); 697 spin_unlock_irq (&ehci->lock); 698 ehci_mem_cleanup (ehci); 699 700#ifdef EHCI_STATS 701 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 702 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 703 ehci->stats.lost_iaa); 704 ehci_dbg (ehci, "complete %ld unlink %ld\n", 705 ehci->stats.complete, ehci->stats.unlink); 706#endif 707 708 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status)); 709} 710 711static int ehci_get_frame (struct usb_hcd *hcd) 712{ 713 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 714 return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size; 715} 716 717/*-------------------------------------------------------------------------*/ 718 719#ifdef CONFIG_PM 720 721/* suspend/resume, section 4.3 */ 722 723/* These routines rely on the bus (pci, platform, etc) 724 * to handle powerdown and wakeup, and currently also on 725 * transceivers that don't need any software attention to set up 726 * the right sort of wakeup. 727 */ 728 729static int ehci_suspend (struct usb_hcd *hcd, pm_message_t message) 730{ 731 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 732 733 if (time_before (jiffies, ehci->next_statechange)) 734 msleep (100); 735 736#ifdef CONFIG_USB_SUSPEND 737 (void) usb_suspend_device (hcd->self.root_hub, message); 738#else 739 usb_lock_device (hcd->self.root_hub); 740 (void) ehci_hub_suspend (hcd); 741 usb_unlock_device (hcd->self.root_hub); 742#endif 743 744 // save (PCI) FLADJ in case of Vaux power loss 745 // ... we'd only use it to handle clock skew 746 747 return 0; 748} 749 750static int ehci_resume (struct usb_hcd *hcd) 751{ 752 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 753 unsigned port; 754 struct usb_device *root = hcd->self.root_hub; 755 int retval = -EINVAL; 756 757 // maybe restore (PCI) FLADJ 758 759 if (time_before (jiffies, ehci->next_statechange)) 760 msleep (100); 761 762 /* If any port is suspended (or owned by the companion), 763 * we know we can/must resume the HC (and mustn't reset it). 764 */ 765 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) { 766 u32 status; 767 port--; 768 status = readl (&ehci->regs->port_status [port]); 769 if (!(status & PORT_POWER)) 770 continue; 771 if (status & (PORT_SUSPEND | PORT_OWNER)) { 772 down (&hcd->self.root_hub->serialize); 773 retval = ehci_hub_resume (hcd); 774 up (&hcd->self.root_hub->serialize); 775 break; 776 } 777 if (!root->children [port]) 778 continue; 779 dbg_port (ehci, __FUNCTION__, port + 1, status); 780 usb_set_device_state (root->children[port], 781 USB_STATE_NOTATTACHED); 782 } 783 784 /* Else reset, to cope with power loss or flush-to-storage 785 * style "resume" having activated BIOS during reboot. 786 */ 787 if (port == 0) { 788 (void) ehci_halt (ehci); 789 (void) ehci_reset (ehci); 790 (void) ehci_hc_reset (hcd); 791 792 /* emptying the schedule aborts any urbs */ 793 spin_lock_irq (&ehci->lock); 794 if (ehci->reclaim) 795 ehci->reclaim_ready = 1; 796 ehci_work (ehci, NULL); 797 spin_unlock_irq (&ehci->lock); 798 799 /* restart; khubd will disconnect devices */ 800 retval = ehci_start (hcd); 801 802 /* here we "know" root ports should always stay powered; 803 * but some controllers may lose all power. 804 */ 805 ehci_port_power (ehci, 1); 806 } 807 808 return retval; 809} 810 811#endif 812 813/*-------------------------------------------------------------------------*/ 814 815/* 816 * ehci_work is called from some interrupts, timers, and so on. 817 * it calls driver completion functions, after dropping ehci->lock. 818 */ 819static void ehci_work (struct ehci_hcd *ehci, struct pt_regs *regs) 820{ 821 timer_action_done (ehci, TIMER_IO_WATCHDOG); 822 if (ehci->reclaim_ready) 823 end_unlink_async (ehci, regs); 824 825 /* another CPU may drop ehci->lock during a schedule scan while 826 * it reports urb completions. this flag guards against bogus 827 * attempts at re-entrant schedule scanning. 828 */ 829 if (ehci->scanning) 830 return; 831 ehci->scanning = 1; 832 scan_async (ehci, regs); 833 if (ehci->next_uframe != -1) 834 scan_periodic (ehci, regs); 835 ehci->scanning = 0; 836 837 /* the IO watchdog guards against hardware or driver bugs that 838 * misplace IRQs, and should let us run completely without IRQs. 839 * such lossage has been observed on both VT6202 and VT8235. 840 */ 841 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && 842 (ehci->async->qh_next.ptr != NULL || 843 ehci->periodic_sched != 0)) 844 timer_action (ehci, TIMER_IO_WATCHDOG); 845} 846 847/*-------------------------------------------------------------------------*/ 848 849static irqreturn_t ehci_irq (struct usb_hcd *hcd, struct pt_regs *regs) 850{ 851 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 852 u32 status; 853 int bh; 854 855 spin_lock (&ehci->lock); 856 857 status = readl (&ehci->regs->status); 858 859 /* e.g. cardbus physical eject */ 860 if (status == ~(u32) 0) { 861 ehci_dbg (ehci, "device removed\n"); 862 goto dead; 863 } 864 865 status &= INTR_MASK; 866 if (!status) { /* irq sharing? */ 867 spin_unlock(&ehci->lock); 868 return IRQ_NONE; 869 } 870 871 /* clear (just) interrupts */ 872 writel (status, &ehci->regs->status); 873 readl (&ehci->regs->command); /* unblock posted write */ 874 bh = 0; 875 876#ifdef EHCI_VERBOSE_DEBUG 877 /* unrequested/ignored: Frame List Rollover */ 878 dbg_status (ehci, "irq", status); 879#endif 880 881 /* INT, ERR, and IAA interrupt rates can be throttled */ 882 883 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 884 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 885 if (likely ((status & STS_ERR) == 0)) 886 COUNT (ehci->stats.normal); 887 else 888 COUNT (ehci->stats.error); 889 bh = 1; 890 } 891 892 /* complete the unlinking of some qh [4.15.2.3] */ 893 if (status & STS_IAA) { 894 COUNT (ehci->stats.reclaim); 895 ehci->reclaim_ready = 1; 896 bh = 1; 897 } 898 899 /* remote wakeup [4.3.1] */ 900 if ((status & STS_PCD) && hcd->remote_wakeup) { 901 unsigned i = HCS_N_PORTS (ehci->hcs_params); 902 903 /* resume root hub? */ 904 status = readl (&ehci->regs->command); 905 if (!(status & CMD_RUN)) 906 writel (status | CMD_RUN, &ehci->regs->command); 907 908 while (i--) { 909 status = readl (&ehci->regs->port_status [i]); 910 if (status & PORT_OWNER) 911 continue; 912 if (!(status & PORT_RESUME) 913 || ehci->reset_done [i] != 0) 914 continue; 915 916 /* start 20 msec resume signaling from this port, 917 * and make khubd collect PORT_STAT_C_SUSPEND to 918 * stop that signaling. 919 */ 920 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); 921 mod_timer (&hcd->rh_timer, 922 ehci->reset_done [i] + 1); 923 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 924 } 925 } 926 927 /* PCI errors [4.15.2.4] */ 928 if (unlikely ((status & STS_FATAL) != 0)) { 929 /* bogus "fatal" IRQs appear on some chips... why? */ 930 status = readl (&ehci->regs->status); 931 dbg_cmd (ehci, "fatal", readl (&ehci->regs->command)); 932 dbg_status (ehci, "fatal", status); 933 if (status & STS_HALT) { 934 ehci_err (ehci, "fatal error\n"); 935dead: 936 ehci_reset (ehci); 937 writel (0, &ehci->regs->configured_flag); 938 /* generic layer kills/unlinks all urbs, then 939 * uses ehci_stop to clean up the rest 940 */ 941 bh = 1; 942 } 943 } 944 945 if (bh) 946 ehci_work (ehci, regs); 947 spin_unlock (&ehci->lock); 948 return IRQ_HANDLED; 949} 950 951/*-------------------------------------------------------------------------*/ 952 953/* 954 * non-error returns are a promise to giveback() the urb later 955 * we drop ownership so next owner (or urb unlink) can get it 956 * 957 * urb + dev is in hcd.self.controller.urb_list 958 * we're queueing TDs onto software and hardware lists 959 * 960 * hcd-specific init for hcpriv hasn't been done yet 961 * 962 * NOTE: control, bulk, and interrupt share the same code to append TDs 963 * to a (possibly active) QH, and the same QH scanning code. 964 */ 965static int ehci_urb_enqueue ( 966 struct usb_hcd *hcd, 967 struct usb_host_endpoint *ep, 968 struct urb *urb, 969 unsigned mem_flags 970) { 971 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 972 struct list_head qtd_list; 973 974 INIT_LIST_HEAD (&qtd_list); 975 976 switch (usb_pipetype (urb->pipe)) { 977 // case PIPE_CONTROL: 978 // case PIPE_BULK: 979 default: 980 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 981 return -ENOMEM; 982 return submit_async (ehci, ep, urb, &qtd_list, mem_flags); 983 984 case PIPE_INTERRUPT: 985 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 986 return -ENOMEM; 987 return intr_submit (ehci, ep, urb, &qtd_list, mem_flags); 988 989 case PIPE_ISOCHRONOUS: 990 if (urb->dev->speed == USB_SPEED_HIGH) 991 return itd_submit (ehci, urb, mem_flags); 992 else 993 return sitd_submit (ehci, urb, mem_flags); 994 } 995} 996 997static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 998{ 999 /* if we need to use IAA and it's busy, defer */ 1000 if (qh->qh_state == QH_STATE_LINKED 1001 && ehci->reclaim 1002 && HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) { 1003 struct ehci_qh *last; 1004 1005 for (last = ehci->reclaim; 1006 last->reclaim; 1007 last = last->reclaim) 1008 continue; 1009 qh->qh_state = QH_STATE_UNLINK_WAIT; 1010 last->reclaim = qh; 1011 1012 /* bypass IAA if the hc can't care */ 1013 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && ehci->reclaim) 1014 end_unlink_async (ehci, NULL); 1015 1016 /* something else might have unlinked the qh by now */ 1017 if (qh->qh_state == QH_STATE_LINKED) 1018 start_unlink_async (ehci, qh); 1019} 1020 1021/* remove from hardware lists 1022 * completions normally happen asynchronously 1023 */ 1024 1025static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) 1026{ 1027 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1028 struct ehci_qh *qh; 1029 unsigned long flags; 1030 1031 spin_lock_irqsave (&ehci->lock, flags); 1032 switch (usb_pipetype (urb->pipe)) { 1033 // case PIPE_CONTROL: 1034 // case PIPE_BULK: 1035 default: 1036 qh = (struct ehci_qh *) urb->hcpriv; 1037 if (!qh) 1038 break; 1039 unlink_async (ehci, qh); 1040 break; 1041 1042 case PIPE_INTERRUPT: 1043 qh = (struct ehci_qh *) urb->hcpriv; 1044 if (!qh) 1045 break; 1046 switch (qh->qh_state) { 1047 case QH_STATE_LINKED: 1048 intr_deschedule (ehci, qh); 1049 /* FALL THROUGH */ 1050 case QH_STATE_IDLE: 1051 qh_completions (ehci, qh, NULL); 1052 break; 1053 default: 1054 ehci_dbg (ehci, "bogus qh %p state %d\n", 1055 qh, qh->qh_state); 1056 goto done; 1057 } 1058 1059 /* reschedule QH iff another request is queued */ 1060 if (!list_empty (&qh->qtd_list) 1061 && HC_IS_RUNNING (hcd->state)) { 1062 int status; 1063 1064 status = qh_schedule (ehci, qh); 1065 spin_unlock_irqrestore (&ehci->lock, flags); 1066 1067 if (status != 0) { 1068 // shouldn't happen often, but ... 1069 // FIXME kill those tds' urbs 1070 err ("can't reschedule qh %p, err %d", 1071 qh, status); 1072 } 1073 return status; 1074 } 1075 break; 1076 1077 case PIPE_ISOCHRONOUS: 1078 // itd or sitd ... 1079 1080 // wait till next completion, do it then. 1081 // completion irqs can wait up to 1024 msec, 1082 break; 1083 } 1084done: 1085 spin_unlock_irqrestore (&ehci->lock, flags); 1086 return 0; 1087} 1088 1089/*-------------------------------------------------------------------------*/ 1090 1091// bulk qh holds the data toggle 1092 1093static void 1094ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1095{ 1096 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1097 unsigned long flags; 1098 struct ehci_qh *qh, *tmp; 1099 1100 /* ASSERT: any requests/urbs are being unlinked */ 1101 /* ASSERT: nobody can be submitting urbs for this any more */ 1102 1103rescan: 1104 spin_lock_irqsave (&ehci->lock, flags); 1105 qh = ep->hcpriv; 1106 if (!qh) 1107 goto done; 1108 1109 /* endpoints can be iso streams. for now, we don't 1110 * accelerate iso completions ... so spin a while. 1111 */ 1112 if (qh->hw_info1 == 0) { 1113 ehci_vdbg (ehci, "iso delay\n"); 1114 goto idle_timeout; 1115 } 1116 1117 if (!HC_IS_RUNNING (hcd->state)) 1118 qh->qh_state = QH_STATE_IDLE; 1119 switch (qh->qh_state) { 1120 case QH_STATE_LINKED: 1121 for (tmp = ehci->async->qh_next.qh; 1122 tmp && tmp != qh; 1123 tmp = tmp->qh_next.qh) 1124 continue; 1125 /* periodic qh self-unlinks on empty */ 1126 if (!tmp) 1127 goto nogood; 1128 unlink_async (ehci, qh); 1129 /* FALL THROUGH */ 1130 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1131idle_timeout: 1132 spin_unlock_irqrestore (&ehci->lock, flags); 1133 set_current_state (TASK_UNINTERRUPTIBLE); 1134 schedule_timeout (1); 1135 goto rescan; 1136 case QH_STATE_IDLE: /* fully unlinked */ 1137 if (list_empty (&qh->qtd_list)) { 1138 qh_put (qh); 1139 break; 1140 } 1141 /* else FALL THROUGH */ 1142 default: 1143nogood: 1144 /* caller was supposed to have unlinked any requests; 1145 * that's not our job. just leak this memory. 1146 */ 1147 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1148 qh, ep->desc.bEndpointAddress, qh->qh_state, 1149 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1150 break; 1151 } 1152 ep->hcpriv = NULL; 1153done: 1154 spin_unlock_irqrestore (&ehci->lock, flags); 1155 return; 1156} 1157 1158/*-------------------------------------------------------------------------*/ 1159 1160static const struct hc_driver ehci_driver = { 1161 .description = hcd_name, 1162 .product_desc = "EHCI Host Controller", 1163 .hcd_priv_size = sizeof(struct ehci_hcd), 1164 1165 /* 1166 * generic hardware linkage 1167 */ 1168 .irq = ehci_irq, 1169 .flags = HCD_MEMORY | HCD_USB2, 1170 1171 /* 1172 * basic lifecycle operations 1173 */ 1174 .reset = ehci_hc_reset, 1175 .start = ehci_start, 1176#ifdef CONFIG_PM 1177 .suspend = ehci_suspend, 1178 .resume = ehci_resume, 1179#endif 1180 .stop = ehci_stop, 1181 1182 /* 1183 * managing i/o requests and associated device resources 1184 */ 1185 .urb_enqueue = ehci_urb_enqueue, 1186 .urb_dequeue = ehci_urb_dequeue, 1187 .endpoint_disable = ehci_endpoint_disable, 1188 1189 /* 1190 * scheduling support 1191 */ 1192 .get_frame_number = ehci_get_frame, 1193 1194 /* 1195 * root hub support 1196 */ 1197 .hub_status_data = ehci_hub_status_data, 1198 .hub_control = ehci_hub_control, 1199 .hub_suspend = ehci_hub_suspend, 1200 .hub_resume = ehci_hub_resume, 1201}; 1202 1203/*-------------------------------------------------------------------------*/ 1204 1205/* EHCI 1.0 doesn't require PCI */ 1206 1207#ifdef CONFIG_PCI 1208 1209/* PCI driver selection metadata; PCI hotplugging uses this */ 1210static const struct pci_device_id pci_ids [] = { { 1211 /* handle any USB 2.0 EHCI controller */ 1212 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0), 1213 .driver_data = (unsigned long) &ehci_driver, 1214 }, 1215 { /* end: all zeroes */ } 1216}; 1217MODULE_DEVICE_TABLE (pci, pci_ids); 1218 1219/* pci driver glue; this is a "new style" PCI driver module */ 1220static struct pci_driver ehci_pci_driver = { 1221 .name = (char *) hcd_name, 1222 .id_table = pci_ids, 1223 1224 .probe = usb_hcd_pci_probe, 1225 .remove = usb_hcd_pci_remove, 1226 1227#ifdef CONFIG_PM 1228 .suspend = usb_hcd_pci_suspend, 1229 .resume = usb_hcd_pci_resume, 1230#endif 1231}; 1232 1233#endif /* PCI */ 1234 1235 1236#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC 1237 1238MODULE_DESCRIPTION (DRIVER_INFO); 1239MODULE_AUTHOR (DRIVER_AUTHOR); 1240MODULE_LICENSE ("GPL"); 1241 1242static int __init init (void) 1243{ 1244 if (usb_disabled()) 1245 return -ENODEV; 1246 1247 pr_debug ("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1248 hcd_name, 1249 sizeof (struct ehci_qh), sizeof (struct ehci_qtd), 1250 sizeof (struct ehci_itd), sizeof (struct ehci_sitd)); 1251 1252 return pci_register_driver (&ehci_pci_driver); 1253} 1254module_init (init); 1255 1256static void __exit cleanup (void) 1257{ 1258 pci_unregister_driver (&ehci_pci_driver); 1259} 1260module_exit (cleanup); 1261