ehci-hcd.c revision 479b46b5599b1e610630d7332e168c1f9c4ee0b4
1/* 2 * Copyright (c) 2000-2004 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/dmapool.h> 22#include <linux/kernel.h> 23#include <linux/delay.h> 24#include <linux/ioport.h> 25#include <linux/sched.h> 26#include <linux/vmalloc.h> 27#include <linux/errno.h> 28#include <linux/init.h> 29#include <linux/timer.h> 30#include <linux/ktime.h> 31#include <linux/list.h> 32#include <linux/interrupt.h> 33#include <linux/usb.h> 34#include <linux/usb/hcd.h> 35#include <linux/moduleparam.h> 36#include <linux/dma-mapping.h> 37#include <linux/debugfs.h> 38#include <linux/slab.h> 39#include <linux/uaccess.h> 40 41#include <asm/byteorder.h> 42#include <asm/io.h> 43#include <asm/irq.h> 44#include <asm/system.h> 45#include <asm/unaligned.h> 46 47/*-------------------------------------------------------------------------*/ 48 49/* 50 * EHCI hc_driver implementation ... experimental, incomplete. 51 * Based on the final 1.0 register interface specification. 52 * 53 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 54 * First was PCMCIA, like ISA; then CardBus, which is PCI. 55 * Next comes "CardBay", using USB 2.0 signals. 56 * 57 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 58 * Special thanks to Intel and VIA for providing host controllers to 59 * test this driver on, and Cypress (including In-System Design) for 60 * providing early devices for those host controllers to talk to! 61 */ 62 63#define DRIVER_AUTHOR "David Brownell" 64#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 65 66static const char hcd_name [] = "ehci_hcd"; 67 68 69#undef VERBOSE_DEBUG 70#undef EHCI_URB_TRACE 71 72#ifdef DEBUG 73#define EHCI_STATS 74#endif 75 76/* magic numbers that can affect system performance */ 77#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 78#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 79#define EHCI_TUNE_RL_TT 0 80#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 81#define EHCI_TUNE_MULT_TT 1 82/* 83 * Some drivers think it's safe to schedule isochronous transfers more than 84 * 256 ms into the future (partly as a result of an old bug in the scheduling 85 * code). In an attempt to avoid trouble, we will use a minimum scheduling 86 * length of 512 frames instead of 256. 87 */ 88#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 89 90#define EHCI_IAA_MSECS 10 /* arbitrary */ 91#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 92#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 93#define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */ 94 95/* Initial IRQ latency: faster than hw default */ 96static int log2_irq_thresh = 0; // 0 to 6 97module_param (log2_irq_thresh, int, S_IRUGO); 98MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 99 100/* initial park setting: slower than hw default */ 101static unsigned park = 0; 102module_param (park, uint, S_IRUGO); 103MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 104 105/* for flakey hardware, ignore overcurrent indicators */ 106static int ignore_oc = 0; 107module_param (ignore_oc, bool, S_IRUGO); 108MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 109 110/* for link power management(LPM) feature */ 111static unsigned int hird; 112module_param(hird, int, S_IRUGO); 113MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n"); 114 115#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 116 117/* for ASPM quirk of ISOC on AMD SB800 */ 118static struct pci_dev *amd_nb_dev; 119 120/*-------------------------------------------------------------------------*/ 121 122#include "ehci.h" 123#include "ehci-dbg.c" 124 125/*-------------------------------------------------------------------------*/ 126 127static void 128timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) 129{ 130 /* Don't override timeouts which shrink or (later) disable 131 * the async ring; just the I/O watchdog. Note that if a 132 * SHRINK were pending, OFF would never be requested. 133 */ 134 if (timer_pending(&ehci->watchdog) 135 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 136 & ehci->actions)) 137 return; 138 139 if (!test_and_set_bit(action, &ehci->actions)) { 140 unsigned long t; 141 142 switch (action) { 143 case TIMER_IO_WATCHDOG: 144 if (!ehci->need_io_watchdog) 145 return; 146 t = EHCI_IO_JIFFIES; 147 break; 148 case TIMER_ASYNC_OFF: 149 t = EHCI_ASYNC_JIFFIES; 150 break; 151 /* case TIMER_ASYNC_SHRINK: */ 152 default: 153 /* add a jiffie since we synch against the 154 * 8 KHz uframe counter. 155 */ 156 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; 157 break; 158 } 159 mod_timer(&ehci->watchdog, t + jiffies); 160 } 161} 162 163/*-------------------------------------------------------------------------*/ 164 165/* 166 * handshake - spin reading hc until handshake completes or fails 167 * @ptr: address of hc register to be read 168 * @mask: bits to look at in result of read 169 * @done: value of those bits when handshake succeeds 170 * @usec: timeout in microseconds 171 * 172 * Returns negative errno, or zero on success 173 * 174 * Success happens when the "mask" bits have the specified value (hardware 175 * handshake done). There are two failure modes: "usec" have passed (major 176 * hardware flakeout), or the register reads as all-ones (hardware removed). 177 * 178 * That last failure should_only happen in cases like physical cardbus eject 179 * before driver shutdown. But it also seems to be caused by bugs in cardbus 180 * bridge shutdown: shutting down the bridge before the devices using it. 181 */ 182static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, 183 u32 mask, u32 done, int usec) 184{ 185 u32 result; 186 187 do { 188 result = ehci_readl(ehci, ptr); 189 if (result == ~(u32)0) /* card removed */ 190 return -ENODEV; 191 result &= mask; 192 if (result == done) 193 return 0; 194 udelay (1); 195 usec--; 196 } while (usec > 0); 197 return -ETIMEDOUT; 198} 199 200/* check TDI/ARC silicon is in host mode */ 201static int tdi_in_host_mode (struct ehci_hcd *ehci) 202{ 203 u32 __iomem *reg_ptr; 204 u32 tmp; 205 206 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 207 tmp = ehci_readl(ehci, reg_ptr); 208 return (tmp & 3) == USBMODE_CM_HC; 209} 210 211/* force HC to halt state from unknown (EHCI spec section 2.3) */ 212static int ehci_halt (struct ehci_hcd *ehci) 213{ 214 u32 temp = ehci_readl(ehci, &ehci->regs->status); 215 216 /* disable any irqs left enabled by previous code */ 217 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 218 219 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { 220 return 0; 221 } 222 223 if ((temp & STS_HALT) != 0) 224 return 0; 225 226 temp = ehci_readl(ehci, &ehci->regs->command); 227 temp &= ~CMD_RUN; 228 ehci_writel(ehci, temp, &ehci->regs->command); 229 return handshake (ehci, &ehci->regs->status, 230 STS_HALT, STS_HALT, 16 * 125); 231} 232 233static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, 234 u32 mask, u32 done, int usec) 235{ 236 int error; 237 238 error = handshake(ehci, ptr, mask, done, usec); 239 if (error) { 240 ehci_halt(ehci); 241 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 242 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", 243 ptr, mask, done, error); 244 } 245 246 return error; 247} 248 249/* put TDI/ARC silicon into EHCI mode */ 250static void tdi_reset (struct ehci_hcd *ehci) 251{ 252 u32 __iomem *reg_ptr; 253 u32 tmp; 254 255 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 256 tmp = ehci_readl(ehci, reg_ptr); 257 tmp |= USBMODE_CM_HC; 258 /* The default byte access to MMR space is LE after 259 * controller reset. Set the required endian mode 260 * for transfer buffers to match the host microprocessor 261 */ 262 if (ehci_big_endian_mmio(ehci)) 263 tmp |= USBMODE_BE; 264 ehci_writel(ehci, tmp, reg_ptr); 265} 266 267/* reset a non-running (STS_HALT == 1) controller */ 268static int ehci_reset (struct ehci_hcd *ehci) 269{ 270 int retval; 271 u32 command = ehci_readl(ehci, &ehci->regs->command); 272 273 /* If the EHCI debug controller is active, special care must be 274 * taken before and after a host controller reset */ 275 if (ehci->debug && !dbgp_reset_prep()) 276 ehci->debug = NULL; 277 278 command |= CMD_RESET; 279 dbg_cmd (ehci, "reset", command); 280 ehci_writel(ehci, command, &ehci->regs->command); 281 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 282 ehci->next_statechange = jiffies; 283 retval = handshake (ehci, &ehci->regs->command, 284 CMD_RESET, 0, 250 * 1000); 285 286 if (ehci->has_hostpc) { 287 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 288 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 289 ehci_writel(ehci, TXFIFO_DEFAULT, 290 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); 291 } 292 if (retval) 293 return retval; 294 295 if (ehci_is_TDI(ehci)) 296 tdi_reset (ehci); 297 298 if (ehci->debug) 299 dbgp_external_startup(); 300 301 return retval; 302} 303 304/* idle the controller (from running) */ 305static void ehci_quiesce (struct ehci_hcd *ehci) 306{ 307 u32 temp; 308 309#ifdef DEBUG 310 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) 311 BUG (); 312#endif 313 314 /* wait for any schedule enables/disables to take effect */ 315 temp = ehci_readl(ehci, &ehci->regs->command) << 10; 316 temp &= STS_ASS | STS_PSS; 317 if (handshake_on_error_set_halt(ehci, &ehci->regs->status, 318 STS_ASS | STS_PSS, temp, 16 * 125)) 319 return; 320 321 /* then disable anything that's still active */ 322 temp = ehci_readl(ehci, &ehci->regs->command); 323 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 324 ehci_writel(ehci, temp, &ehci->regs->command); 325 326 /* hardware can take 16 microframes to turn off ... */ 327 handshake_on_error_set_halt(ehci, &ehci->regs->status, 328 STS_ASS | STS_PSS, 0, 16 * 125); 329} 330 331/*-------------------------------------------------------------------------*/ 332 333static void end_unlink_async(struct ehci_hcd *ehci); 334static void ehci_work(struct ehci_hcd *ehci); 335 336#include "ehci-hub.c" 337#include "ehci-lpm.c" 338#include "ehci-mem.c" 339#include "ehci-q.c" 340#include "ehci-sched.c" 341 342/*-------------------------------------------------------------------------*/ 343 344static void ehci_iaa_watchdog(unsigned long param) 345{ 346 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 347 unsigned long flags; 348 349 spin_lock_irqsave (&ehci->lock, flags); 350 351 /* Lost IAA irqs wedge things badly; seen first with a vt8235. 352 * So we need this watchdog, but must protect it against both 353 * (a) SMP races against real IAA firing and retriggering, and 354 * (b) clean HC shutdown, when IAA watchdog was pending. 355 */ 356 if (ehci->reclaim 357 && !timer_pending(&ehci->iaa_watchdog) 358 && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { 359 u32 cmd, status; 360 361 /* If we get here, IAA is *REALLY* late. It's barely 362 * conceivable that the system is so busy that CMD_IAAD 363 * is still legitimately set, so let's be sure it's 364 * clear before we read STS_IAA. (The HC should clear 365 * CMD_IAAD when it sets STS_IAA.) 366 */ 367 cmd = ehci_readl(ehci, &ehci->regs->command); 368 if (cmd & CMD_IAAD) 369 ehci_writel(ehci, cmd & ~CMD_IAAD, 370 &ehci->regs->command); 371 372 /* If IAA is set here it either legitimately triggered 373 * before we cleared IAAD above (but _way_ late, so we'll 374 * still count it as lost) ... or a silicon erratum: 375 * - VIA seems to set IAA without triggering the IRQ; 376 * - IAAD potentially cleared without setting IAA. 377 */ 378 status = ehci_readl(ehci, &ehci->regs->status); 379 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { 380 COUNT (ehci->stats.lost_iaa); 381 ehci_writel(ehci, STS_IAA, &ehci->regs->status); 382 } 383 384 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", 385 status, cmd); 386 end_unlink_async(ehci); 387 } 388 389 spin_unlock_irqrestore(&ehci->lock, flags); 390} 391 392static void ehci_watchdog(unsigned long param) 393{ 394 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 395 unsigned long flags; 396 397 spin_lock_irqsave(&ehci->lock, flags); 398 399 /* stop async processing after it's idled a bit */ 400 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 401 start_unlink_async (ehci, ehci->async); 402 403 /* ehci could run by timer, without IRQs ... */ 404 ehci_work (ehci); 405 406 spin_unlock_irqrestore (&ehci->lock, flags); 407} 408 409/* On some systems, leaving remote wakeup enabled prevents system shutdown. 410 * The firmware seems to think that powering off is a wakeup event! 411 * This routine turns off remote wakeup and everything else, on all ports. 412 */ 413static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 414{ 415 int port = HCS_N_PORTS(ehci->hcs_params); 416 417 while (port--) 418 ehci_writel(ehci, PORT_RWC_BITS, 419 &ehci->regs->port_status[port]); 420} 421 422/* 423 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 424 * Should be called with ehci->lock held. 425 */ 426static void ehci_silence_controller(struct ehci_hcd *ehci) 427{ 428 ehci_halt(ehci); 429 ehci_turn_off_all_ports(ehci); 430 431 /* make BIOS/etc use companion controller during reboot */ 432 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 433 434 /* unblock posted writes */ 435 ehci_readl(ehci, &ehci->regs->configured_flag); 436} 437 438/* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 439 * This forcibly disables dma and IRQs, helping kexec and other cases 440 * where the next system software may expect clean state. 441 */ 442static void ehci_shutdown(struct usb_hcd *hcd) 443{ 444 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 445 446 del_timer_sync(&ehci->watchdog); 447 del_timer_sync(&ehci->iaa_watchdog); 448 449 spin_lock_irq(&ehci->lock); 450 ehci_silence_controller(ehci); 451 spin_unlock_irq(&ehci->lock); 452} 453 454static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 455{ 456 unsigned port; 457 458 if (!HCS_PPC (ehci->hcs_params)) 459 return; 460 461 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 462 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 463 (void) ehci_hub_control(ehci_to_hcd(ehci), 464 is_on ? SetPortFeature : ClearPortFeature, 465 USB_PORT_FEAT_POWER, 466 port--, NULL, 0); 467 /* Flush those writes */ 468 ehci_readl(ehci, &ehci->regs->command); 469 msleep(20); 470} 471 472/*-------------------------------------------------------------------------*/ 473 474/* 475 * ehci_work is called from some interrupts, timers, and so on. 476 * it calls driver completion functions, after dropping ehci->lock. 477 */ 478static void ehci_work (struct ehci_hcd *ehci) 479{ 480 timer_action_done (ehci, TIMER_IO_WATCHDOG); 481 482 /* another CPU may drop ehci->lock during a schedule scan while 483 * it reports urb completions. this flag guards against bogus 484 * attempts at re-entrant schedule scanning. 485 */ 486 if (ehci->scanning) 487 return; 488 ehci->scanning = 1; 489 scan_async (ehci); 490 if (ehci->next_uframe != -1) 491 scan_periodic (ehci); 492 ehci->scanning = 0; 493 494 /* the IO watchdog guards against hardware or driver bugs that 495 * misplace IRQs, and should let us run completely without IRQs. 496 * such lossage has been observed on both VT6202 and VT8235. 497 */ 498 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && 499 (ehci->async->qh_next.ptr != NULL || 500 ehci->periodic_sched != 0)) 501 timer_action (ehci, TIMER_IO_WATCHDOG); 502} 503 504/* 505 * Called when the ehci_hcd module is removed. 506 */ 507static void ehci_stop (struct usb_hcd *hcd) 508{ 509 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 510 511 ehci_dbg (ehci, "stop\n"); 512 513 /* no more interrupts ... */ 514 del_timer_sync (&ehci->watchdog); 515 del_timer_sync(&ehci->iaa_watchdog); 516 517 spin_lock_irq(&ehci->lock); 518 if (HC_IS_RUNNING (hcd->state)) 519 ehci_quiesce (ehci); 520 521 ehci_silence_controller(ehci); 522 ehci_reset (ehci); 523 spin_unlock_irq(&ehci->lock); 524 525 remove_companion_file(ehci); 526 remove_debug_files (ehci); 527 528 /* root hub is shut down separately (first, when possible) */ 529 spin_lock_irq (&ehci->lock); 530 if (ehci->async) 531 ehci_work (ehci); 532 spin_unlock_irq (&ehci->lock); 533 ehci_mem_cleanup (ehci); 534 535 if (amd_nb_dev) { 536 pci_dev_put(amd_nb_dev); 537 amd_nb_dev = NULL; 538 } 539 540#ifdef EHCI_STATS 541 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 542 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 543 ehci->stats.lost_iaa); 544 ehci_dbg (ehci, "complete %ld unlink %ld\n", 545 ehci->stats.complete, ehci->stats.unlink); 546#endif 547 548 dbg_status (ehci, "ehci_stop completed", 549 ehci_readl(ehci, &ehci->regs->status)); 550} 551 552/* one-time init, only for memory state */ 553static int ehci_init(struct usb_hcd *hcd) 554{ 555 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 556 u32 temp; 557 int retval; 558 u32 hcc_params; 559 struct ehci_qh_hw *hw; 560 561 spin_lock_init(&ehci->lock); 562 563 /* 564 * keep io watchdog by default, those good HCDs could turn off it later 565 */ 566 ehci->need_io_watchdog = 1; 567 init_timer(&ehci->watchdog); 568 ehci->watchdog.function = ehci_watchdog; 569 ehci->watchdog.data = (unsigned long) ehci; 570 571 init_timer(&ehci->iaa_watchdog); 572 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 573 ehci->iaa_watchdog.data = (unsigned long) ehci; 574 575 /* 576 * hw default: 1K periodic list heads, one per frame. 577 * periodic_size can shrink by USBCMD update if hcc_params allows. 578 */ 579 ehci->periodic_size = DEFAULT_I_TDPS; 580 INIT_LIST_HEAD(&ehci->cached_itd_list); 581 INIT_LIST_HEAD(&ehci->cached_sitd_list); 582 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 583 return retval; 584 585 /* controllers may cache some of the periodic schedule ... */ 586 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 587 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 588 ehci->i_thresh = 2 + 8; 589 else // N microframes cached 590 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 591 592 ehci->reclaim = NULL; 593 ehci->next_uframe = -1; 594 ehci->clock_frame = -1; 595 596 /* 597 * dedicate a qh for the async ring head, since we couldn't unlink 598 * a 'real' qh without stopping the async schedule [4.8]. use it 599 * as the 'reclamation list head' too. 600 * its dummy is used in hw_alt_next of many tds, to prevent the qh 601 * from automatically advancing to the next td after short reads. 602 */ 603 ehci->async->qh_next.qh = NULL; 604 hw = ehci->async->hw; 605 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 606 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 607 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 608 hw->hw_qtd_next = EHCI_LIST_END(ehci); 609 ehci->async->qh_state = QH_STATE_LINKED; 610 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 611 612 /* clear interrupt enables, set irq latency */ 613 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 614 log2_irq_thresh = 0; 615 temp = 1 << (16 + log2_irq_thresh); 616 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 617 ehci->has_ppcd = 1; 618 ehci_dbg(ehci, "enable per-port change event\n"); 619 temp |= CMD_PPCEE; 620 } 621 if (HCC_CANPARK(hcc_params)) { 622 /* HW default park == 3, on hardware that supports it (like 623 * NVidia and ALI silicon), maximizes throughput on the async 624 * schedule by avoiding QH fetches between transfers. 625 * 626 * With fast usb storage devices and NForce2, "park" seems to 627 * make problems: throughput reduction (!), data errors... 628 */ 629 if (park) { 630 park = min(park, (unsigned) 3); 631 temp |= CMD_PARK; 632 temp |= park << 8; 633 } 634 ehci_dbg(ehci, "park %d\n", park); 635 } 636 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 637 /* periodic schedule size can be smaller than default */ 638 temp &= ~(3 << 2); 639 temp |= (EHCI_TUNE_FLS << 2); 640 switch (EHCI_TUNE_FLS) { 641 case 0: ehci->periodic_size = 1024; break; 642 case 1: ehci->periodic_size = 512; break; 643 case 2: ehci->periodic_size = 256; break; 644 default: BUG(); 645 } 646 } 647 if (HCC_LPM(hcc_params)) { 648 /* support link power management EHCI 1.1 addendum */ 649 ehci_dbg(ehci, "support lpm\n"); 650 ehci->has_lpm = 1; 651 if (hird > 0xf) { 652 ehci_dbg(ehci, "hird %d invalid, use default 0", 653 hird); 654 hird = 0; 655 } 656 temp |= hird << 24; 657 } 658 ehci->command = temp; 659 660 /* Accept arbitrarily long scatter-gather lists */ 661 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 662 hcd->self.sg_tablesize = ~0; 663 return 0; 664} 665 666/* start HC running; it's halted, ehci_init() has been run (once) */ 667static int ehci_run (struct usb_hcd *hcd) 668{ 669 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 670 int retval; 671 u32 temp; 672 u32 hcc_params; 673 674 hcd->uses_new_polling = 1; 675 676 /* EHCI spec section 4.1 */ 677 if ((retval = ehci_reset(ehci)) != 0) { 678 ehci_mem_cleanup(ehci); 679 return retval; 680 } 681 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 682 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 683 684 /* 685 * hcc_params controls whether ehci->regs->segment must (!!!) 686 * be used; it constrains QH/ITD/SITD and QTD locations. 687 * pci_pool consistent memory always uses segment zero. 688 * streaming mappings for I/O buffers, like pci_map_single(), 689 * can return segments above 4GB, if the device allows. 690 * 691 * NOTE: the dma mask is visible through dma_supported(), so 692 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 693 * Scsi_Host.highmem_io, and so forth. It's readonly to all 694 * host side drivers though. 695 */ 696 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 697 if (HCC_64BIT_ADDR(hcc_params)) { 698 ehci_writel(ehci, 0, &ehci->regs->segment); 699#if 0 700// this is deeply broken on almost all architectures 701 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) 702 ehci_info(ehci, "enabled 64bit DMA\n"); 703#endif 704 } 705 706 707 // Philips, Intel, and maybe others need CMD_RUN before the 708 // root hub will detect new devices (why?); NEC doesn't 709 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 710 ehci->command |= CMD_RUN; 711 ehci_writel(ehci, ehci->command, &ehci->regs->command); 712 dbg_cmd (ehci, "init", ehci->command); 713 714 /* 715 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 716 * are explicitly handed to companion controller(s), so no TT is 717 * involved with the root hub. (Except where one is integrated, 718 * and there's no companion controller unless maybe for USB OTG.) 719 * 720 * Turning on the CF flag will transfer ownership of all ports 721 * from the companions to the EHCI controller. If any of the 722 * companions are in the middle of a port reset at the time, it 723 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 724 * guarantees that no resets are in progress. After we set CF, 725 * a short delay lets the hardware catch up; new resets shouldn't 726 * be started before the port switching actions could complete. 727 */ 728 down_write(&ehci_cf_port_reset_rwsem); 729 hcd->state = HC_STATE_RUNNING; 730 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 731 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 732 msleep(5); 733 up_write(&ehci_cf_port_reset_rwsem); 734 ehci->last_periodic_enable = ktime_get_real(); 735 736 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); 737 ehci_info (ehci, 738 "USB %x.%x started, EHCI %x.%02x%s\n", 739 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 740 temp >> 8, temp & 0xff, 741 ignore_oc ? ", overcurrent ignored" : ""); 742 743 ehci_writel(ehci, INTR_MASK, 744 &ehci->regs->intr_enable); /* Turn On Interrupts */ 745 746 /* GRR this is run-once init(), being done every time the HC starts. 747 * So long as they're part of class devices, we can't do it init() 748 * since the class device isn't created that early. 749 */ 750 create_debug_files(ehci); 751 create_companion_file(ehci); 752 753 return 0; 754} 755 756/*-------------------------------------------------------------------------*/ 757 758static irqreturn_t ehci_irq (struct usb_hcd *hcd) 759{ 760 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 761 u32 status, masked_status, pcd_status = 0, cmd; 762 int bh; 763 764 spin_lock (&ehci->lock); 765 766 status = ehci_readl(ehci, &ehci->regs->status); 767 768 /* e.g. cardbus physical eject */ 769 if (status == ~(u32) 0) { 770 ehci_dbg (ehci, "device removed\n"); 771 goto dead; 772 } 773 774 masked_status = status & INTR_MASK; 775 if (!masked_status) { /* irq sharing? */ 776 spin_unlock(&ehci->lock); 777 return IRQ_NONE; 778 } 779 780 /* clear (just) interrupts */ 781 ehci_writel(ehci, masked_status, &ehci->regs->status); 782 cmd = ehci_readl(ehci, &ehci->regs->command); 783 bh = 0; 784 785#ifdef VERBOSE_DEBUG 786 /* unrequested/ignored: Frame List Rollover */ 787 dbg_status (ehci, "irq", status); 788#endif 789 790 /* INT, ERR, and IAA interrupt rates can be throttled */ 791 792 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 793 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 794 if (likely ((status & STS_ERR) == 0)) 795 COUNT (ehci->stats.normal); 796 else 797 COUNT (ehci->stats.error); 798 bh = 1; 799 } 800 801 /* complete the unlinking of some qh [4.15.2.3] */ 802 if (status & STS_IAA) { 803 /* guard against (alleged) silicon errata */ 804 if (cmd & CMD_IAAD) { 805 ehci_writel(ehci, cmd & ~CMD_IAAD, 806 &ehci->regs->command); 807 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 808 } 809 if (ehci->reclaim) { 810 COUNT(ehci->stats.reclaim); 811 end_unlink_async(ehci); 812 } else 813 ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); 814 } 815 816 /* remote wakeup [4.3.1] */ 817 if (status & STS_PCD) { 818 unsigned i = HCS_N_PORTS (ehci->hcs_params); 819 u32 ppcd = 0; 820 821 /* kick root hub later */ 822 pcd_status = status; 823 824 /* resume root hub? */ 825 if (!(cmd & CMD_RUN)) 826 usb_hcd_resume_root_hub(hcd); 827 828 /* get per-port change detect bits */ 829 if (ehci->has_ppcd) 830 ppcd = status >> 16; 831 832 while (i--) { 833 int pstatus; 834 835 /* leverage per-port change bits feature */ 836 if (ehci->has_ppcd && !(ppcd & (1 << i))) 837 continue; 838 pstatus = ehci_readl(ehci, 839 &ehci->regs->port_status[i]); 840 841 if (pstatus & PORT_OWNER) 842 continue; 843 if (!(test_bit(i, &ehci->suspended_ports) && 844 ((pstatus & PORT_RESUME) || 845 !(pstatus & PORT_SUSPEND)) && 846 (pstatus & PORT_PE) && 847 ehci->reset_done[i] == 0)) 848 continue; 849 850 /* start 20 msec resume signaling from this port, 851 * and make khubd collect PORT_STAT_C_SUSPEND to 852 * stop that signaling. Use 5 ms extra for safety, 853 * like usb_port_resume() does. 854 */ 855 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); 856 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 857 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 858 } 859 } 860 861 /* PCI errors [4.15.2.4] */ 862 if (unlikely ((status & STS_FATAL) != 0)) { 863 ehci_err(ehci, "fatal error\n"); 864 dbg_cmd(ehci, "fatal", cmd); 865 dbg_status(ehci, "fatal", status); 866 ehci_halt(ehci); 867dead: 868 ehci_reset(ehci); 869 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 870 /* generic layer kills/unlinks all urbs, then 871 * uses ehci_stop to clean up the rest 872 */ 873 bh = 1; 874 } 875 876 if (bh) 877 ehci_work (ehci); 878 spin_unlock (&ehci->lock); 879 if (pcd_status) 880 usb_hcd_poll_rh_status(hcd); 881 return IRQ_HANDLED; 882} 883 884/*-------------------------------------------------------------------------*/ 885 886/* 887 * non-error returns are a promise to giveback() the urb later 888 * we drop ownership so next owner (or urb unlink) can get it 889 * 890 * urb + dev is in hcd.self.controller.urb_list 891 * we're queueing TDs onto software and hardware lists 892 * 893 * hcd-specific init for hcpriv hasn't been done yet 894 * 895 * NOTE: control, bulk, and interrupt share the same code to append TDs 896 * to a (possibly active) QH, and the same QH scanning code. 897 */ 898static int ehci_urb_enqueue ( 899 struct usb_hcd *hcd, 900 struct urb *urb, 901 gfp_t mem_flags 902) { 903 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 904 struct list_head qtd_list; 905 906 INIT_LIST_HEAD (&qtd_list); 907 908 switch (usb_pipetype (urb->pipe)) { 909 case PIPE_CONTROL: 910 /* qh_completions() code doesn't handle all the fault cases 911 * in multi-TD control transfers. Even 1KB is rare anyway. 912 */ 913 if (urb->transfer_buffer_length > (16 * 1024)) 914 return -EMSGSIZE; 915 /* FALLTHROUGH */ 916 /* case PIPE_BULK: */ 917 default: 918 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 919 return -ENOMEM; 920 return submit_async(ehci, urb, &qtd_list, mem_flags); 921 922 case PIPE_INTERRUPT: 923 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 924 return -ENOMEM; 925 return intr_submit(ehci, urb, &qtd_list, mem_flags); 926 927 case PIPE_ISOCHRONOUS: 928 if (urb->dev->speed == USB_SPEED_HIGH) 929 return itd_submit (ehci, urb, mem_flags); 930 else 931 return sitd_submit (ehci, urb, mem_flags); 932 } 933} 934 935static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 936{ 937 /* failfast */ 938 if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) 939 end_unlink_async(ehci); 940 941 /* If the QH isn't linked then there's nothing we can do 942 * unless we were called during a giveback, in which case 943 * qh_completions() has to deal with it. 944 */ 945 if (qh->qh_state != QH_STATE_LINKED) { 946 if (qh->qh_state == QH_STATE_COMPLETING) 947 qh->needs_rescan = 1; 948 return; 949 } 950 951 /* defer till later if busy */ 952 if (ehci->reclaim) { 953 struct ehci_qh *last; 954 955 for (last = ehci->reclaim; 956 last->reclaim; 957 last = last->reclaim) 958 continue; 959 qh->qh_state = QH_STATE_UNLINK_WAIT; 960 last->reclaim = qh; 961 962 /* start IAA cycle */ 963 } else 964 start_unlink_async (ehci, qh); 965} 966 967/* remove from hardware lists 968 * completions normally happen asynchronously 969 */ 970 971static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 972{ 973 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 974 struct ehci_qh *qh; 975 unsigned long flags; 976 int rc; 977 978 spin_lock_irqsave (&ehci->lock, flags); 979 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 980 if (rc) 981 goto done; 982 983 switch (usb_pipetype (urb->pipe)) { 984 // case PIPE_CONTROL: 985 // case PIPE_BULK: 986 default: 987 qh = (struct ehci_qh *) urb->hcpriv; 988 if (!qh) 989 break; 990 switch (qh->qh_state) { 991 case QH_STATE_LINKED: 992 case QH_STATE_COMPLETING: 993 unlink_async(ehci, qh); 994 break; 995 case QH_STATE_UNLINK: 996 case QH_STATE_UNLINK_WAIT: 997 /* already started */ 998 break; 999 case QH_STATE_IDLE: 1000 /* QH might be waiting for a Clear-TT-Buffer */ 1001 qh_completions(ehci, qh); 1002 break; 1003 } 1004 break; 1005 1006 case PIPE_INTERRUPT: 1007 qh = (struct ehci_qh *) urb->hcpriv; 1008 if (!qh) 1009 break; 1010 switch (qh->qh_state) { 1011 case QH_STATE_LINKED: 1012 case QH_STATE_COMPLETING: 1013 intr_deschedule (ehci, qh); 1014 break; 1015 case QH_STATE_IDLE: 1016 qh_completions (ehci, qh); 1017 break; 1018 default: 1019 ehci_dbg (ehci, "bogus qh %p state %d\n", 1020 qh, qh->qh_state); 1021 goto done; 1022 } 1023 break; 1024 1025 case PIPE_ISOCHRONOUS: 1026 // itd or sitd ... 1027 1028 // wait till next completion, do it then. 1029 // completion irqs can wait up to 1024 msec, 1030 break; 1031 } 1032done: 1033 spin_unlock_irqrestore (&ehci->lock, flags); 1034 return rc; 1035} 1036 1037/*-------------------------------------------------------------------------*/ 1038 1039// bulk qh holds the data toggle 1040 1041static void 1042ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1043{ 1044 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1045 unsigned long flags; 1046 struct ehci_qh *qh, *tmp; 1047 1048 /* ASSERT: any requests/urbs are being unlinked */ 1049 /* ASSERT: nobody can be submitting urbs for this any more */ 1050 1051rescan: 1052 spin_lock_irqsave (&ehci->lock, flags); 1053 qh = ep->hcpriv; 1054 if (!qh) 1055 goto done; 1056 1057 /* endpoints can be iso streams. for now, we don't 1058 * accelerate iso completions ... so spin a while. 1059 */ 1060 if (qh->hw == NULL) { 1061 ehci_vdbg (ehci, "iso delay\n"); 1062 goto idle_timeout; 1063 } 1064 1065 if (!HC_IS_RUNNING (hcd->state)) 1066 qh->qh_state = QH_STATE_IDLE; 1067 switch (qh->qh_state) { 1068 case QH_STATE_LINKED: 1069 case QH_STATE_COMPLETING: 1070 for (tmp = ehci->async->qh_next.qh; 1071 tmp && tmp != qh; 1072 tmp = tmp->qh_next.qh) 1073 continue; 1074 /* periodic qh self-unlinks on empty, and a COMPLETING qh 1075 * may already be unlinked. 1076 */ 1077 if (tmp) 1078 unlink_async(ehci, qh); 1079 /* FALL THROUGH */ 1080 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1081 case QH_STATE_UNLINK_WAIT: 1082idle_timeout: 1083 spin_unlock_irqrestore (&ehci->lock, flags); 1084 schedule_timeout_uninterruptible(1); 1085 goto rescan; 1086 case QH_STATE_IDLE: /* fully unlinked */ 1087 if (qh->clearing_tt) 1088 goto idle_timeout; 1089 if (list_empty (&qh->qtd_list)) { 1090 qh_put (qh); 1091 break; 1092 } 1093 /* else FALL THROUGH */ 1094 default: 1095 /* caller was supposed to have unlinked any requests; 1096 * that's not our job. just leak this memory. 1097 */ 1098 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1099 qh, ep->desc.bEndpointAddress, qh->qh_state, 1100 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1101 break; 1102 } 1103 ep->hcpriv = NULL; 1104done: 1105 spin_unlock_irqrestore (&ehci->lock, flags); 1106} 1107 1108static void 1109ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1110{ 1111 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1112 struct ehci_qh *qh; 1113 int eptype = usb_endpoint_type(&ep->desc); 1114 int epnum = usb_endpoint_num(&ep->desc); 1115 int is_out = usb_endpoint_dir_out(&ep->desc); 1116 unsigned long flags; 1117 1118 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1119 return; 1120 1121 spin_lock_irqsave(&ehci->lock, flags); 1122 qh = ep->hcpriv; 1123 1124 /* For Bulk and Interrupt endpoints we maintain the toggle state 1125 * in the hardware; the toggle bits in udev aren't used at all. 1126 * When an endpoint is reset by usb_clear_halt() we must reset 1127 * the toggle bit in the QH. 1128 */ 1129 if (qh) { 1130 usb_settoggle(qh->dev, epnum, is_out, 0); 1131 if (!list_empty(&qh->qtd_list)) { 1132 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1133 } else if (qh->qh_state == QH_STATE_LINKED || 1134 qh->qh_state == QH_STATE_COMPLETING) { 1135 1136 /* The toggle value in the QH can't be updated 1137 * while the QH is active. Unlink it now; 1138 * re-linking will call qh_refresh(). 1139 */ 1140 if (eptype == USB_ENDPOINT_XFER_BULK) 1141 unlink_async(ehci, qh); 1142 else 1143 intr_deschedule(ehci, qh); 1144 } 1145 } 1146 spin_unlock_irqrestore(&ehci->lock, flags); 1147} 1148 1149static int ehci_get_frame (struct usb_hcd *hcd) 1150{ 1151 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1152 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % 1153 ehci->periodic_size; 1154} 1155 1156/*-------------------------------------------------------------------------*/ 1157 1158MODULE_DESCRIPTION(DRIVER_DESC); 1159MODULE_AUTHOR (DRIVER_AUTHOR); 1160MODULE_LICENSE ("GPL"); 1161 1162#ifdef CONFIG_PCI 1163#include "ehci-pci.c" 1164#define PCI_DRIVER ehci_pci_driver 1165#endif 1166 1167#ifdef CONFIG_USB_EHCI_FSL 1168#include "ehci-fsl.c" 1169#define PLATFORM_DRIVER ehci_fsl_driver 1170#endif 1171 1172#ifdef CONFIG_USB_EHCI_MXC 1173#include "ehci-mxc.c" 1174#define PLATFORM_DRIVER ehci_mxc_driver 1175#endif 1176 1177#ifdef CONFIG_CPU_SUBTYPE_SH7786 1178#include "ehci-sh.c" 1179#define PLATFORM_DRIVER ehci_hcd_sh_driver 1180#endif 1181 1182#ifdef CONFIG_SOC_AU1200 1183#include "ehci-au1xxx.c" 1184#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 1185#endif 1186 1187#ifdef CONFIG_USB_EHCI_HCD_OMAP 1188#include "ehci-omap.c" 1189#define PLATFORM_DRIVER ehci_hcd_omap_driver 1190#endif 1191 1192#ifdef CONFIG_PPC_PS3 1193#include "ehci-ps3.c" 1194#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1195#endif 1196 1197#ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1198#include "ehci-ppc-of.c" 1199#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1200#endif 1201 1202#ifdef CONFIG_XPS_USB_HCD_XILINX 1203#include "ehci-xilinx-of.c" 1204#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1205#endif 1206 1207#ifdef CONFIG_PLAT_ORION 1208#include "ehci-orion.c" 1209#define PLATFORM_DRIVER ehci_orion_driver 1210#endif 1211 1212#ifdef CONFIG_ARCH_IXP4XX 1213#include "ehci-ixp4xx.c" 1214#define PLATFORM_DRIVER ixp4xx_ehci_driver 1215#endif 1216 1217#ifdef CONFIG_USB_W90X900_EHCI 1218#include "ehci-w90x900.c" 1219#define PLATFORM_DRIVER ehci_hcd_w90x900_driver 1220#endif 1221 1222#ifdef CONFIG_ARCH_AT91 1223#include "ehci-atmel.c" 1224#define PLATFORM_DRIVER ehci_atmel_driver 1225#endif 1226 1227#ifdef CONFIG_USB_OCTEON_EHCI 1228#include "ehci-octeon.c" 1229#define PLATFORM_DRIVER ehci_octeon_driver 1230#endif 1231 1232#ifdef CONFIG_USB_CNS3XXX_EHCI 1233#include "ehci-cns3xxx.c" 1234#define PLATFORM_DRIVER cns3xxx_ehci_driver 1235#endif 1236 1237#ifdef CONFIG_ARCH_VT8500 1238#include "ehci-vt8500.c" 1239#define PLATFORM_DRIVER vt8500_ehci_driver 1240#endif 1241 1242#ifdef CONFIG_PLAT_SPEAR 1243#include "ehci-spear.c" 1244#define PLATFORM_DRIVER spear_ehci_hcd_driver 1245#endif 1246 1247#ifdef CONFIG_USB_EHCI_MSM 1248#include "ehci-msm.c" 1249#define PLATFORM_DRIVER ehci_msm_driver 1250#endif 1251 1252#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1253 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1254 !defined(XILINX_OF_PLATFORM_DRIVER) 1255#error "missing bus glue for ehci-hcd" 1256#endif 1257 1258static int __init ehci_hcd_init(void) 1259{ 1260 int retval = 0; 1261 1262 if (usb_disabled()) 1263 return -ENODEV; 1264 1265 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1266 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1267 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1268 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1269 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1270 " before uhci_hcd and ohci_hcd, not after\n"); 1271 1272 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1273 hcd_name, 1274 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1275 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1276 1277#ifdef DEBUG 1278 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1279 if (!ehci_debug_root) { 1280 retval = -ENOENT; 1281 goto err_debug; 1282 } 1283#endif 1284 1285#ifdef PLATFORM_DRIVER 1286 retval = platform_driver_register(&PLATFORM_DRIVER); 1287 if (retval < 0) 1288 goto clean0; 1289#endif 1290 1291#ifdef PCI_DRIVER 1292 retval = pci_register_driver(&PCI_DRIVER); 1293 if (retval < 0) 1294 goto clean1; 1295#endif 1296 1297#ifdef PS3_SYSTEM_BUS_DRIVER 1298 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1299 if (retval < 0) 1300 goto clean2; 1301#endif 1302 1303#ifdef OF_PLATFORM_DRIVER 1304 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); 1305 if (retval < 0) 1306 goto clean3; 1307#endif 1308 1309#ifdef XILINX_OF_PLATFORM_DRIVER 1310 retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER); 1311 if (retval < 0) 1312 goto clean4; 1313#endif 1314 return retval; 1315 1316#ifdef XILINX_OF_PLATFORM_DRIVER 1317 /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */ 1318clean4: 1319#endif 1320#ifdef OF_PLATFORM_DRIVER 1321 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1322clean3: 1323#endif 1324#ifdef PS3_SYSTEM_BUS_DRIVER 1325 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1326clean2: 1327#endif 1328#ifdef PCI_DRIVER 1329 pci_unregister_driver(&PCI_DRIVER); 1330clean1: 1331#endif 1332#ifdef PLATFORM_DRIVER 1333 platform_driver_unregister(&PLATFORM_DRIVER); 1334clean0: 1335#endif 1336#ifdef DEBUG 1337 debugfs_remove(ehci_debug_root); 1338 ehci_debug_root = NULL; 1339err_debug: 1340#endif 1341 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1342 return retval; 1343} 1344module_init(ehci_hcd_init); 1345 1346static void __exit ehci_hcd_cleanup(void) 1347{ 1348#ifdef XILINX_OF_PLATFORM_DRIVER 1349 of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); 1350#endif 1351#ifdef OF_PLATFORM_DRIVER 1352 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1353#endif 1354#ifdef PLATFORM_DRIVER 1355 platform_driver_unregister(&PLATFORM_DRIVER); 1356#endif 1357#ifdef PCI_DRIVER 1358 pci_unregister_driver(&PCI_DRIVER); 1359#endif 1360#ifdef PS3_SYSTEM_BUS_DRIVER 1361 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1362#endif 1363#ifdef DEBUG 1364 debugfs_remove(ehci_debug_root); 1365#endif 1366 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1367} 1368module_exit(ehci_hcd_cleanup); 1369 1370