ehci-hcd.c revision 79ad3b5add4a683af02d1b51ccb699d1b01f1fbf
1/* 2 * Copyright (c) 2000-2004 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/dmapool.h> 22#include <linux/kernel.h> 23#include <linux/delay.h> 24#include <linux/ioport.h> 25#include <linux/sched.h> 26#include <linux/vmalloc.h> 27#include <linux/errno.h> 28#include <linux/init.h> 29#include <linux/timer.h> 30#include <linux/ktime.h> 31#include <linux/list.h> 32#include <linux/interrupt.h> 33#include <linux/usb.h> 34#include <linux/usb/hcd.h> 35#include <linux/moduleparam.h> 36#include <linux/dma-mapping.h> 37#include <linux/debugfs.h> 38#include <linux/slab.h> 39#include <linux/uaccess.h> 40 41#include <asm/byteorder.h> 42#include <asm/io.h> 43#include <asm/irq.h> 44#include <asm/system.h> 45#include <asm/unaligned.h> 46 47/*-------------------------------------------------------------------------*/ 48 49/* 50 * EHCI hc_driver implementation ... experimental, incomplete. 51 * Based on the final 1.0 register interface specification. 52 * 53 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 54 * First was PCMCIA, like ISA; then CardBus, which is PCI. 55 * Next comes "CardBay", using USB 2.0 signals. 56 * 57 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 58 * Special thanks to Intel and VIA for providing host controllers to 59 * test this driver on, and Cypress (including In-System Design) for 60 * providing early devices for those host controllers to talk to! 61 */ 62 63#define DRIVER_AUTHOR "David Brownell" 64#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 65 66static const char hcd_name [] = "ehci_hcd"; 67 68 69#undef VERBOSE_DEBUG 70#undef EHCI_URB_TRACE 71 72#ifdef DEBUG 73#define EHCI_STATS 74#endif 75 76/* magic numbers that can affect system performance */ 77#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 78#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 79#define EHCI_TUNE_RL_TT 0 80#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 81#define EHCI_TUNE_MULT_TT 1 82/* 83 * Some drivers think it's safe to schedule isochronous transfers more than 84 * 256 ms into the future (partly as a result of an old bug in the scheduling 85 * code). In an attempt to avoid trouble, we will use a minimum scheduling 86 * length of 512 frames instead of 256. 87 */ 88#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 89 90#define EHCI_IAA_MSECS 10 /* arbitrary */ 91#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 92#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 93#define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */ 94 95/* Initial IRQ latency: faster than hw default */ 96static int log2_irq_thresh = 0; // 0 to 6 97module_param (log2_irq_thresh, int, S_IRUGO); 98MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 99 100/* initial park setting: slower than hw default */ 101static unsigned park = 0; 102module_param (park, uint, S_IRUGO); 103MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 104 105/* for flakey hardware, ignore overcurrent indicators */ 106static int ignore_oc = 0; 107module_param (ignore_oc, bool, S_IRUGO); 108MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 109 110/* for link power management(LPM) feature */ 111static unsigned int hird; 112module_param(hird, int, S_IRUGO); 113MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n"); 114 115#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 116 117/*-------------------------------------------------------------------------*/ 118 119#include "ehci.h" 120#include "ehci-dbg.c" 121#include "pci-quirks.h" 122 123/*-------------------------------------------------------------------------*/ 124 125static void 126timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) 127{ 128 /* Don't override timeouts which shrink or (later) disable 129 * the async ring; just the I/O watchdog. Note that if a 130 * SHRINK were pending, OFF would never be requested. 131 */ 132 if (timer_pending(&ehci->watchdog) 133 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 134 & ehci->actions)) 135 return; 136 137 if (!test_and_set_bit(action, &ehci->actions)) { 138 unsigned long t; 139 140 switch (action) { 141 case TIMER_IO_WATCHDOG: 142 if (!ehci->need_io_watchdog) 143 return; 144 t = EHCI_IO_JIFFIES; 145 break; 146 case TIMER_ASYNC_OFF: 147 t = EHCI_ASYNC_JIFFIES; 148 break; 149 /* case TIMER_ASYNC_SHRINK: */ 150 default: 151 /* add a jiffie since we synch against the 152 * 8 KHz uframe counter. 153 */ 154 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; 155 break; 156 } 157 mod_timer(&ehci->watchdog, t + jiffies); 158 } 159} 160 161/*-------------------------------------------------------------------------*/ 162 163/* 164 * handshake - spin reading hc until handshake completes or fails 165 * @ptr: address of hc register to be read 166 * @mask: bits to look at in result of read 167 * @done: value of those bits when handshake succeeds 168 * @usec: timeout in microseconds 169 * 170 * Returns negative errno, or zero on success 171 * 172 * Success happens when the "mask" bits have the specified value (hardware 173 * handshake done). There are two failure modes: "usec" have passed (major 174 * hardware flakeout), or the register reads as all-ones (hardware removed). 175 * 176 * That last failure should_only happen in cases like physical cardbus eject 177 * before driver shutdown. But it also seems to be caused by bugs in cardbus 178 * bridge shutdown: shutting down the bridge before the devices using it. 179 */ 180static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, 181 u32 mask, u32 done, int usec) 182{ 183 u32 result; 184 185 do { 186 result = ehci_readl(ehci, ptr); 187 if (result == ~(u32)0) /* card removed */ 188 return -ENODEV; 189 result &= mask; 190 if (result == done) 191 return 0; 192 udelay (1); 193 usec--; 194 } while (usec > 0); 195 return -ETIMEDOUT; 196} 197 198/* check TDI/ARC silicon is in host mode */ 199static int tdi_in_host_mode (struct ehci_hcd *ehci) 200{ 201 u32 __iomem *reg_ptr; 202 u32 tmp; 203 204 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 205 tmp = ehci_readl(ehci, reg_ptr); 206 return (tmp & 3) == USBMODE_CM_HC; 207} 208 209/* force HC to halt state from unknown (EHCI spec section 2.3) */ 210static int ehci_halt (struct ehci_hcd *ehci) 211{ 212 u32 temp = ehci_readl(ehci, &ehci->regs->status); 213 214 /* disable any irqs left enabled by previous code */ 215 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 216 217 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { 218 return 0; 219 } 220 221 if ((temp & STS_HALT) != 0) 222 return 0; 223 224 temp = ehci_readl(ehci, &ehci->regs->command); 225 temp &= ~CMD_RUN; 226 ehci_writel(ehci, temp, &ehci->regs->command); 227 return handshake (ehci, &ehci->regs->status, 228 STS_HALT, STS_HALT, 16 * 125); 229} 230 231static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, 232 u32 mask, u32 done, int usec) 233{ 234 int error; 235 236 error = handshake(ehci, ptr, mask, done, usec); 237 if (error) { 238 ehci_halt(ehci); 239 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 240 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", 241 ptr, mask, done, error); 242 } 243 244 return error; 245} 246 247/* put TDI/ARC silicon into EHCI mode */ 248static void tdi_reset (struct ehci_hcd *ehci) 249{ 250 u32 __iomem *reg_ptr; 251 u32 tmp; 252 253 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 254 tmp = ehci_readl(ehci, reg_ptr); 255 tmp |= USBMODE_CM_HC; 256 /* The default byte access to MMR space is LE after 257 * controller reset. Set the required endian mode 258 * for transfer buffers to match the host microprocessor 259 */ 260 if (ehci_big_endian_mmio(ehci)) 261 tmp |= USBMODE_BE; 262 ehci_writel(ehci, tmp, reg_ptr); 263} 264 265/* reset a non-running (STS_HALT == 1) controller */ 266static int ehci_reset (struct ehci_hcd *ehci) 267{ 268 int retval; 269 u32 command = ehci_readl(ehci, &ehci->regs->command); 270 271 /* If the EHCI debug controller is active, special care must be 272 * taken before and after a host controller reset */ 273 if (ehci->debug && !dbgp_reset_prep()) 274 ehci->debug = NULL; 275 276 command |= CMD_RESET; 277 dbg_cmd (ehci, "reset", command); 278 ehci_writel(ehci, command, &ehci->regs->command); 279 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 280 ehci->next_statechange = jiffies; 281 retval = handshake (ehci, &ehci->regs->command, 282 CMD_RESET, 0, 250 * 1000); 283 284 if (ehci->has_hostpc) { 285 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 286 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 287 ehci_writel(ehci, TXFIFO_DEFAULT, 288 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); 289 } 290 if (retval) 291 return retval; 292 293 if (ehci_is_TDI(ehci)) 294 tdi_reset (ehci); 295 296 if (ehci->debug) 297 dbgp_external_startup(); 298 299 return retval; 300} 301 302/* idle the controller (from running) */ 303static void ehci_quiesce (struct ehci_hcd *ehci) 304{ 305 u32 temp; 306 307#ifdef DEBUG 308 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) 309 BUG (); 310#endif 311 312 /* wait for any schedule enables/disables to take effect */ 313 temp = ehci_readl(ehci, &ehci->regs->command) << 10; 314 temp &= STS_ASS | STS_PSS; 315 if (handshake_on_error_set_halt(ehci, &ehci->regs->status, 316 STS_ASS | STS_PSS, temp, 16 * 125)) 317 return; 318 319 /* then disable anything that's still active */ 320 temp = ehci_readl(ehci, &ehci->regs->command); 321 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 322 ehci_writel(ehci, temp, &ehci->regs->command); 323 324 /* hardware can take 16 microframes to turn off ... */ 325 handshake_on_error_set_halt(ehci, &ehci->regs->status, 326 STS_ASS | STS_PSS, 0, 16 * 125); 327} 328 329/*-------------------------------------------------------------------------*/ 330 331static void end_unlink_async(struct ehci_hcd *ehci); 332static void ehci_work(struct ehci_hcd *ehci); 333 334#include "ehci-hub.c" 335#include "ehci-lpm.c" 336#include "ehci-mem.c" 337#include "ehci-q.c" 338#include "ehci-sched.c" 339 340/*-------------------------------------------------------------------------*/ 341 342static void ehci_iaa_watchdog(unsigned long param) 343{ 344 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 345 unsigned long flags; 346 347 spin_lock_irqsave (&ehci->lock, flags); 348 349 /* Lost IAA irqs wedge things badly; seen first with a vt8235. 350 * So we need this watchdog, but must protect it against both 351 * (a) SMP races against real IAA firing and retriggering, and 352 * (b) clean HC shutdown, when IAA watchdog was pending. 353 */ 354 if (ehci->reclaim 355 && !timer_pending(&ehci->iaa_watchdog) 356 && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { 357 u32 cmd, status; 358 359 /* If we get here, IAA is *REALLY* late. It's barely 360 * conceivable that the system is so busy that CMD_IAAD 361 * is still legitimately set, so let's be sure it's 362 * clear before we read STS_IAA. (The HC should clear 363 * CMD_IAAD when it sets STS_IAA.) 364 */ 365 cmd = ehci_readl(ehci, &ehci->regs->command); 366 if (cmd & CMD_IAAD) 367 ehci_writel(ehci, cmd & ~CMD_IAAD, 368 &ehci->regs->command); 369 370 /* If IAA is set here it either legitimately triggered 371 * before we cleared IAAD above (but _way_ late, so we'll 372 * still count it as lost) ... or a silicon erratum: 373 * - VIA seems to set IAA without triggering the IRQ; 374 * - IAAD potentially cleared without setting IAA. 375 */ 376 status = ehci_readl(ehci, &ehci->regs->status); 377 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { 378 COUNT (ehci->stats.lost_iaa); 379 ehci_writel(ehci, STS_IAA, &ehci->regs->status); 380 } 381 382 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", 383 status, cmd); 384 end_unlink_async(ehci); 385 } 386 387 spin_unlock_irqrestore(&ehci->lock, flags); 388} 389 390static void ehci_watchdog(unsigned long param) 391{ 392 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 393 unsigned long flags; 394 395 spin_lock_irqsave(&ehci->lock, flags); 396 397 /* stop async processing after it's idled a bit */ 398 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 399 start_unlink_async (ehci, ehci->async); 400 401 /* ehci could run by timer, without IRQs ... */ 402 ehci_work (ehci); 403 404 spin_unlock_irqrestore (&ehci->lock, flags); 405} 406 407/* On some systems, leaving remote wakeup enabled prevents system shutdown. 408 * The firmware seems to think that powering off is a wakeup event! 409 * This routine turns off remote wakeup and everything else, on all ports. 410 */ 411static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 412{ 413 int port = HCS_N_PORTS(ehci->hcs_params); 414 415 while (port--) 416 ehci_writel(ehci, PORT_RWC_BITS, 417 &ehci->regs->port_status[port]); 418} 419 420/* 421 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 422 * Should be called with ehci->lock held. 423 */ 424static void ehci_silence_controller(struct ehci_hcd *ehci) 425{ 426 ehci_halt(ehci); 427 ehci_turn_off_all_ports(ehci); 428 429 /* make BIOS/etc use companion controller during reboot */ 430 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 431 432 /* unblock posted writes */ 433 ehci_readl(ehci, &ehci->regs->configured_flag); 434} 435 436/* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 437 * This forcibly disables dma and IRQs, helping kexec and other cases 438 * where the next system software may expect clean state. 439 */ 440static void ehci_shutdown(struct usb_hcd *hcd) 441{ 442 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 443 444 del_timer_sync(&ehci->watchdog); 445 del_timer_sync(&ehci->iaa_watchdog); 446 447 spin_lock_irq(&ehci->lock); 448 ehci_silence_controller(ehci); 449 spin_unlock_irq(&ehci->lock); 450} 451 452static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 453{ 454 unsigned port; 455 456 if (!HCS_PPC (ehci->hcs_params)) 457 return; 458 459 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 460 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 461 (void) ehci_hub_control(ehci_to_hcd(ehci), 462 is_on ? SetPortFeature : ClearPortFeature, 463 USB_PORT_FEAT_POWER, 464 port--, NULL, 0); 465 /* Flush those writes */ 466 ehci_readl(ehci, &ehci->regs->command); 467 msleep(20); 468} 469 470/*-------------------------------------------------------------------------*/ 471 472/* 473 * ehci_work is called from some interrupts, timers, and so on. 474 * it calls driver completion functions, after dropping ehci->lock. 475 */ 476static void ehci_work (struct ehci_hcd *ehci) 477{ 478 timer_action_done (ehci, TIMER_IO_WATCHDOG); 479 480 /* another CPU may drop ehci->lock during a schedule scan while 481 * it reports urb completions. this flag guards against bogus 482 * attempts at re-entrant schedule scanning. 483 */ 484 if (ehci->scanning) 485 return; 486 ehci->scanning = 1; 487 scan_async (ehci); 488 if (ehci->next_uframe != -1) 489 scan_periodic (ehci); 490 ehci->scanning = 0; 491 492 /* the IO watchdog guards against hardware or driver bugs that 493 * misplace IRQs, and should let us run completely without IRQs. 494 * such lossage has been observed on both VT6202 and VT8235. 495 */ 496 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && 497 (ehci->async->qh_next.ptr != NULL || 498 ehci->periodic_sched != 0)) 499 timer_action (ehci, TIMER_IO_WATCHDOG); 500} 501 502/* 503 * Called when the ehci_hcd module is removed. 504 */ 505static void ehci_stop (struct usb_hcd *hcd) 506{ 507 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 508 509 ehci_dbg (ehci, "stop\n"); 510 511 /* no more interrupts ... */ 512 del_timer_sync (&ehci->watchdog); 513 del_timer_sync(&ehci->iaa_watchdog); 514 515 spin_lock_irq(&ehci->lock); 516 if (HC_IS_RUNNING (hcd->state)) 517 ehci_quiesce (ehci); 518 519 ehci_silence_controller(ehci); 520 ehci_reset (ehci); 521 spin_unlock_irq(&ehci->lock); 522 523 remove_companion_file(ehci); 524 remove_debug_files (ehci); 525 526 /* root hub is shut down separately (first, when possible) */ 527 spin_lock_irq (&ehci->lock); 528 if (ehci->async) 529 ehci_work (ehci); 530 spin_unlock_irq (&ehci->lock); 531 ehci_mem_cleanup (ehci); 532 533 if (ehci->amd_pll_fix == 1) 534 usb_amd_dev_put(); 535 536#ifdef EHCI_STATS 537 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 538 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 539 ehci->stats.lost_iaa); 540 ehci_dbg (ehci, "complete %ld unlink %ld\n", 541 ehci->stats.complete, ehci->stats.unlink); 542#endif 543 544 dbg_status (ehci, "ehci_stop completed", 545 ehci_readl(ehci, &ehci->regs->status)); 546} 547 548/* one-time init, only for memory state */ 549static int ehci_init(struct usb_hcd *hcd) 550{ 551 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 552 u32 temp; 553 int retval; 554 u32 hcc_params; 555 struct ehci_qh_hw *hw; 556 557 spin_lock_init(&ehci->lock); 558 559 /* 560 * keep io watchdog by default, those good HCDs could turn off it later 561 */ 562 ehci->need_io_watchdog = 1; 563 init_timer(&ehci->watchdog); 564 ehci->watchdog.function = ehci_watchdog; 565 ehci->watchdog.data = (unsigned long) ehci; 566 567 init_timer(&ehci->iaa_watchdog); 568 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 569 ehci->iaa_watchdog.data = (unsigned long) ehci; 570 571 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 572 573 /* 574 * hw default: 1K periodic list heads, one per frame. 575 * periodic_size can shrink by USBCMD update if hcc_params allows. 576 */ 577 ehci->periodic_size = DEFAULT_I_TDPS; 578 INIT_LIST_HEAD(&ehci->cached_itd_list); 579 INIT_LIST_HEAD(&ehci->cached_sitd_list); 580 581 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 582 /* periodic schedule size can be smaller than default */ 583 switch (EHCI_TUNE_FLS) { 584 case 0: ehci->periodic_size = 1024; break; 585 case 1: ehci->periodic_size = 512; break; 586 case 2: ehci->periodic_size = 256; break; 587 default: BUG(); 588 } 589 } 590 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 591 return retval; 592 593 /* controllers may cache some of the periodic schedule ... */ 594 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 595 ehci->i_thresh = 2 + 8; 596 else // N microframes cached 597 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 598 599 ehci->reclaim = NULL; 600 ehci->next_uframe = -1; 601 ehci->clock_frame = -1; 602 603 /* 604 * dedicate a qh for the async ring head, since we couldn't unlink 605 * a 'real' qh without stopping the async schedule [4.8]. use it 606 * as the 'reclamation list head' too. 607 * its dummy is used in hw_alt_next of many tds, to prevent the qh 608 * from automatically advancing to the next td after short reads. 609 */ 610 ehci->async->qh_next.qh = NULL; 611 hw = ehci->async->hw; 612 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 613 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 614 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 615 hw->hw_qtd_next = EHCI_LIST_END(ehci); 616 ehci->async->qh_state = QH_STATE_LINKED; 617 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 618 619 /* clear interrupt enables, set irq latency */ 620 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 621 log2_irq_thresh = 0; 622 temp = 1 << (16 + log2_irq_thresh); 623 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 624 ehci->has_ppcd = 1; 625 ehci_dbg(ehci, "enable per-port change event\n"); 626 temp |= CMD_PPCEE; 627 } 628 if (HCC_CANPARK(hcc_params)) { 629 /* HW default park == 3, on hardware that supports it (like 630 * NVidia and ALI silicon), maximizes throughput on the async 631 * schedule by avoiding QH fetches between transfers. 632 * 633 * With fast usb storage devices and NForce2, "park" seems to 634 * make problems: throughput reduction (!), data errors... 635 */ 636 if (park) { 637 park = min(park, (unsigned) 3); 638 temp |= CMD_PARK; 639 temp |= park << 8; 640 } 641 ehci_dbg(ehci, "park %d\n", park); 642 } 643 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 644 /* periodic schedule size can be smaller than default */ 645 temp &= ~(3 << 2); 646 temp |= (EHCI_TUNE_FLS << 2); 647 } 648 if (HCC_LPM(hcc_params)) { 649 /* support link power management EHCI 1.1 addendum */ 650 ehci_dbg(ehci, "support lpm\n"); 651 ehci->has_lpm = 1; 652 if (hird > 0xf) { 653 ehci_dbg(ehci, "hird %d invalid, use default 0", 654 hird); 655 hird = 0; 656 } 657 temp |= hird << 24; 658 } 659 ehci->command = temp; 660 661 /* Accept arbitrarily long scatter-gather lists */ 662 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 663 hcd->self.sg_tablesize = ~0; 664 return 0; 665} 666 667/* start HC running; it's halted, ehci_init() has been run (once) */ 668static int ehci_run (struct usb_hcd *hcd) 669{ 670 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 671 int retval; 672 u32 temp; 673 u32 hcc_params; 674 675 hcd->uses_new_polling = 1; 676 677 /* EHCI spec section 4.1 */ 678 /* 679 * TDI driver does the ehci_reset in their reset callback. 680 * Don't reset here, because configuration settings will 681 * vanish. 682 */ 683 if (!ehci_is_TDI(ehci) && (retval = ehci_reset(ehci)) != 0) { 684 ehci_mem_cleanup(ehci); 685 return retval; 686 } 687 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 688 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 689 690 /* 691 * hcc_params controls whether ehci->regs->segment must (!!!) 692 * be used; it constrains QH/ITD/SITD and QTD locations. 693 * pci_pool consistent memory always uses segment zero. 694 * streaming mappings for I/O buffers, like pci_map_single(), 695 * can return segments above 4GB, if the device allows. 696 * 697 * NOTE: the dma mask is visible through dma_supported(), so 698 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 699 * Scsi_Host.highmem_io, and so forth. It's readonly to all 700 * host side drivers though. 701 */ 702 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 703 if (HCC_64BIT_ADDR(hcc_params)) { 704 ehci_writel(ehci, 0, &ehci->regs->segment); 705#if 0 706// this is deeply broken on almost all architectures 707 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) 708 ehci_info(ehci, "enabled 64bit DMA\n"); 709#endif 710 } 711 712 713 // Philips, Intel, and maybe others need CMD_RUN before the 714 // root hub will detect new devices (why?); NEC doesn't 715 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 716 ehci->command |= CMD_RUN; 717 ehci_writel(ehci, ehci->command, &ehci->regs->command); 718 dbg_cmd (ehci, "init", ehci->command); 719 720 /* 721 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 722 * are explicitly handed to companion controller(s), so no TT is 723 * involved with the root hub. (Except where one is integrated, 724 * and there's no companion controller unless maybe for USB OTG.) 725 * 726 * Turning on the CF flag will transfer ownership of all ports 727 * from the companions to the EHCI controller. If any of the 728 * companions are in the middle of a port reset at the time, it 729 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 730 * guarantees that no resets are in progress. After we set CF, 731 * a short delay lets the hardware catch up; new resets shouldn't 732 * be started before the port switching actions could complete. 733 */ 734 down_write(&ehci_cf_port_reset_rwsem); 735 hcd->state = HC_STATE_RUNNING; 736 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 737 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 738 msleep(5); 739 up_write(&ehci_cf_port_reset_rwsem); 740 ehci->last_periodic_enable = ktime_get_real(); 741 742 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); 743 ehci_info (ehci, 744 "USB %x.%x started, EHCI %x.%02x%s\n", 745 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 746 temp >> 8, temp & 0xff, 747 ignore_oc ? ", overcurrent ignored" : ""); 748 749 ehci_writel(ehci, INTR_MASK, 750 &ehci->regs->intr_enable); /* Turn On Interrupts */ 751 752 /* GRR this is run-once init(), being done every time the HC starts. 753 * So long as they're part of class devices, we can't do it init() 754 * since the class device isn't created that early. 755 */ 756 create_debug_files(ehci); 757 create_companion_file(ehci); 758 759 return 0; 760} 761 762/*-------------------------------------------------------------------------*/ 763 764static irqreturn_t ehci_irq (struct usb_hcd *hcd) 765{ 766 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 767 u32 status, masked_status, pcd_status = 0, cmd; 768 int bh; 769 770 spin_lock (&ehci->lock); 771 772 status = ehci_readl(ehci, &ehci->regs->status); 773 774 /* e.g. cardbus physical eject */ 775 if (status == ~(u32) 0) { 776 ehci_dbg (ehci, "device removed\n"); 777 goto dead; 778 } 779 780 masked_status = status & INTR_MASK; 781 if (!masked_status) { /* irq sharing? */ 782 spin_unlock(&ehci->lock); 783 return IRQ_NONE; 784 } 785 786 /* clear (just) interrupts */ 787 ehci_writel(ehci, masked_status, &ehci->regs->status); 788 cmd = ehci_readl(ehci, &ehci->regs->command); 789 bh = 0; 790 791#ifdef VERBOSE_DEBUG 792 /* unrequested/ignored: Frame List Rollover */ 793 dbg_status (ehci, "irq", status); 794#endif 795 796 /* INT, ERR, and IAA interrupt rates can be throttled */ 797 798 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 799 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 800 if (likely ((status & STS_ERR) == 0)) 801 COUNT (ehci->stats.normal); 802 else 803 COUNT (ehci->stats.error); 804 bh = 1; 805 } 806 807 /* complete the unlinking of some qh [4.15.2.3] */ 808 if (status & STS_IAA) { 809 /* guard against (alleged) silicon errata */ 810 if (cmd & CMD_IAAD) { 811 ehci_writel(ehci, cmd & ~CMD_IAAD, 812 &ehci->regs->command); 813 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 814 } 815 if (ehci->reclaim) { 816 COUNT(ehci->stats.reclaim); 817 end_unlink_async(ehci); 818 } else 819 ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); 820 } 821 822 /* remote wakeup [4.3.1] */ 823 if (status & STS_PCD) { 824 unsigned i = HCS_N_PORTS (ehci->hcs_params); 825 u32 ppcd = 0; 826 827 /* kick root hub later */ 828 pcd_status = status; 829 830 /* resume root hub? */ 831 if (!(cmd & CMD_RUN)) 832 usb_hcd_resume_root_hub(hcd); 833 834 /* get per-port change detect bits */ 835 if (ehci->has_ppcd) 836 ppcd = status >> 16; 837 838 while (i--) { 839 int pstatus; 840 841 /* leverage per-port change bits feature */ 842 if (ehci->has_ppcd && !(ppcd & (1 << i))) 843 continue; 844 pstatus = ehci_readl(ehci, 845 &ehci->regs->port_status[i]); 846 847 if (pstatus & PORT_OWNER) 848 continue; 849 if (!(test_bit(i, &ehci->suspended_ports) && 850 ((pstatus & PORT_RESUME) || 851 !(pstatus & PORT_SUSPEND)) && 852 (pstatus & PORT_PE) && 853 ehci->reset_done[i] == 0)) 854 continue; 855 856 /* start 20 msec resume signaling from this port, 857 * and make khubd collect PORT_STAT_C_SUSPEND to 858 * stop that signaling. Use 5 ms extra for safety, 859 * like usb_port_resume() does. 860 */ 861 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); 862 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 863 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 864 } 865 } 866 867 /* PCI errors [4.15.2.4] */ 868 if (unlikely ((status & STS_FATAL) != 0)) { 869 ehci_err(ehci, "fatal error\n"); 870 dbg_cmd(ehci, "fatal", cmd); 871 dbg_status(ehci, "fatal", status); 872 ehci_halt(ehci); 873dead: 874 ehci_reset(ehci); 875 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 876 /* generic layer kills/unlinks all urbs, then 877 * uses ehci_stop to clean up the rest 878 */ 879 bh = 1; 880 } 881 882 if (bh) 883 ehci_work (ehci); 884 spin_unlock (&ehci->lock); 885 if (pcd_status) 886 usb_hcd_poll_rh_status(hcd); 887 return IRQ_HANDLED; 888} 889 890/*-------------------------------------------------------------------------*/ 891 892/* 893 * non-error returns are a promise to giveback() the urb later 894 * we drop ownership so next owner (or urb unlink) can get it 895 * 896 * urb + dev is in hcd.self.controller.urb_list 897 * we're queueing TDs onto software and hardware lists 898 * 899 * hcd-specific init for hcpriv hasn't been done yet 900 * 901 * NOTE: control, bulk, and interrupt share the same code to append TDs 902 * to a (possibly active) QH, and the same QH scanning code. 903 */ 904static int ehci_urb_enqueue ( 905 struct usb_hcd *hcd, 906 struct urb *urb, 907 gfp_t mem_flags 908) { 909 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 910 struct list_head qtd_list; 911 912 INIT_LIST_HEAD (&qtd_list); 913 914 switch (usb_pipetype (urb->pipe)) { 915 case PIPE_CONTROL: 916 /* qh_completions() code doesn't handle all the fault cases 917 * in multi-TD control transfers. Even 1KB is rare anyway. 918 */ 919 if (urb->transfer_buffer_length > (16 * 1024)) 920 return -EMSGSIZE; 921 /* FALLTHROUGH */ 922 /* case PIPE_BULK: */ 923 default: 924 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 925 return -ENOMEM; 926 return submit_async(ehci, urb, &qtd_list, mem_flags); 927 928 case PIPE_INTERRUPT: 929 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 930 return -ENOMEM; 931 return intr_submit(ehci, urb, &qtd_list, mem_flags); 932 933 case PIPE_ISOCHRONOUS: 934 if (urb->dev->speed == USB_SPEED_HIGH) 935 return itd_submit (ehci, urb, mem_flags); 936 else 937 return sitd_submit (ehci, urb, mem_flags); 938 } 939} 940 941static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 942{ 943 /* failfast */ 944 if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) 945 end_unlink_async(ehci); 946 947 /* If the QH isn't linked then there's nothing we can do 948 * unless we were called during a giveback, in which case 949 * qh_completions() has to deal with it. 950 */ 951 if (qh->qh_state != QH_STATE_LINKED) { 952 if (qh->qh_state == QH_STATE_COMPLETING) 953 qh->needs_rescan = 1; 954 return; 955 } 956 957 /* defer till later if busy */ 958 if (ehci->reclaim) { 959 struct ehci_qh *last; 960 961 for (last = ehci->reclaim; 962 last->reclaim; 963 last = last->reclaim) 964 continue; 965 qh->qh_state = QH_STATE_UNLINK_WAIT; 966 last->reclaim = qh; 967 968 /* start IAA cycle */ 969 } else 970 start_unlink_async (ehci, qh); 971} 972 973/* remove from hardware lists 974 * completions normally happen asynchronously 975 */ 976 977static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 978{ 979 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 980 struct ehci_qh *qh; 981 unsigned long flags; 982 int rc; 983 984 spin_lock_irqsave (&ehci->lock, flags); 985 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 986 if (rc) 987 goto done; 988 989 switch (usb_pipetype (urb->pipe)) { 990 // case PIPE_CONTROL: 991 // case PIPE_BULK: 992 default: 993 qh = (struct ehci_qh *) urb->hcpriv; 994 if (!qh) 995 break; 996 switch (qh->qh_state) { 997 case QH_STATE_LINKED: 998 case QH_STATE_COMPLETING: 999 unlink_async(ehci, qh); 1000 break; 1001 case QH_STATE_UNLINK: 1002 case QH_STATE_UNLINK_WAIT: 1003 /* already started */ 1004 break; 1005 case QH_STATE_IDLE: 1006 /* QH might be waiting for a Clear-TT-Buffer */ 1007 qh_completions(ehci, qh); 1008 break; 1009 } 1010 break; 1011 1012 case PIPE_INTERRUPT: 1013 qh = (struct ehci_qh *) urb->hcpriv; 1014 if (!qh) 1015 break; 1016 switch (qh->qh_state) { 1017 case QH_STATE_LINKED: 1018 case QH_STATE_COMPLETING: 1019 intr_deschedule (ehci, qh); 1020 break; 1021 case QH_STATE_IDLE: 1022 qh_completions (ehci, qh); 1023 break; 1024 default: 1025 ehci_dbg (ehci, "bogus qh %p state %d\n", 1026 qh, qh->qh_state); 1027 goto done; 1028 } 1029 break; 1030 1031 case PIPE_ISOCHRONOUS: 1032 // itd or sitd ... 1033 1034 // wait till next completion, do it then. 1035 // completion irqs can wait up to 1024 msec, 1036 break; 1037 } 1038done: 1039 spin_unlock_irqrestore (&ehci->lock, flags); 1040 return rc; 1041} 1042 1043/*-------------------------------------------------------------------------*/ 1044 1045// bulk qh holds the data toggle 1046 1047static void 1048ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1049{ 1050 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1051 unsigned long flags; 1052 struct ehci_qh *qh, *tmp; 1053 1054 /* ASSERT: any requests/urbs are being unlinked */ 1055 /* ASSERT: nobody can be submitting urbs for this any more */ 1056 1057rescan: 1058 spin_lock_irqsave (&ehci->lock, flags); 1059 qh = ep->hcpriv; 1060 if (!qh) 1061 goto done; 1062 1063 /* endpoints can be iso streams. for now, we don't 1064 * accelerate iso completions ... so spin a while. 1065 */ 1066 if (qh->hw == NULL) { 1067 ehci_vdbg (ehci, "iso delay\n"); 1068 goto idle_timeout; 1069 } 1070 1071 if (!HC_IS_RUNNING (hcd->state)) 1072 qh->qh_state = QH_STATE_IDLE; 1073 switch (qh->qh_state) { 1074 case QH_STATE_LINKED: 1075 case QH_STATE_COMPLETING: 1076 for (tmp = ehci->async->qh_next.qh; 1077 tmp && tmp != qh; 1078 tmp = tmp->qh_next.qh) 1079 continue; 1080 /* periodic qh self-unlinks on empty, and a COMPLETING qh 1081 * may already be unlinked. 1082 */ 1083 if (tmp) 1084 unlink_async(ehci, qh); 1085 /* FALL THROUGH */ 1086 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1087 case QH_STATE_UNLINK_WAIT: 1088idle_timeout: 1089 spin_unlock_irqrestore (&ehci->lock, flags); 1090 schedule_timeout_uninterruptible(1); 1091 goto rescan; 1092 case QH_STATE_IDLE: /* fully unlinked */ 1093 if (qh->clearing_tt) 1094 goto idle_timeout; 1095 if (list_empty (&qh->qtd_list)) { 1096 qh_put (qh); 1097 break; 1098 } 1099 /* else FALL THROUGH */ 1100 default: 1101 /* caller was supposed to have unlinked any requests; 1102 * that's not our job. just leak this memory. 1103 */ 1104 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1105 qh, ep->desc.bEndpointAddress, qh->qh_state, 1106 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1107 break; 1108 } 1109 ep->hcpriv = NULL; 1110done: 1111 spin_unlock_irqrestore (&ehci->lock, flags); 1112} 1113 1114static void 1115ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1116{ 1117 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1118 struct ehci_qh *qh; 1119 int eptype = usb_endpoint_type(&ep->desc); 1120 int epnum = usb_endpoint_num(&ep->desc); 1121 int is_out = usb_endpoint_dir_out(&ep->desc); 1122 unsigned long flags; 1123 1124 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1125 return; 1126 1127 spin_lock_irqsave(&ehci->lock, flags); 1128 qh = ep->hcpriv; 1129 1130 /* For Bulk and Interrupt endpoints we maintain the toggle state 1131 * in the hardware; the toggle bits in udev aren't used at all. 1132 * When an endpoint is reset by usb_clear_halt() we must reset 1133 * the toggle bit in the QH. 1134 */ 1135 if (qh) { 1136 usb_settoggle(qh->dev, epnum, is_out, 0); 1137 if (!list_empty(&qh->qtd_list)) { 1138 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1139 } else if (qh->qh_state == QH_STATE_LINKED || 1140 qh->qh_state == QH_STATE_COMPLETING) { 1141 1142 /* The toggle value in the QH can't be updated 1143 * while the QH is active. Unlink it now; 1144 * re-linking will call qh_refresh(). 1145 */ 1146 if (eptype == USB_ENDPOINT_XFER_BULK) 1147 unlink_async(ehci, qh); 1148 else 1149 intr_deschedule(ehci, qh); 1150 } 1151 } 1152 spin_unlock_irqrestore(&ehci->lock, flags); 1153} 1154 1155static int ehci_get_frame (struct usb_hcd *hcd) 1156{ 1157 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1158 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % 1159 ehci->periodic_size; 1160} 1161 1162/*-------------------------------------------------------------------------*/ 1163 1164MODULE_DESCRIPTION(DRIVER_DESC); 1165MODULE_AUTHOR (DRIVER_AUTHOR); 1166MODULE_LICENSE ("GPL"); 1167 1168#ifdef CONFIG_PCI 1169#include "ehci-pci.c" 1170#define PCI_DRIVER ehci_pci_driver 1171#endif 1172 1173#ifdef CONFIG_USB_EHCI_FSL 1174#include "ehci-fsl.c" 1175#define PLATFORM_DRIVER ehci_fsl_driver 1176#endif 1177 1178#ifdef CONFIG_USB_EHCI_MXC 1179#include "ehci-mxc.c" 1180#define PLATFORM_DRIVER ehci_mxc_driver 1181#endif 1182 1183#ifdef CONFIG_USB_EHCI_SH 1184#include "ehci-sh.c" 1185#define PLATFORM_DRIVER ehci_hcd_sh_driver 1186#endif 1187 1188#ifdef CONFIG_SOC_AU1200 1189#include "ehci-au1xxx.c" 1190#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 1191#endif 1192 1193#ifdef CONFIG_USB_EHCI_HCD_OMAP 1194#include "ehci-omap.c" 1195#define PLATFORM_DRIVER ehci_hcd_omap_driver 1196#endif 1197 1198#ifdef CONFIG_PPC_PS3 1199#include "ehci-ps3.c" 1200#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1201#endif 1202 1203#ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1204#include "ehci-ppc-of.c" 1205#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1206#endif 1207 1208#ifdef CONFIG_XPS_USB_HCD_XILINX 1209#include "ehci-xilinx-of.c" 1210#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1211#endif 1212 1213#ifdef CONFIG_PLAT_ORION 1214#include "ehci-orion.c" 1215#define PLATFORM_DRIVER ehci_orion_driver 1216#endif 1217 1218#ifdef CONFIG_ARCH_IXP4XX 1219#include "ehci-ixp4xx.c" 1220#define PLATFORM_DRIVER ixp4xx_ehci_driver 1221#endif 1222 1223#ifdef CONFIG_USB_W90X900_EHCI 1224#include "ehci-w90x900.c" 1225#define PLATFORM_DRIVER ehci_hcd_w90x900_driver 1226#endif 1227 1228#ifdef CONFIG_ARCH_AT91 1229#include "ehci-atmel.c" 1230#define PLATFORM_DRIVER ehci_atmel_driver 1231#endif 1232 1233#ifdef CONFIG_USB_OCTEON_EHCI 1234#include "ehci-octeon.c" 1235#define PLATFORM_DRIVER ehci_octeon_driver 1236#endif 1237 1238#ifdef CONFIG_USB_CNS3XXX_EHCI 1239#include "ehci-cns3xxx.c" 1240#define PLATFORM_DRIVER cns3xxx_ehci_driver 1241#endif 1242 1243#ifdef CONFIG_ARCH_VT8500 1244#include "ehci-vt8500.c" 1245#define PLATFORM_DRIVER vt8500_ehci_driver 1246#endif 1247 1248#ifdef CONFIG_PLAT_SPEAR 1249#include "ehci-spear.c" 1250#define PLATFORM_DRIVER spear_ehci_hcd_driver 1251#endif 1252 1253#ifdef CONFIG_USB_EHCI_MSM 1254#include "ehci-msm.c" 1255#define PLATFORM_DRIVER ehci_msm_driver 1256#endif 1257 1258#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP 1259#include "ehci-pmcmsp.c" 1260#define PLATFORM_DRIVER ehci_hcd_msp_driver 1261#endif 1262 1263#ifdef CONFIG_USB_EHCI_TEGRA 1264#include "ehci-tegra.c" 1265#define PLATFORM_DRIVER tegra_ehci_driver 1266#endif 1267 1268#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1269 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1270 !defined(XILINX_OF_PLATFORM_DRIVER) 1271#error "missing bus glue for ehci-hcd" 1272#endif 1273 1274static int __init ehci_hcd_init(void) 1275{ 1276 int retval = 0; 1277 1278 if (usb_disabled()) 1279 return -ENODEV; 1280 1281 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1282 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1283 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1284 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1285 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1286 " before uhci_hcd and ohci_hcd, not after\n"); 1287 1288 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1289 hcd_name, 1290 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1291 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1292 1293#ifdef DEBUG 1294 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1295 if (!ehci_debug_root) { 1296 retval = -ENOENT; 1297 goto err_debug; 1298 } 1299#endif 1300 1301#ifdef PLATFORM_DRIVER 1302 retval = platform_driver_register(&PLATFORM_DRIVER); 1303 if (retval < 0) 1304 goto clean0; 1305#endif 1306 1307#ifdef PCI_DRIVER 1308 retval = pci_register_driver(&PCI_DRIVER); 1309 if (retval < 0) 1310 goto clean1; 1311#endif 1312 1313#ifdef PS3_SYSTEM_BUS_DRIVER 1314 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1315 if (retval < 0) 1316 goto clean2; 1317#endif 1318 1319#ifdef OF_PLATFORM_DRIVER 1320 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); 1321 if (retval < 0) 1322 goto clean3; 1323#endif 1324 1325#ifdef XILINX_OF_PLATFORM_DRIVER 1326 retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER); 1327 if (retval < 0) 1328 goto clean4; 1329#endif 1330 return retval; 1331 1332#ifdef XILINX_OF_PLATFORM_DRIVER 1333 /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */ 1334clean4: 1335#endif 1336#ifdef OF_PLATFORM_DRIVER 1337 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1338clean3: 1339#endif 1340#ifdef PS3_SYSTEM_BUS_DRIVER 1341 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1342clean2: 1343#endif 1344#ifdef PCI_DRIVER 1345 pci_unregister_driver(&PCI_DRIVER); 1346clean1: 1347#endif 1348#ifdef PLATFORM_DRIVER 1349 platform_driver_unregister(&PLATFORM_DRIVER); 1350clean0: 1351#endif 1352#ifdef DEBUG 1353 debugfs_remove(ehci_debug_root); 1354 ehci_debug_root = NULL; 1355err_debug: 1356#endif 1357 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1358 return retval; 1359} 1360module_init(ehci_hcd_init); 1361 1362static void __exit ehci_hcd_cleanup(void) 1363{ 1364#ifdef XILINX_OF_PLATFORM_DRIVER 1365 of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); 1366#endif 1367#ifdef OF_PLATFORM_DRIVER 1368 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1369#endif 1370#ifdef PLATFORM_DRIVER 1371 platform_driver_unregister(&PLATFORM_DRIVER); 1372#endif 1373#ifdef PCI_DRIVER 1374 pci_unregister_driver(&PCI_DRIVER); 1375#endif 1376#ifdef PS3_SYSTEM_BUS_DRIVER 1377 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1378#endif 1379#ifdef DEBUG 1380 debugfs_remove(ehci_debug_root); 1381#endif 1382 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1383} 1384module_exit(ehci_hcd_cleanup); 1385 1386