ehci-hcd.c revision 7d12e780e003f93433d49ce78cfedf4b4c52adc5
1/* 2 * Copyright (c) 2000-2004 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/dmapool.h> 22#include <linux/kernel.h> 23#include <linux/delay.h> 24#include <linux/ioport.h> 25#include <linux/sched.h> 26#include <linux/slab.h> 27#include <linux/smp_lock.h> 28#include <linux/errno.h> 29#include <linux/init.h> 30#include <linux/timer.h> 31#include <linux/list.h> 32#include <linux/interrupt.h> 33#include <linux/reboot.h> 34#include <linux/usb.h> 35#include <linux/moduleparam.h> 36#include <linux/dma-mapping.h> 37 38#include "../core/hcd.h" 39 40#include <asm/byteorder.h> 41#include <asm/io.h> 42#include <asm/irq.h> 43#include <asm/system.h> 44#include <asm/unaligned.h> 45 46 47/*-------------------------------------------------------------------------*/ 48 49/* 50 * EHCI hc_driver implementation ... experimental, incomplete. 51 * Based on the final 1.0 register interface specification. 52 * 53 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 54 * First was PCMCIA, like ISA; then CardBus, which is PCI. 55 * Next comes "CardBay", using USB 2.0 signals. 56 * 57 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 58 * Special thanks to Intel and VIA for providing host controllers to 59 * test this driver on, and Cypress (including In-System Design) for 60 * providing early devices for those host controllers to talk to! 61 * 62 * HISTORY: 63 * 64 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db) 65 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net) 66 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka, 67 * <sojkam@centrum.cz>, updates by DB). 68 * 69 * 2002-11-29 Correct handling for hw async_next register. 70 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared; 71 * only scheduling is different, no arbitrary limitations. 72 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support, 73 * clean up HC run state handshaking. 74 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts 75 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other 76 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM. 77 * 2002-05-07 Some error path cleanups to report better errors; wmb(); 78 * use non-CVS version id; better iso bandwidth claim. 79 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on 80 * errors in submit path. Bugfixes to interrupt scheduling/processing. 81 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift 82 * more checking to generic hcd framework (db). Make it work with 83 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt). 84 * 2002-01-14 Minor cleanup; version synch. 85 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers. 86 * 2002-01-04 Control/Bulk queuing behaves. 87 * 88 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel. 89 * 2001-June Works with usb-storage and NEC EHCI on 2.4 90 */ 91 92#define DRIVER_VERSION "10 Dec 2004" 93#define DRIVER_AUTHOR "David Brownell" 94#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 95 96static const char hcd_name [] = "ehci_hcd"; 97 98 99#undef EHCI_VERBOSE_DEBUG 100#undef EHCI_URB_TRACE 101 102#ifdef DEBUG 103#define EHCI_STATS 104#endif 105 106/* magic numbers that can affect system performance */ 107#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 108#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 109#define EHCI_TUNE_RL_TT 0 110#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 111#define EHCI_TUNE_MULT_TT 1 112#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 113 114#define EHCI_IAA_MSECS 10 /* arbitrary */ 115#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 116#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 117#define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */ 118 119/* Initial IRQ latency: faster than hw default */ 120static int log2_irq_thresh = 0; // 0 to 6 121module_param (log2_irq_thresh, int, S_IRUGO); 122MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 123 124/* initial park setting: slower than hw default */ 125static unsigned park = 0; 126module_param (park, uint, S_IRUGO); 127MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 128 129#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 130 131/*-------------------------------------------------------------------------*/ 132 133#include "ehci.h" 134#include "ehci-dbg.c" 135 136/*-------------------------------------------------------------------------*/ 137 138/* 139 * handshake - spin reading hc until handshake completes or fails 140 * @ptr: address of hc register to be read 141 * @mask: bits to look at in result of read 142 * @done: value of those bits when handshake succeeds 143 * @usec: timeout in microseconds 144 * 145 * Returns negative errno, or zero on success 146 * 147 * Success happens when the "mask" bits have the specified value (hardware 148 * handshake done). There are two failure modes: "usec" have passed (major 149 * hardware flakeout), or the register reads as all-ones (hardware removed). 150 * 151 * That last failure should_only happen in cases like physical cardbus eject 152 * before driver shutdown. But it also seems to be caused by bugs in cardbus 153 * bridge shutdown: shutting down the bridge before the devices using it. 154 */ 155static int handshake (void __iomem *ptr, u32 mask, u32 done, int usec) 156{ 157 u32 result; 158 159 do { 160 result = readl (ptr); 161 if (result == ~(u32)0) /* card removed */ 162 return -ENODEV; 163 result &= mask; 164 if (result == done) 165 return 0; 166 udelay (1); 167 usec--; 168 } while (usec > 0); 169 return -ETIMEDOUT; 170} 171 172/* force HC to halt state from unknown (EHCI spec section 2.3) */ 173static int ehci_halt (struct ehci_hcd *ehci) 174{ 175 u32 temp = readl (&ehci->regs->status); 176 177 /* disable any irqs left enabled by previous code */ 178 writel (0, &ehci->regs->intr_enable); 179 180 if ((temp & STS_HALT) != 0) 181 return 0; 182 183 temp = readl (&ehci->regs->command); 184 temp &= ~CMD_RUN; 185 writel (temp, &ehci->regs->command); 186 return handshake (&ehci->regs->status, STS_HALT, STS_HALT, 16 * 125); 187} 188 189/* put TDI/ARC silicon into EHCI mode */ 190static void tdi_reset (struct ehci_hcd *ehci) 191{ 192 u32 __iomem *reg_ptr; 193 u32 tmp; 194 195 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + 0x68); 196 tmp = readl (reg_ptr); 197 tmp |= 0x3; 198 writel (tmp, reg_ptr); 199} 200 201/* reset a non-running (STS_HALT == 1) controller */ 202static int ehci_reset (struct ehci_hcd *ehci) 203{ 204 int retval; 205 u32 command = readl (&ehci->regs->command); 206 207 command |= CMD_RESET; 208 dbg_cmd (ehci, "reset", command); 209 writel (command, &ehci->regs->command); 210 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 211 ehci->next_statechange = jiffies; 212 retval = handshake (&ehci->regs->command, CMD_RESET, 0, 250 * 1000); 213 214 if (retval) 215 return retval; 216 217 if (ehci_is_TDI(ehci)) 218 tdi_reset (ehci); 219 220 return retval; 221} 222 223/* idle the controller (from running) */ 224static void ehci_quiesce (struct ehci_hcd *ehci) 225{ 226 u32 temp; 227 228#ifdef DEBUG 229 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) 230 BUG (); 231#endif 232 233 /* wait for any schedule enables/disables to take effect */ 234 temp = readl (&ehci->regs->command) << 10; 235 temp &= STS_ASS | STS_PSS; 236 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS, 237 temp, 16 * 125) != 0) { 238 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 239 return; 240 } 241 242 /* then disable anything that's still active */ 243 temp = readl (&ehci->regs->command); 244 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 245 writel (temp, &ehci->regs->command); 246 247 /* hardware can take 16 microframes to turn off ... */ 248 if (handshake (&ehci->regs->status, STS_ASS | STS_PSS, 249 0, 16 * 125) != 0) { 250 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 251 return; 252 } 253} 254 255/*-------------------------------------------------------------------------*/ 256 257static void end_unlink_async (struct ehci_hcd *ehci); 258static void ehci_work(struct ehci_hcd *ehci); 259 260#include "ehci-hub.c" 261#include "ehci-mem.c" 262#include "ehci-q.c" 263#include "ehci-sched.c" 264 265/*-------------------------------------------------------------------------*/ 266 267static void ehci_iaa_watchdog (unsigned long param) 268{ 269 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 270 unsigned long flags; 271 u32 status; 272 273 spin_lock_irqsave (&ehci->lock, flags); 274 WARN_ON(!ehci->reclaim); 275 276 /* lost IAA irqs wedge things badly; seen first with a vt8235 */ 277 if (ehci->reclaim) { 278 status = readl (&ehci->regs->status); 279 if (status & STS_IAA) { 280 ehci_vdbg (ehci, "lost IAA\n"); 281 COUNT (ehci->stats.lost_iaa); 282 writel (STS_IAA, &ehci->regs->status); 283 end_unlink_async (ehci); 284 } 285 } 286 287 spin_unlock_irqrestore (&ehci->lock, flags); 288} 289 290static void ehci_watchdog (unsigned long param) 291{ 292 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 293 unsigned long flags; 294 295 spin_lock_irqsave (&ehci->lock, flags); 296 297 /* stop async processing after it's idled a bit */ 298 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 299 start_unlink_async (ehci, ehci->async); 300 301 /* ehci could run by timer, without IRQs ... */ 302 ehci_work (ehci); 303 304 spin_unlock_irqrestore (&ehci->lock, flags); 305} 306 307/* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 308 * This forcibly disables dma and IRQs, helping kexec and other cases 309 * where the next system software may expect clean state. 310 */ 311static void 312ehci_shutdown (struct usb_hcd *hcd) 313{ 314 struct ehci_hcd *ehci; 315 316 ehci = hcd_to_ehci (hcd); 317 (void) ehci_halt (ehci); 318 319 /* make BIOS/etc use companion controller during reboot */ 320 writel (0, &ehci->regs->configured_flag); 321} 322 323static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 324{ 325 unsigned port; 326 327 if (!HCS_PPC (ehci->hcs_params)) 328 return; 329 330 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 331 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 332 (void) ehci_hub_control(ehci_to_hcd(ehci), 333 is_on ? SetPortFeature : ClearPortFeature, 334 USB_PORT_FEAT_POWER, 335 port--, NULL, 0); 336 msleep(20); 337} 338 339/*-------------------------------------------------------------------------*/ 340 341/* 342 * ehci_work is called from some interrupts, timers, and so on. 343 * it calls driver completion functions, after dropping ehci->lock. 344 */ 345static void ehci_work (struct ehci_hcd *ehci) 346{ 347 timer_action_done (ehci, TIMER_IO_WATCHDOG); 348 349 /* another CPU may drop ehci->lock during a schedule scan while 350 * it reports urb completions. this flag guards against bogus 351 * attempts at re-entrant schedule scanning. 352 */ 353 if (ehci->scanning) 354 return; 355 ehci->scanning = 1; 356 scan_async (ehci); 357 if (ehci->next_uframe != -1) 358 scan_periodic (ehci); 359 ehci->scanning = 0; 360 361 /* the IO watchdog guards against hardware or driver bugs that 362 * misplace IRQs, and should let us run completely without IRQs. 363 * such lossage has been observed on both VT6202 and VT8235. 364 */ 365 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && 366 (ehci->async->qh_next.ptr != NULL || 367 ehci->periodic_sched != 0)) 368 timer_action (ehci, TIMER_IO_WATCHDOG); 369} 370 371static void ehci_stop (struct usb_hcd *hcd) 372{ 373 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 374 375 ehci_dbg (ehci, "stop\n"); 376 377 /* Turn off port power on all root hub ports. */ 378 ehci_port_power (ehci, 0); 379 380 /* no more interrupts ... */ 381 del_timer_sync (&ehci->watchdog); 382 del_timer_sync (&ehci->iaa_watchdog); 383 384 spin_lock_irq(&ehci->lock); 385 if (HC_IS_RUNNING (hcd->state)) 386 ehci_quiesce (ehci); 387 388 ehci_reset (ehci); 389 writel (0, &ehci->regs->intr_enable); 390 spin_unlock_irq(&ehci->lock); 391 392 /* let companion controllers work when we aren't */ 393 writel (0, &ehci->regs->configured_flag); 394 395 remove_debug_files (ehci); 396 397 /* root hub is shut down separately (first, when possible) */ 398 spin_lock_irq (&ehci->lock); 399 if (ehci->async) 400 ehci_work (ehci); 401 spin_unlock_irq (&ehci->lock); 402 ehci_mem_cleanup (ehci); 403 404#ifdef EHCI_STATS 405 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 406 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 407 ehci->stats.lost_iaa); 408 ehci_dbg (ehci, "complete %ld unlink %ld\n", 409 ehci->stats.complete, ehci->stats.unlink); 410#endif 411 412 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status)); 413} 414 415/* one-time init, only for memory state */ 416static int ehci_init(struct usb_hcd *hcd) 417{ 418 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 419 u32 temp; 420 int retval; 421 u32 hcc_params; 422 423 spin_lock_init(&ehci->lock); 424 425 init_timer(&ehci->watchdog); 426 ehci->watchdog.function = ehci_watchdog; 427 ehci->watchdog.data = (unsigned long) ehci; 428 429 init_timer(&ehci->iaa_watchdog); 430 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 431 ehci->iaa_watchdog.data = (unsigned long) ehci; 432 433 /* 434 * hw default: 1K periodic list heads, one per frame. 435 * periodic_size can shrink by USBCMD update if hcc_params allows. 436 */ 437 ehci->periodic_size = DEFAULT_I_TDPS; 438 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 439 return retval; 440 441 /* controllers may cache some of the periodic schedule ... */ 442 hcc_params = readl(&ehci->caps->hcc_params); 443 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 444 ehci->i_thresh = 8; 445 else // N microframes cached 446 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 447 448 ehci->reclaim = NULL; 449 ehci->next_uframe = -1; 450 451 /* 452 * dedicate a qh for the async ring head, since we couldn't unlink 453 * a 'real' qh without stopping the async schedule [4.8]. use it 454 * as the 'reclamation list head' too. 455 * its dummy is used in hw_alt_next of many tds, to prevent the qh 456 * from automatically advancing to the next td after short reads. 457 */ 458 ehci->async->qh_next.qh = NULL; 459 ehci->async->hw_next = QH_NEXT(ehci->async->qh_dma); 460 ehci->async->hw_info1 = cpu_to_le32(QH_HEAD); 461 ehci->async->hw_token = cpu_to_le32(QTD_STS_HALT); 462 ehci->async->hw_qtd_next = EHCI_LIST_END; 463 ehci->async->qh_state = QH_STATE_LINKED; 464 ehci->async->hw_alt_next = QTD_NEXT(ehci->async->dummy->qtd_dma); 465 466 /* clear interrupt enables, set irq latency */ 467 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 468 log2_irq_thresh = 0; 469 temp = 1 << (16 + log2_irq_thresh); 470 if (HCC_CANPARK(hcc_params)) { 471 /* HW default park == 3, on hardware that supports it (like 472 * NVidia and ALI silicon), maximizes throughput on the async 473 * schedule by avoiding QH fetches between transfers. 474 * 475 * With fast usb storage devices and NForce2, "park" seems to 476 * make problems: throughput reduction (!), data errors... 477 */ 478 if (park) { 479 park = min(park, (unsigned) 3); 480 temp |= CMD_PARK; 481 temp |= park << 8; 482 } 483 ehci_dbg(ehci, "park %d\n", park); 484 } 485 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 486 /* periodic schedule size can be smaller than default */ 487 temp &= ~(3 << 2); 488 temp |= (EHCI_TUNE_FLS << 2); 489 switch (EHCI_TUNE_FLS) { 490 case 0: ehci->periodic_size = 1024; break; 491 case 1: ehci->periodic_size = 512; break; 492 case 2: ehci->periodic_size = 256; break; 493 default: BUG(); 494 } 495 } 496 ehci->command = temp; 497 498 return 0; 499} 500 501/* start HC running; it's halted, ehci_init() has been run (once) */ 502static int ehci_run (struct usb_hcd *hcd) 503{ 504 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 505 int retval; 506 u32 temp; 507 u32 hcc_params; 508 509 /* EHCI spec section 4.1 */ 510 if ((retval = ehci_reset(ehci)) != 0) { 511 ehci_mem_cleanup(ehci); 512 return retval; 513 } 514 writel(ehci->periodic_dma, &ehci->regs->frame_list); 515 writel((u32)ehci->async->qh_dma, &ehci->regs->async_next); 516 517 /* 518 * hcc_params controls whether ehci->regs->segment must (!!!) 519 * be used; it constrains QH/ITD/SITD and QTD locations. 520 * pci_pool consistent memory always uses segment zero. 521 * streaming mappings for I/O buffers, like pci_map_single(), 522 * can return segments above 4GB, if the device allows. 523 * 524 * NOTE: the dma mask is visible through dma_supported(), so 525 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 526 * Scsi_Host.highmem_io, and so forth. It's readonly to all 527 * host side drivers though. 528 */ 529 hcc_params = readl(&ehci->caps->hcc_params); 530 if (HCC_64BIT_ADDR(hcc_params)) { 531 writel(0, &ehci->regs->segment); 532#if 0 533// this is deeply broken on almost all architectures 534 if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK)) 535 ehci_info(ehci, "enabled 64bit DMA\n"); 536#endif 537 } 538 539 540 // Philips, Intel, and maybe others need CMD_RUN before the 541 // root hub will detect new devices (why?); NEC doesn't 542 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 543 ehci->command |= CMD_RUN; 544 writel (ehci->command, &ehci->regs->command); 545 dbg_cmd (ehci, "init", ehci->command); 546 547 /* 548 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 549 * are explicitly handed to companion controller(s), so no TT is 550 * involved with the root hub. (Except where one is integrated, 551 * and there's no companion controller unless maybe for USB OTG.) 552 */ 553 hcd->state = HC_STATE_RUNNING; 554 writel (FLAG_CF, &ehci->regs->configured_flag); 555 readl (&ehci->regs->command); /* unblock posted writes */ 556 557 temp = HC_VERSION(readl (&ehci->caps->hc_capbase)); 558 ehci_info (ehci, 559 "USB %x.%x started, EHCI %x.%02x, driver %s\n", 560 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 561 temp >> 8, temp & 0xff, DRIVER_VERSION); 562 563 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */ 564 565 /* GRR this is run-once init(), being done every time the HC starts. 566 * So long as they're part of class devices, we can't do it init() 567 * since the class device isn't created that early. 568 */ 569 create_debug_files(ehci); 570 571 return 0; 572} 573 574/*-------------------------------------------------------------------------*/ 575 576static irqreturn_t ehci_irq (struct usb_hcd *hcd) 577{ 578 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 579 u32 status; 580 int bh; 581 582 spin_lock (&ehci->lock); 583 584 status = readl (&ehci->regs->status); 585 586 /* e.g. cardbus physical eject */ 587 if (status == ~(u32) 0) { 588 ehci_dbg (ehci, "device removed\n"); 589 goto dead; 590 } 591 592 status &= INTR_MASK; 593 if (!status) { /* irq sharing? */ 594 spin_unlock(&ehci->lock); 595 return IRQ_NONE; 596 } 597 598 /* clear (just) interrupts */ 599 writel (status, &ehci->regs->status); 600 readl (&ehci->regs->command); /* unblock posted write */ 601 bh = 0; 602 603#ifdef EHCI_VERBOSE_DEBUG 604 /* unrequested/ignored: Frame List Rollover */ 605 dbg_status (ehci, "irq", status); 606#endif 607 608 /* INT, ERR, and IAA interrupt rates can be throttled */ 609 610 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 611 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 612 if (likely ((status & STS_ERR) == 0)) 613 COUNT (ehci->stats.normal); 614 else 615 COUNT (ehci->stats.error); 616 bh = 1; 617 } 618 619 /* complete the unlinking of some qh [4.15.2.3] */ 620 if (status & STS_IAA) { 621 COUNT (ehci->stats.reclaim); 622 end_unlink_async (ehci); 623 bh = 1; 624 } 625 626 /* remote wakeup [4.3.1] */ 627 if (status & STS_PCD) { 628 unsigned i = HCS_N_PORTS (ehci->hcs_params); 629 630 /* resume root hub? */ 631 status = readl (&ehci->regs->command); 632 if (!(status & CMD_RUN)) 633 writel (status | CMD_RUN, &ehci->regs->command); 634 635 while (i--) { 636 int pstatus = readl (&ehci->regs->port_status [i]); 637 638 if (pstatus & PORT_OWNER) 639 continue; 640 if (!(pstatus & PORT_RESUME) 641 || ehci->reset_done [i] != 0) 642 continue; 643 644 /* start 20 msec resume signaling from this port, 645 * and make khubd collect PORT_STAT_C_SUSPEND to 646 * stop that signaling. 647 */ 648 ehci->reset_done [i] = jiffies + msecs_to_jiffies (20); 649 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 650 usb_hcd_resume_root_hub(hcd); 651 } 652 } 653 654 /* PCI errors [4.15.2.4] */ 655 if (unlikely ((status & STS_FATAL) != 0)) { 656 /* bogus "fatal" IRQs appear on some chips... why? */ 657 status = readl (&ehci->regs->status); 658 dbg_cmd (ehci, "fatal", readl (&ehci->regs->command)); 659 dbg_status (ehci, "fatal", status); 660 if (status & STS_HALT) { 661 ehci_err (ehci, "fatal error\n"); 662dead: 663 ehci_reset (ehci); 664 writel (0, &ehci->regs->configured_flag); 665 /* generic layer kills/unlinks all urbs, then 666 * uses ehci_stop to clean up the rest 667 */ 668 bh = 1; 669 } 670 } 671 672 if (bh) 673 ehci_work (ehci); 674 spin_unlock (&ehci->lock); 675 return IRQ_HANDLED; 676} 677 678/*-------------------------------------------------------------------------*/ 679 680/* 681 * non-error returns are a promise to giveback() the urb later 682 * we drop ownership so next owner (or urb unlink) can get it 683 * 684 * urb + dev is in hcd.self.controller.urb_list 685 * we're queueing TDs onto software and hardware lists 686 * 687 * hcd-specific init for hcpriv hasn't been done yet 688 * 689 * NOTE: control, bulk, and interrupt share the same code to append TDs 690 * to a (possibly active) QH, and the same QH scanning code. 691 */ 692static int ehci_urb_enqueue ( 693 struct usb_hcd *hcd, 694 struct usb_host_endpoint *ep, 695 struct urb *urb, 696 gfp_t mem_flags 697) { 698 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 699 struct list_head qtd_list; 700 701 INIT_LIST_HEAD (&qtd_list); 702 703 switch (usb_pipetype (urb->pipe)) { 704 // case PIPE_CONTROL: 705 // case PIPE_BULK: 706 default: 707 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 708 return -ENOMEM; 709 return submit_async (ehci, ep, urb, &qtd_list, mem_flags); 710 711 case PIPE_INTERRUPT: 712 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 713 return -ENOMEM; 714 return intr_submit (ehci, ep, urb, &qtd_list, mem_flags); 715 716 case PIPE_ISOCHRONOUS: 717 if (urb->dev->speed == USB_SPEED_HIGH) 718 return itd_submit (ehci, urb, mem_flags); 719 else 720 return sitd_submit (ehci, urb, mem_flags); 721 } 722} 723 724static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 725{ 726 // BUG_ON(qh->qh_state != QH_STATE_LINKED); 727 728 /* failfast */ 729 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) 730 end_unlink_async (ehci); 731 732 /* defer till later if busy */ 733 else if (ehci->reclaim) { 734 struct ehci_qh *last; 735 736 for (last = ehci->reclaim; 737 last->reclaim; 738 last = last->reclaim) 739 continue; 740 qh->qh_state = QH_STATE_UNLINK_WAIT; 741 last->reclaim = qh; 742 743 /* start IAA cycle */ 744 } else 745 start_unlink_async (ehci, qh); 746} 747 748/* remove from hardware lists 749 * completions normally happen asynchronously 750 */ 751 752static int ehci_urb_dequeue (struct usb_hcd *hcd, struct urb *urb) 753{ 754 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 755 struct ehci_qh *qh; 756 unsigned long flags; 757 758 spin_lock_irqsave (&ehci->lock, flags); 759 switch (usb_pipetype (urb->pipe)) { 760 // case PIPE_CONTROL: 761 // case PIPE_BULK: 762 default: 763 qh = (struct ehci_qh *) urb->hcpriv; 764 if (!qh) 765 break; 766 switch (qh->qh_state) { 767 case QH_STATE_LINKED: 768 case QH_STATE_COMPLETING: 769 unlink_async (ehci, qh); 770 break; 771 case QH_STATE_UNLINK: 772 case QH_STATE_UNLINK_WAIT: 773 /* already started */ 774 break; 775 case QH_STATE_IDLE: 776 WARN_ON(1); 777 break; 778 } 779 break; 780 781 case PIPE_INTERRUPT: 782 qh = (struct ehci_qh *) urb->hcpriv; 783 if (!qh) 784 break; 785 switch (qh->qh_state) { 786 case QH_STATE_LINKED: 787 intr_deschedule (ehci, qh); 788 /* FALL THROUGH */ 789 case QH_STATE_IDLE: 790 qh_completions (ehci, qh); 791 break; 792 default: 793 ehci_dbg (ehci, "bogus qh %p state %d\n", 794 qh, qh->qh_state); 795 goto done; 796 } 797 798 /* reschedule QH iff another request is queued */ 799 if (!list_empty (&qh->qtd_list) 800 && HC_IS_RUNNING (hcd->state)) { 801 int status; 802 803 status = qh_schedule (ehci, qh); 804 spin_unlock_irqrestore (&ehci->lock, flags); 805 806 if (status != 0) { 807 // shouldn't happen often, but ... 808 // FIXME kill those tds' urbs 809 err ("can't reschedule qh %p, err %d", 810 qh, status); 811 } 812 return status; 813 } 814 break; 815 816 case PIPE_ISOCHRONOUS: 817 // itd or sitd ... 818 819 // wait till next completion, do it then. 820 // completion irqs can wait up to 1024 msec, 821 break; 822 } 823done: 824 spin_unlock_irqrestore (&ehci->lock, flags); 825 return 0; 826} 827 828/*-------------------------------------------------------------------------*/ 829 830// bulk qh holds the data toggle 831 832static void 833ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 834{ 835 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 836 unsigned long flags; 837 struct ehci_qh *qh, *tmp; 838 839 /* ASSERT: any requests/urbs are being unlinked */ 840 /* ASSERT: nobody can be submitting urbs for this any more */ 841 842rescan: 843 spin_lock_irqsave (&ehci->lock, flags); 844 qh = ep->hcpriv; 845 if (!qh) 846 goto done; 847 848 /* endpoints can be iso streams. for now, we don't 849 * accelerate iso completions ... so spin a while. 850 */ 851 if (qh->hw_info1 == 0) { 852 ehci_vdbg (ehci, "iso delay\n"); 853 goto idle_timeout; 854 } 855 856 if (!HC_IS_RUNNING (hcd->state)) 857 qh->qh_state = QH_STATE_IDLE; 858 switch (qh->qh_state) { 859 case QH_STATE_LINKED: 860 for (tmp = ehci->async->qh_next.qh; 861 tmp && tmp != qh; 862 tmp = tmp->qh_next.qh) 863 continue; 864 /* periodic qh self-unlinks on empty */ 865 if (!tmp) 866 goto nogood; 867 unlink_async (ehci, qh); 868 /* FALL THROUGH */ 869 case QH_STATE_UNLINK: /* wait for hw to finish? */ 870 case QH_STATE_UNLINK_WAIT: 871idle_timeout: 872 spin_unlock_irqrestore (&ehci->lock, flags); 873 schedule_timeout_uninterruptible(1); 874 goto rescan; 875 case QH_STATE_IDLE: /* fully unlinked */ 876 if (list_empty (&qh->qtd_list)) { 877 qh_put (qh); 878 break; 879 } 880 /* else FALL THROUGH */ 881 default: 882nogood: 883 /* caller was supposed to have unlinked any requests; 884 * that's not our job. just leak this memory. 885 */ 886 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 887 qh, ep->desc.bEndpointAddress, qh->qh_state, 888 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 889 break; 890 } 891 ep->hcpriv = NULL; 892done: 893 spin_unlock_irqrestore (&ehci->lock, flags); 894 return; 895} 896 897static int ehci_get_frame (struct usb_hcd *hcd) 898{ 899 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 900 return (readl (&ehci->regs->frame_index) >> 3) % ehci->periodic_size; 901} 902 903/*-------------------------------------------------------------------------*/ 904 905#define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC 906 907MODULE_DESCRIPTION (DRIVER_INFO); 908MODULE_AUTHOR (DRIVER_AUTHOR); 909MODULE_LICENSE ("GPL"); 910 911#ifdef CONFIG_PCI 912#include "ehci-pci.c" 913#define PCI_DRIVER ehci_pci_driver 914#endif 915 916#ifdef CONFIG_MPC834x 917#include "ehci-fsl.c" 918#define PLATFORM_DRIVER ehci_fsl_driver 919#endif 920 921#ifdef CONFIG_SOC_AU1200 922#include "ehci-au1xxx.c" 923#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 924#endif 925 926#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) 927#error "missing bus glue for ehci-hcd" 928#endif 929 930static int __init ehci_hcd_init(void) 931{ 932 int retval = 0; 933 934 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 935 hcd_name, 936 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 937 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 938 939#ifdef PLATFORM_DRIVER 940 retval = platform_driver_register(&PLATFORM_DRIVER); 941 if (retval < 0) 942 return retval; 943#endif 944 945#ifdef PCI_DRIVER 946 retval = pci_register_driver(&PCI_DRIVER); 947 if (retval < 0) { 948#ifdef PLATFORM_DRIVER 949 platform_driver_unregister(&PLATFORM_DRIVER); 950#endif 951 } 952#endif 953 954 return retval; 955} 956module_init(ehci_hcd_init); 957 958static void __exit ehci_hcd_cleanup(void) 959{ 960#ifdef PLATFORM_DRIVER 961 platform_driver_unregister(&PLATFORM_DRIVER); 962#endif 963#ifdef PCI_DRIVER 964 pci_unregister_driver(&PCI_DRIVER); 965#endif 966} 967module_exit(ehci_hcd_cleanup); 968 969