ehci-hcd.c revision c8c38de9d8002578599222296b90696745ac0fe3
1/* 2 * Copyright (c) 2000-2004 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/dmapool.h> 22#include <linux/kernel.h> 23#include <linux/delay.h> 24#include <linux/ioport.h> 25#include <linux/sched.h> 26#include <linux/vmalloc.h> 27#include <linux/errno.h> 28#include <linux/init.h> 29#include <linux/timer.h> 30#include <linux/ktime.h> 31#include <linux/list.h> 32#include <linux/interrupt.h> 33#include <linux/usb.h> 34#include <linux/usb/hcd.h> 35#include <linux/moduleparam.h> 36#include <linux/dma-mapping.h> 37#include <linux/debugfs.h> 38#include <linux/slab.h> 39#include <linux/uaccess.h> 40 41#include <asm/byteorder.h> 42#include <asm/io.h> 43#include <asm/irq.h> 44#include <asm/system.h> 45#include <asm/unaligned.h> 46 47/*-------------------------------------------------------------------------*/ 48 49/* 50 * EHCI hc_driver implementation ... experimental, incomplete. 51 * Based on the final 1.0 register interface specification. 52 * 53 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 54 * First was PCMCIA, like ISA; then CardBus, which is PCI. 55 * Next comes "CardBay", using USB 2.0 signals. 56 * 57 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 58 * Special thanks to Intel and VIA for providing host controllers to 59 * test this driver on, and Cypress (including In-System Design) for 60 * providing early devices for those host controllers to talk to! 61 */ 62 63#define DRIVER_AUTHOR "David Brownell" 64#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 65 66static const char hcd_name [] = "ehci_hcd"; 67 68 69#undef VERBOSE_DEBUG 70#undef EHCI_URB_TRACE 71 72#ifdef DEBUG 73#define EHCI_STATS 74#endif 75 76/* magic numbers that can affect system performance */ 77#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 78#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 79#define EHCI_TUNE_RL_TT 0 80#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 81#define EHCI_TUNE_MULT_TT 1 82/* 83 * Some drivers think it's safe to schedule isochronous transfers more than 84 * 256 ms into the future (partly as a result of an old bug in the scheduling 85 * code). In an attempt to avoid trouble, we will use a minimum scheduling 86 * length of 512 frames instead of 256. 87 */ 88#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 89 90#define EHCI_IAA_MSECS 10 /* arbitrary */ 91#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 92#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 93#define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */ 94 95/* Initial IRQ latency: faster than hw default */ 96static int log2_irq_thresh = 0; // 0 to 6 97module_param (log2_irq_thresh, int, S_IRUGO); 98MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 99 100/* initial park setting: slower than hw default */ 101static unsigned park = 0; 102module_param (park, uint, S_IRUGO); 103MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 104 105/* for flakey hardware, ignore overcurrent indicators */ 106static int ignore_oc = 0; 107module_param (ignore_oc, bool, S_IRUGO); 108MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 109 110/* for link power management(LPM) feature */ 111static unsigned int hird; 112module_param(hird, int, S_IRUGO); 113MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n"); 114 115#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 116 117/*-------------------------------------------------------------------------*/ 118 119#include "ehci.h" 120#include "ehci-dbg.c" 121 122/*-------------------------------------------------------------------------*/ 123 124static void 125timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) 126{ 127 /* Don't override timeouts which shrink or (later) disable 128 * the async ring; just the I/O watchdog. Note that if a 129 * SHRINK were pending, OFF would never be requested. 130 */ 131 if (timer_pending(&ehci->watchdog) 132 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 133 & ehci->actions)) 134 return; 135 136 if (!test_and_set_bit(action, &ehci->actions)) { 137 unsigned long t; 138 139 switch (action) { 140 case TIMER_IO_WATCHDOG: 141 if (!ehci->need_io_watchdog) 142 return; 143 t = EHCI_IO_JIFFIES; 144 break; 145 case TIMER_ASYNC_OFF: 146 t = EHCI_ASYNC_JIFFIES; 147 break; 148 /* case TIMER_ASYNC_SHRINK: */ 149 default: 150 /* add a jiffie since we synch against the 151 * 8 KHz uframe counter. 152 */ 153 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; 154 break; 155 } 156 mod_timer(&ehci->watchdog, t + jiffies); 157 } 158} 159 160/*-------------------------------------------------------------------------*/ 161 162/* 163 * handshake - spin reading hc until handshake completes or fails 164 * @ptr: address of hc register to be read 165 * @mask: bits to look at in result of read 166 * @done: value of those bits when handshake succeeds 167 * @usec: timeout in microseconds 168 * 169 * Returns negative errno, or zero on success 170 * 171 * Success happens when the "mask" bits have the specified value (hardware 172 * handshake done). There are two failure modes: "usec" have passed (major 173 * hardware flakeout), or the register reads as all-ones (hardware removed). 174 * 175 * That last failure should_only happen in cases like physical cardbus eject 176 * before driver shutdown. But it also seems to be caused by bugs in cardbus 177 * bridge shutdown: shutting down the bridge before the devices using it. 178 */ 179static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, 180 u32 mask, u32 done, int usec) 181{ 182 u32 result; 183 184 do { 185 result = ehci_readl(ehci, ptr); 186 if (result == ~(u32)0) /* card removed */ 187 return -ENODEV; 188 result &= mask; 189 if (result == done) 190 return 0; 191 udelay (1); 192 usec--; 193 } while (usec > 0); 194 return -ETIMEDOUT; 195} 196 197/* check TDI/ARC silicon is in host mode */ 198static int tdi_in_host_mode (struct ehci_hcd *ehci) 199{ 200 u32 __iomem *reg_ptr; 201 u32 tmp; 202 203 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 204 tmp = ehci_readl(ehci, reg_ptr); 205 return (tmp & 3) == USBMODE_CM_HC; 206} 207 208/* force HC to halt state from unknown (EHCI spec section 2.3) */ 209static int ehci_halt (struct ehci_hcd *ehci) 210{ 211 u32 temp = ehci_readl(ehci, &ehci->regs->status); 212 213 /* disable any irqs left enabled by previous code */ 214 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 215 216 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { 217 return 0; 218 } 219 220 if ((temp & STS_HALT) != 0) 221 return 0; 222 223 temp = ehci_readl(ehci, &ehci->regs->command); 224 temp &= ~CMD_RUN; 225 ehci_writel(ehci, temp, &ehci->regs->command); 226 return handshake (ehci, &ehci->regs->status, 227 STS_HALT, STS_HALT, 16 * 125); 228} 229 230static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, 231 u32 mask, u32 done, int usec) 232{ 233 int error; 234 235 error = handshake(ehci, ptr, mask, done, usec); 236 if (error) { 237 ehci_halt(ehci); 238 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 239 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", 240 ptr, mask, done, error); 241 } 242 243 return error; 244} 245 246/* put TDI/ARC silicon into EHCI mode */ 247static void tdi_reset (struct ehci_hcd *ehci) 248{ 249 u32 __iomem *reg_ptr; 250 u32 tmp; 251 252 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 253 tmp = ehci_readl(ehci, reg_ptr); 254 tmp |= USBMODE_CM_HC; 255 /* The default byte access to MMR space is LE after 256 * controller reset. Set the required endian mode 257 * for transfer buffers to match the host microprocessor 258 */ 259 if (ehci_big_endian_mmio(ehci)) 260 tmp |= USBMODE_BE; 261 ehci_writel(ehci, tmp, reg_ptr); 262} 263 264/* reset a non-running (STS_HALT == 1) controller */ 265static int ehci_reset (struct ehci_hcd *ehci) 266{ 267 int retval; 268 u32 command = ehci_readl(ehci, &ehci->regs->command); 269 270 /* If the EHCI debug controller is active, special care must be 271 * taken before and after a host controller reset */ 272 if (ehci->debug && !dbgp_reset_prep()) 273 ehci->debug = NULL; 274 275 command |= CMD_RESET; 276 dbg_cmd (ehci, "reset", command); 277 ehci_writel(ehci, command, &ehci->regs->command); 278 ehci_to_hcd(ehci)->state = HC_STATE_HALT; 279 ehci->next_statechange = jiffies; 280 retval = handshake (ehci, &ehci->regs->command, 281 CMD_RESET, 0, 250 * 1000); 282 283 if (ehci->has_hostpc) { 284 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 285 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 286 ehci_writel(ehci, TXFIFO_DEFAULT, 287 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); 288 } 289 if (retval) 290 return retval; 291 292 if (ehci_is_TDI(ehci)) 293 tdi_reset (ehci); 294 295 if (ehci->debug) 296 dbgp_external_startup(); 297 298 return retval; 299} 300 301/* idle the controller (from running) */ 302static void ehci_quiesce (struct ehci_hcd *ehci) 303{ 304 u32 temp; 305 306#ifdef DEBUG 307 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) 308 BUG (); 309#endif 310 311 /* wait for any schedule enables/disables to take effect */ 312 temp = ehci_readl(ehci, &ehci->regs->command) << 10; 313 temp &= STS_ASS | STS_PSS; 314 if (handshake_on_error_set_halt(ehci, &ehci->regs->status, 315 STS_ASS | STS_PSS, temp, 16 * 125)) 316 return; 317 318 /* then disable anything that's still active */ 319 temp = ehci_readl(ehci, &ehci->regs->command); 320 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 321 ehci_writel(ehci, temp, &ehci->regs->command); 322 323 /* hardware can take 16 microframes to turn off ... */ 324 handshake_on_error_set_halt(ehci, &ehci->regs->status, 325 STS_ASS | STS_PSS, 0, 16 * 125); 326} 327 328/*-------------------------------------------------------------------------*/ 329 330static void end_unlink_async(struct ehci_hcd *ehci); 331static void ehci_work(struct ehci_hcd *ehci); 332 333#include "ehci-hub.c" 334#include "ehci-lpm.c" 335#include "ehci-mem.c" 336#include "ehci-q.c" 337#include "ehci-sched.c" 338 339/*-------------------------------------------------------------------------*/ 340 341static void ehci_iaa_watchdog(unsigned long param) 342{ 343 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 344 unsigned long flags; 345 346 spin_lock_irqsave (&ehci->lock, flags); 347 348 /* Lost IAA irqs wedge things badly; seen first with a vt8235. 349 * So we need this watchdog, but must protect it against both 350 * (a) SMP races against real IAA firing and retriggering, and 351 * (b) clean HC shutdown, when IAA watchdog was pending. 352 */ 353 if (ehci->reclaim 354 && !timer_pending(&ehci->iaa_watchdog) 355 && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { 356 u32 cmd, status; 357 358 /* If we get here, IAA is *REALLY* late. It's barely 359 * conceivable that the system is so busy that CMD_IAAD 360 * is still legitimately set, so let's be sure it's 361 * clear before we read STS_IAA. (The HC should clear 362 * CMD_IAAD when it sets STS_IAA.) 363 */ 364 cmd = ehci_readl(ehci, &ehci->regs->command); 365 if (cmd & CMD_IAAD) 366 ehci_writel(ehci, cmd & ~CMD_IAAD, 367 &ehci->regs->command); 368 369 /* If IAA is set here it either legitimately triggered 370 * before we cleared IAAD above (but _way_ late, so we'll 371 * still count it as lost) ... or a silicon erratum: 372 * - VIA seems to set IAA without triggering the IRQ; 373 * - IAAD potentially cleared without setting IAA. 374 */ 375 status = ehci_readl(ehci, &ehci->regs->status); 376 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { 377 COUNT (ehci->stats.lost_iaa); 378 ehci_writel(ehci, STS_IAA, &ehci->regs->status); 379 } 380 381 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", 382 status, cmd); 383 end_unlink_async(ehci); 384 } 385 386 spin_unlock_irqrestore(&ehci->lock, flags); 387} 388 389static void ehci_watchdog(unsigned long param) 390{ 391 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 392 unsigned long flags; 393 394 spin_lock_irqsave(&ehci->lock, flags); 395 396 /* stop async processing after it's idled a bit */ 397 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 398 start_unlink_async (ehci, ehci->async); 399 400 /* ehci could run by timer, without IRQs ... */ 401 ehci_work (ehci); 402 403 spin_unlock_irqrestore (&ehci->lock, flags); 404} 405 406/* On some systems, leaving remote wakeup enabled prevents system shutdown. 407 * The firmware seems to think that powering off is a wakeup event! 408 * This routine turns off remote wakeup and everything else, on all ports. 409 */ 410static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 411{ 412 int port = HCS_N_PORTS(ehci->hcs_params); 413 414 while (port--) 415 ehci_writel(ehci, PORT_RWC_BITS, 416 &ehci->regs->port_status[port]); 417} 418 419/* 420 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 421 * Should be called with ehci->lock held. 422 */ 423static void ehci_silence_controller(struct ehci_hcd *ehci) 424{ 425 ehci_halt(ehci); 426 ehci_turn_off_all_ports(ehci); 427 428 /* make BIOS/etc use companion controller during reboot */ 429 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 430 431 /* unblock posted writes */ 432 ehci_readl(ehci, &ehci->regs->configured_flag); 433} 434 435/* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 436 * This forcibly disables dma and IRQs, helping kexec and other cases 437 * where the next system software may expect clean state. 438 */ 439static void ehci_shutdown(struct usb_hcd *hcd) 440{ 441 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 442 443 del_timer_sync(&ehci->watchdog); 444 del_timer_sync(&ehci->iaa_watchdog); 445 446 spin_lock_irq(&ehci->lock); 447 ehci_silence_controller(ehci); 448 spin_unlock_irq(&ehci->lock); 449} 450 451static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 452{ 453 unsigned port; 454 455 if (!HCS_PPC (ehci->hcs_params)) 456 return; 457 458 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 459 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 460 (void) ehci_hub_control(ehci_to_hcd(ehci), 461 is_on ? SetPortFeature : ClearPortFeature, 462 USB_PORT_FEAT_POWER, 463 port--, NULL, 0); 464 /* Flush those writes */ 465 ehci_readl(ehci, &ehci->regs->command); 466 msleep(20); 467} 468 469/*-------------------------------------------------------------------------*/ 470 471/* 472 * ehci_work is called from some interrupts, timers, and so on. 473 * it calls driver completion functions, after dropping ehci->lock. 474 */ 475static void ehci_work (struct ehci_hcd *ehci) 476{ 477 timer_action_done (ehci, TIMER_IO_WATCHDOG); 478 479 /* another CPU may drop ehci->lock during a schedule scan while 480 * it reports urb completions. this flag guards against bogus 481 * attempts at re-entrant schedule scanning. 482 */ 483 if (ehci->scanning) 484 return; 485 ehci->scanning = 1; 486 scan_async (ehci); 487 if (ehci->next_uframe != -1) 488 scan_periodic (ehci); 489 ehci->scanning = 0; 490 491 /* the IO watchdog guards against hardware or driver bugs that 492 * misplace IRQs, and should let us run completely without IRQs. 493 * such lossage has been observed on both VT6202 and VT8235. 494 */ 495 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && 496 (ehci->async->qh_next.ptr != NULL || 497 ehci->periodic_sched != 0)) 498 timer_action (ehci, TIMER_IO_WATCHDOG); 499} 500 501/* 502 * Called when the ehci_hcd module is removed. 503 */ 504static void ehci_stop (struct usb_hcd *hcd) 505{ 506 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 507 508 ehci_dbg (ehci, "stop\n"); 509 510 /* no more interrupts ... */ 511 del_timer_sync (&ehci->watchdog); 512 del_timer_sync(&ehci->iaa_watchdog); 513 514 spin_lock_irq(&ehci->lock); 515 if (HC_IS_RUNNING (hcd->state)) 516 ehci_quiesce (ehci); 517 518 ehci_silence_controller(ehci); 519 ehci_reset (ehci); 520 spin_unlock_irq(&ehci->lock); 521 522 remove_companion_file(ehci); 523 remove_debug_files (ehci); 524 525 /* root hub is shut down separately (first, when possible) */ 526 spin_lock_irq (&ehci->lock); 527 if (ehci->async) 528 ehci_work (ehci); 529 spin_unlock_irq (&ehci->lock); 530 ehci_mem_cleanup (ehci); 531 532#ifdef EHCI_STATS 533 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 534 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 535 ehci->stats.lost_iaa); 536 ehci_dbg (ehci, "complete %ld unlink %ld\n", 537 ehci->stats.complete, ehci->stats.unlink); 538#endif 539 540 dbg_status (ehci, "ehci_stop completed", 541 ehci_readl(ehci, &ehci->regs->status)); 542} 543 544/* one-time init, only for memory state */ 545static int ehci_init(struct usb_hcd *hcd) 546{ 547 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 548 u32 temp; 549 int retval; 550 u32 hcc_params; 551 struct ehci_qh_hw *hw; 552 553 spin_lock_init(&ehci->lock); 554 555 /* 556 * keep io watchdog by default, those good HCDs could turn off it later 557 */ 558 ehci->need_io_watchdog = 1; 559 init_timer(&ehci->watchdog); 560 ehci->watchdog.function = ehci_watchdog; 561 ehci->watchdog.data = (unsigned long) ehci; 562 563 init_timer(&ehci->iaa_watchdog); 564 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 565 ehci->iaa_watchdog.data = (unsigned long) ehci; 566 567 /* 568 * hw default: 1K periodic list heads, one per frame. 569 * periodic_size can shrink by USBCMD update if hcc_params allows. 570 */ 571 ehci->periodic_size = DEFAULT_I_TDPS; 572 INIT_LIST_HEAD(&ehci->cached_itd_list); 573 INIT_LIST_HEAD(&ehci->cached_sitd_list); 574 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 575 return retval; 576 577 /* controllers may cache some of the periodic schedule ... */ 578 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 579 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 580 ehci->i_thresh = 2 + 8; 581 else // N microframes cached 582 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 583 584 ehci->reclaim = NULL; 585 ehci->next_uframe = -1; 586 ehci->clock_frame = -1; 587 588 /* 589 * dedicate a qh for the async ring head, since we couldn't unlink 590 * a 'real' qh without stopping the async schedule [4.8]. use it 591 * as the 'reclamation list head' too. 592 * its dummy is used in hw_alt_next of many tds, to prevent the qh 593 * from automatically advancing to the next td after short reads. 594 */ 595 ehci->async->qh_next.qh = NULL; 596 hw = ehci->async->hw; 597 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 598 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 599 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 600 hw->hw_qtd_next = EHCI_LIST_END(ehci); 601 ehci->async->qh_state = QH_STATE_LINKED; 602 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 603 604 /* clear interrupt enables, set irq latency */ 605 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 606 log2_irq_thresh = 0; 607 temp = 1 << (16 + log2_irq_thresh); 608 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 609 ehci->has_ppcd = 1; 610 ehci_dbg(ehci, "enable per-port change event\n"); 611 temp |= CMD_PPCEE; 612 } 613 if (HCC_CANPARK(hcc_params)) { 614 /* HW default park == 3, on hardware that supports it (like 615 * NVidia and ALI silicon), maximizes throughput on the async 616 * schedule by avoiding QH fetches between transfers. 617 * 618 * With fast usb storage devices and NForce2, "park" seems to 619 * make problems: throughput reduction (!), data errors... 620 */ 621 if (park) { 622 park = min(park, (unsigned) 3); 623 temp |= CMD_PARK; 624 temp |= park << 8; 625 } 626 ehci_dbg(ehci, "park %d\n", park); 627 } 628 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 629 /* periodic schedule size can be smaller than default */ 630 temp &= ~(3 << 2); 631 temp |= (EHCI_TUNE_FLS << 2); 632 switch (EHCI_TUNE_FLS) { 633 case 0: ehci->periodic_size = 1024; break; 634 case 1: ehci->periodic_size = 512; break; 635 case 2: ehci->periodic_size = 256; break; 636 default: BUG(); 637 } 638 } 639 if (HCC_LPM(hcc_params)) { 640 /* support link power management EHCI 1.1 addendum */ 641 ehci_dbg(ehci, "support lpm\n"); 642 ehci->has_lpm = 1; 643 if (hird > 0xf) { 644 ehci_dbg(ehci, "hird %d invalid, use default 0", 645 hird); 646 hird = 0; 647 } 648 temp |= hird << 24; 649 } 650 ehci->command = temp; 651 652 /* Accept arbitrarily long scatter-gather lists */ 653 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 654 hcd->self.sg_tablesize = ~0; 655 return 0; 656} 657 658/* start HC running; it's halted, ehci_init() has been run (once) */ 659static int ehci_run (struct usb_hcd *hcd) 660{ 661 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 662 int retval; 663 u32 temp; 664 u32 hcc_params; 665 666 hcd->uses_new_polling = 1; 667 668 /* EHCI spec section 4.1 */ 669 if ((retval = ehci_reset(ehci)) != 0) { 670 ehci_mem_cleanup(ehci); 671 return retval; 672 } 673 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 674 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 675 676 /* 677 * hcc_params controls whether ehci->regs->segment must (!!!) 678 * be used; it constrains QH/ITD/SITD and QTD locations. 679 * pci_pool consistent memory always uses segment zero. 680 * streaming mappings for I/O buffers, like pci_map_single(), 681 * can return segments above 4GB, if the device allows. 682 * 683 * NOTE: the dma mask is visible through dma_supported(), so 684 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 685 * Scsi_Host.highmem_io, and so forth. It's readonly to all 686 * host side drivers though. 687 */ 688 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 689 if (HCC_64BIT_ADDR(hcc_params)) { 690 ehci_writel(ehci, 0, &ehci->regs->segment); 691#if 0 692// this is deeply broken on almost all architectures 693 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) 694 ehci_info(ehci, "enabled 64bit DMA\n"); 695#endif 696 } 697 698 699 // Philips, Intel, and maybe others need CMD_RUN before the 700 // root hub will detect new devices (why?); NEC doesn't 701 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 702 ehci->command |= CMD_RUN; 703 ehci_writel(ehci, ehci->command, &ehci->regs->command); 704 dbg_cmd (ehci, "init", ehci->command); 705 706 /* 707 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 708 * are explicitly handed to companion controller(s), so no TT is 709 * involved with the root hub. (Except where one is integrated, 710 * and there's no companion controller unless maybe for USB OTG.) 711 * 712 * Turning on the CF flag will transfer ownership of all ports 713 * from the companions to the EHCI controller. If any of the 714 * companions are in the middle of a port reset at the time, it 715 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 716 * guarantees that no resets are in progress. After we set CF, 717 * a short delay lets the hardware catch up; new resets shouldn't 718 * be started before the port switching actions could complete. 719 */ 720 down_write(&ehci_cf_port_reset_rwsem); 721 hcd->state = HC_STATE_RUNNING; 722 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 723 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 724 msleep(5); 725 up_write(&ehci_cf_port_reset_rwsem); 726 ehci->last_periodic_enable = ktime_get_real(); 727 728 temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); 729 ehci_info (ehci, 730 "USB %x.%x started, EHCI %x.%02x%s\n", 731 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 732 temp >> 8, temp & 0xff, 733 ignore_oc ? ", overcurrent ignored" : ""); 734 735 ehci_writel(ehci, INTR_MASK, 736 &ehci->regs->intr_enable); /* Turn On Interrupts */ 737 738 /* GRR this is run-once init(), being done every time the HC starts. 739 * So long as they're part of class devices, we can't do it init() 740 * since the class device isn't created that early. 741 */ 742 create_debug_files(ehci); 743 create_companion_file(ehci); 744 745 return 0; 746} 747 748/*-------------------------------------------------------------------------*/ 749 750static irqreturn_t ehci_irq (struct usb_hcd *hcd) 751{ 752 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 753 u32 status, masked_status, pcd_status = 0, cmd; 754 int bh; 755 756 spin_lock (&ehci->lock); 757 758 status = ehci_readl(ehci, &ehci->regs->status); 759 760 /* e.g. cardbus physical eject */ 761 if (status == ~(u32) 0) { 762 ehci_dbg (ehci, "device removed\n"); 763 goto dead; 764 } 765 766 masked_status = status & INTR_MASK; 767 if (!masked_status) { /* irq sharing? */ 768 spin_unlock(&ehci->lock); 769 return IRQ_NONE; 770 } 771 772 /* clear (just) interrupts */ 773 ehci_writel(ehci, masked_status, &ehci->regs->status); 774 cmd = ehci_readl(ehci, &ehci->regs->command); 775 bh = 0; 776 777#ifdef VERBOSE_DEBUG 778 /* unrequested/ignored: Frame List Rollover */ 779 dbg_status (ehci, "irq", status); 780#endif 781 782 /* INT, ERR, and IAA interrupt rates can be throttled */ 783 784 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 785 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 786 if (likely ((status & STS_ERR) == 0)) 787 COUNT (ehci->stats.normal); 788 else 789 COUNT (ehci->stats.error); 790 bh = 1; 791 } 792 793 /* complete the unlinking of some qh [4.15.2.3] */ 794 if (status & STS_IAA) { 795 /* guard against (alleged) silicon errata */ 796 if (cmd & CMD_IAAD) { 797 ehci_writel(ehci, cmd & ~CMD_IAAD, 798 &ehci->regs->command); 799 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 800 } 801 if (ehci->reclaim) { 802 COUNT(ehci->stats.reclaim); 803 end_unlink_async(ehci); 804 } else 805 ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); 806 } 807 808 /* remote wakeup [4.3.1] */ 809 if (status & STS_PCD) { 810 unsigned i = HCS_N_PORTS (ehci->hcs_params); 811 u32 ppcd = 0; 812 813 /* kick root hub later */ 814 pcd_status = status; 815 816 /* resume root hub? */ 817 if (!(cmd & CMD_RUN)) 818 usb_hcd_resume_root_hub(hcd); 819 820 /* get per-port change detect bits */ 821 if (ehci->has_ppcd) 822 ppcd = status >> 16; 823 824 while (i--) { 825 int pstatus; 826 827 /* leverage per-port change bits feature */ 828 if (ehci->has_ppcd && !(ppcd & (1 << i))) 829 continue; 830 pstatus = ehci_readl(ehci, 831 &ehci->regs->port_status[i]); 832 833 if (pstatus & PORT_OWNER) 834 continue; 835 if (!(test_bit(i, &ehci->suspended_ports) && 836 ((pstatus & PORT_RESUME) || 837 !(pstatus & PORT_SUSPEND)) && 838 (pstatus & PORT_PE) && 839 ehci->reset_done[i] == 0)) 840 continue; 841 842 /* start 20 msec resume signaling from this port, 843 * and make khubd collect PORT_STAT_C_SUSPEND to 844 * stop that signaling. Use 5 ms extra for safety, 845 * like usb_port_resume() does. 846 */ 847 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); 848 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 849 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 850 } 851 } 852 853 /* PCI errors [4.15.2.4] */ 854 if (unlikely ((status & STS_FATAL) != 0)) { 855 ehci_err(ehci, "fatal error\n"); 856 dbg_cmd(ehci, "fatal", cmd); 857 dbg_status(ehci, "fatal", status); 858 ehci_halt(ehci); 859dead: 860 ehci_reset(ehci); 861 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 862 /* generic layer kills/unlinks all urbs, then 863 * uses ehci_stop to clean up the rest 864 */ 865 bh = 1; 866 } 867 868 if (bh) 869 ehci_work (ehci); 870 spin_unlock (&ehci->lock); 871 if (pcd_status) 872 usb_hcd_poll_rh_status(hcd); 873 return IRQ_HANDLED; 874} 875 876/*-------------------------------------------------------------------------*/ 877 878/* 879 * non-error returns are a promise to giveback() the urb later 880 * we drop ownership so next owner (or urb unlink) can get it 881 * 882 * urb + dev is in hcd.self.controller.urb_list 883 * we're queueing TDs onto software and hardware lists 884 * 885 * hcd-specific init for hcpriv hasn't been done yet 886 * 887 * NOTE: control, bulk, and interrupt share the same code to append TDs 888 * to a (possibly active) QH, and the same QH scanning code. 889 */ 890static int ehci_urb_enqueue ( 891 struct usb_hcd *hcd, 892 struct urb *urb, 893 gfp_t mem_flags 894) { 895 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 896 struct list_head qtd_list; 897 898 INIT_LIST_HEAD (&qtd_list); 899 900 switch (usb_pipetype (urb->pipe)) { 901 case PIPE_CONTROL: 902 /* qh_completions() code doesn't handle all the fault cases 903 * in multi-TD control transfers. Even 1KB is rare anyway. 904 */ 905 if (urb->transfer_buffer_length > (16 * 1024)) 906 return -EMSGSIZE; 907 /* FALLTHROUGH */ 908 /* case PIPE_BULK: */ 909 default: 910 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 911 return -ENOMEM; 912 return submit_async(ehci, urb, &qtd_list, mem_flags); 913 914 case PIPE_INTERRUPT: 915 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 916 return -ENOMEM; 917 return intr_submit(ehci, urb, &qtd_list, mem_flags); 918 919 case PIPE_ISOCHRONOUS: 920 if (urb->dev->speed == USB_SPEED_HIGH) 921 return itd_submit (ehci, urb, mem_flags); 922 else 923 return sitd_submit (ehci, urb, mem_flags); 924 } 925} 926 927static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 928{ 929 /* failfast */ 930 if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) 931 end_unlink_async(ehci); 932 933 /* If the QH isn't linked then there's nothing we can do 934 * unless we were called during a giveback, in which case 935 * qh_completions() has to deal with it. 936 */ 937 if (qh->qh_state != QH_STATE_LINKED) { 938 if (qh->qh_state == QH_STATE_COMPLETING) 939 qh->needs_rescan = 1; 940 return; 941 } 942 943 /* defer till later if busy */ 944 if (ehci->reclaim) { 945 struct ehci_qh *last; 946 947 for (last = ehci->reclaim; 948 last->reclaim; 949 last = last->reclaim) 950 continue; 951 qh->qh_state = QH_STATE_UNLINK_WAIT; 952 last->reclaim = qh; 953 954 /* start IAA cycle */ 955 } else 956 start_unlink_async (ehci, qh); 957} 958 959/* remove from hardware lists 960 * completions normally happen asynchronously 961 */ 962 963static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 964{ 965 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 966 struct ehci_qh *qh; 967 unsigned long flags; 968 int rc; 969 970 spin_lock_irqsave (&ehci->lock, flags); 971 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 972 if (rc) 973 goto done; 974 975 switch (usb_pipetype (urb->pipe)) { 976 // case PIPE_CONTROL: 977 // case PIPE_BULK: 978 default: 979 qh = (struct ehci_qh *) urb->hcpriv; 980 if (!qh) 981 break; 982 switch (qh->qh_state) { 983 case QH_STATE_LINKED: 984 case QH_STATE_COMPLETING: 985 unlink_async(ehci, qh); 986 break; 987 case QH_STATE_UNLINK: 988 case QH_STATE_UNLINK_WAIT: 989 /* already started */ 990 break; 991 case QH_STATE_IDLE: 992 /* QH might be waiting for a Clear-TT-Buffer */ 993 qh_completions(ehci, qh); 994 break; 995 } 996 break; 997 998 case PIPE_INTERRUPT: 999 qh = (struct ehci_qh *) urb->hcpriv; 1000 if (!qh) 1001 break; 1002 switch (qh->qh_state) { 1003 case QH_STATE_LINKED: 1004 case QH_STATE_COMPLETING: 1005 intr_deschedule (ehci, qh); 1006 break; 1007 case QH_STATE_IDLE: 1008 qh_completions (ehci, qh); 1009 break; 1010 default: 1011 ehci_dbg (ehci, "bogus qh %p state %d\n", 1012 qh, qh->qh_state); 1013 goto done; 1014 } 1015 break; 1016 1017 case PIPE_ISOCHRONOUS: 1018 // itd or sitd ... 1019 1020 // wait till next completion, do it then. 1021 // completion irqs can wait up to 1024 msec, 1022 break; 1023 } 1024done: 1025 spin_unlock_irqrestore (&ehci->lock, flags); 1026 return rc; 1027} 1028 1029/*-------------------------------------------------------------------------*/ 1030 1031// bulk qh holds the data toggle 1032 1033static void 1034ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1035{ 1036 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1037 unsigned long flags; 1038 struct ehci_qh *qh, *tmp; 1039 1040 /* ASSERT: any requests/urbs are being unlinked */ 1041 /* ASSERT: nobody can be submitting urbs for this any more */ 1042 1043rescan: 1044 spin_lock_irqsave (&ehci->lock, flags); 1045 qh = ep->hcpriv; 1046 if (!qh) 1047 goto done; 1048 1049 /* endpoints can be iso streams. for now, we don't 1050 * accelerate iso completions ... so spin a while. 1051 */ 1052 if (qh->hw == NULL) { 1053 ehci_vdbg (ehci, "iso delay\n"); 1054 goto idle_timeout; 1055 } 1056 1057 if (!HC_IS_RUNNING (hcd->state)) 1058 qh->qh_state = QH_STATE_IDLE; 1059 switch (qh->qh_state) { 1060 case QH_STATE_LINKED: 1061 case QH_STATE_COMPLETING: 1062 for (tmp = ehci->async->qh_next.qh; 1063 tmp && tmp != qh; 1064 tmp = tmp->qh_next.qh) 1065 continue; 1066 /* periodic qh self-unlinks on empty */ 1067 if (!tmp) 1068 goto nogood; 1069 unlink_async (ehci, qh); 1070 /* FALL THROUGH */ 1071 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1072 case QH_STATE_UNLINK_WAIT: 1073idle_timeout: 1074 spin_unlock_irqrestore (&ehci->lock, flags); 1075 schedule_timeout_uninterruptible(1); 1076 goto rescan; 1077 case QH_STATE_IDLE: /* fully unlinked */ 1078 if (qh->clearing_tt) 1079 goto idle_timeout; 1080 if (list_empty (&qh->qtd_list)) { 1081 qh_put (qh); 1082 break; 1083 } 1084 /* else FALL THROUGH */ 1085 default: 1086nogood: 1087 /* caller was supposed to have unlinked any requests; 1088 * that's not our job. just leak this memory. 1089 */ 1090 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1091 qh, ep->desc.bEndpointAddress, qh->qh_state, 1092 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1093 break; 1094 } 1095 ep->hcpriv = NULL; 1096done: 1097 spin_unlock_irqrestore (&ehci->lock, flags); 1098} 1099 1100static void 1101ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1102{ 1103 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1104 struct ehci_qh *qh; 1105 int eptype = usb_endpoint_type(&ep->desc); 1106 int epnum = usb_endpoint_num(&ep->desc); 1107 int is_out = usb_endpoint_dir_out(&ep->desc); 1108 unsigned long flags; 1109 1110 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1111 return; 1112 1113 spin_lock_irqsave(&ehci->lock, flags); 1114 qh = ep->hcpriv; 1115 1116 /* For Bulk and Interrupt endpoints we maintain the toggle state 1117 * in the hardware; the toggle bits in udev aren't used at all. 1118 * When an endpoint is reset by usb_clear_halt() we must reset 1119 * the toggle bit in the QH. 1120 */ 1121 if (qh) { 1122 usb_settoggle(qh->dev, epnum, is_out, 0); 1123 if (!list_empty(&qh->qtd_list)) { 1124 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1125 } else if (qh->qh_state == QH_STATE_LINKED || 1126 qh->qh_state == QH_STATE_COMPLETING) { 1127 1128 /* The toggle value in the QH can't be updated 1129 * while the QH is active. Unlink it now; 1130 * re-linking will call qh_refresh(). 1131 */ 1132 if (eptype == USB_ENDPOINT_XFER_BULK) 1133 unlink_async(ehci, qh); 1134 else 1135 intr_deschedule(ehci, qh); 1136 } 1137 } 1138 spin_unlock_irqrestore(&ehci->lock, flags); 1139} 1140 1141static int ehci_get_frame (struct usb_hcd *hcd) 1142{ 1143 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1144 return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % 1145 ehci->periodic_size; 1146} 1147 1148/*-------------------------------------------------------------------------*/ 1149 1150MODULE_DESCRIPTION(DRIVER_DESC); 1151MODULE_AUTHOR (DRIVER_AUTHOR); 1152MODULE_LICENSE ("GPL"); 1153 1154#ifdef CONFIG_PCI 1155#include "ehci-pci.c" 1156#define PCI_DRIVER ehci_pci_driver 1157#endif 1158 1159#ifdef CONFIG_USB_EHCI_FSL 1160#include "ehci-fsl.c" 1161#define PLATFORM_DRIVER ehci_fsl_driver 1162#endif 1163 1164#ifdef CONFIG_USB_EHCI_MXC 1165#include "ehci-mxc.c" 1166#define PLATFORM_DRIVER ehci_mxc_driver 1167#endif 1168 1169#ifdef CONFIG_SOC_AU1200 1170#include "ehci-au1xxx.c" 1171#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 1172#endif 1173 1174#ifdef CONFIG_ARCH_OMAP3 1175#include "ehci-omap.c" 1176#define PLATFORM_DRIVER ehci_hcd_omap_driver 1177#endif 1178 1179#ifdef CONFIG_PPC_PS3 1180#include "ehci-ps3.c" 1181#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1182#endif 1183 1184#ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1185#include "ehci-ppc-of.c" 1186#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1187#endif 1188 1189#ifdef CONFIG_XPS_USB_HCD_XILINX 1190#include "ehci-xilinx-of.c" 1191#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1192#endif 1193 1194#ifdef CONFIG_PLAT_ORION 1195#include "ehci-orion.c" 1196#define PLATFORM_DRIVER ehci_orion_driver 1197#endif 1198 1199#ifdef CONFIG_ARCH_IXP4XX 1200#include "ehci-ixp4xx.c" 1201#define PLATFORM_DRIVER ixp4xx_ehci_driver 1202#endif 1203 1204#ifdef CONFIG_USB_W90X900_EHCI 1205#include "ehci-w90x900.c" 1206#define PLATFORM_DRIVER ehci_hcd_w90x900_driver 1207#endif 1208 1209#ifdef CONFIG_ARCH_AT91 1210#include "ehci-atmel.c" 1211#define PLATFORM_DRIVER ehci_atmel_driver 1212#endif 1213 1214#ifdef CONFIG_USB_OCTEON_EHCI 1215#include "ehci-octeon.c" 1216#define PLATFORM_DRIVER ehci_octeon_driver 1217#endif 1218 1219#ifdef CONFIG_ARCH_VT8500 1220#include "ehci-vt8500.c" 1221#define PLATFORM_DRIVER vt8500_ehci_driver 1222#endif 1223 1224#ifdef CONFIG_PLAT_SPEAR 1225#include "ehci-spear.c" 1226#define PLATFORM_DRIVER spear_ehci_hcd_driver 1227#endif 1228 1229#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1230 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1231 !defined(XILINX_OF_PLATFORM_DRIVER) 1232#error "missing bus glue for ehci-hcd" 1233#endif 1234 1235static int __init ehci_hcd_init(void) 1236{ 1237 int retval = 0; 1238 1239 if (usb_disabled()) 1240 return -ENODEV; 1241 1242 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1243 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1244 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1245 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1246 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1247 " before uhci_hcd and ohci_hcd, not after\n"); 1248 1249 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1250 hcd_name, 1251 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1252 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1253 1254#ifdef DEBUG 1255 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1256 if (!ehci_debug_root) { 1257 retval = -ENOENT; 1258 goto err_debug; 1259 } 1260#endif 1261 1262#ifdef PLATFORM_DRIVER 1263 retval = platform_driver_register(&PLATFORM_DRIVER); 1264 if (retval < 0) 1265 goto clean0; 1266#endif 1267 1268#ifdef PCI_DRIVER 1269 retval = pci_register_driver(&PCI_DRIVER); 1270 if (retval < 0) 1271 goto clean1; 1272#endif 1273 1274#ifdef PS3_SYSTEM_BUS_DRIVER 1275 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1276 if (retval < 0) 1277 goto clean2; 1278#endif 1279 1280#ifdef OF_PLATFORM_DRIVER 1281 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); 1282 if (retval < 0) 1283 goto clean3; 1284#endif 1285 1286#ifdef XILINX_OF_PLATFORM_DRIVER 1287 retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER); 1288 if (retval < 0) 1289 goto clean4; 1290#endif 1291 return retval; 1292 1293#ifdef XILINX_OF_PLATFORM_DRIVER 1294 /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */ 1295clean4: 1296#endif 1297#ifdef OF_PLATFORM_DRIVER 1298 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1299clean3: 1300#endif 1301#ifdef PS3_SYSTEM_BUS_DRIVER 1302 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1303clean2: 1304#endif 1305#ifdef PCI_DRIVER 1306 pci_unregister_driver(&PCI_DRIVER); 1307clean1: 1308#endif 1309#ifdef PLATFORM_DRIVER 1310 platform_driver_unregister(&PLATFORM_DRIVER); 1311clean0: 1312#endif 1313#ifdef DEBUG 1314 debugfs_remove(ehci_debug_root); 1315 ehci_debug_root = NULL; 1316err_debug: 1317#endif 1318 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1319 return retval; 1320} 1321module_init(ehci_hcd_init); 1322 1323static void __exit ehci_hcd_cleanup(void) 1324{ 1325#ifdef XILINX_OF_PLATFORM_DRIVER 1326 of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); 1327#endif 1328#ifdef OF_PLATFORM_DRIVER 1329 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1330#endif 1331#ifdef PLATFORM_DRIVER 1332 platform_driver_unregister(&PLATFORM_DRIVER); 1333#endif 1334#ifdef PCI_DRIVER 1335 pci_unregister_driver(&PCI_DRIVER); 1336#endif 1337#ifdef PS3_SYSTEM_BUS_DRIVER 1338 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1339#endif 1340#ifdef DEBUG 1341 debugfs_remove(ehci_debug_root); 1342#endif 1343 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1344} 1345module_exit(ehci_hcd_cleanup); 1346 1347