ehci-hcd.c revision dc75ce9d929aabeb0843a6b1a4ab320e58ba1597
1/* 2 * Enhanced Host Controller Interface (EHCI) driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * Copyright (c) 2000-2004 by David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#include <linux/module.h> 24#include <linux/pci.h> 25#include <linux/dmapool.h> 26#include <linux/kernel.h> 27#include <linux/delay.h> 28#include <linux/ioport.h> 29#include <linux/sched.h> 30#include <linux/vmalloc.h> 31#include <linux/errno.h> 32#include <linux/init.h> 33#include <linux/timer.h> 34#include <linux/ktime.h> 35#include <linux/list.h> 36#include <linux/interrupt.h> 37#include <linux/usb.h> 38#include <linux/usb/hcd.h> 39#include <linux/moduleparam.h> 40#include <linux/dma-mapping.h> 41#include <linux/debugfs.h> 42#include <linux/slab.h> 43#include <linux/uaccess.h> 44 45#include <asm/byteorder.h> 46#include <asm/io.h> 47#include <asm/irq.h> 48#include <asm/unaligned.h> 49 50#if defined(CONFIG_PPC_PS3) 51#include <asm/firmware.h> 52#endif 53 54/*-------------------------------------------------------------------------*/ 55 56/* 57 * EHCI hc_driver implementation ... experimental, incomplete. 58 * Based on the final 1.0 register interface specification. 59 * 60 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 61 * First was PCMCIA, like ISA; then CardBus, which is PCI. 62 * Next comes "CardBay", using USB 2.0 signals. 63 * 64 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 65 * Special thanks to Intel and VIA for providing host controllers to 66 * test this driver on, and Cypress (including In-System Design) for 67 * providing early devices for those host controllers to talk to! 68 */ 69 70#define DRIVER_AUTHOR "David Brownell" 71#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 72 73static const char hcd_name [] = "ehci_hcd"; 74 75 76#undef VERBOSE_DEBUG 77#undef EHCI_URB_TRACE 78 79#ifdef DEBUG 80#define EHCI_STATS 81#endif 82 83/* magic numbers that can affect system performance */ 84#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 85#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 86#define EHCI_TUNE_RL_TT 0 87#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 88#define EHCI_TUNE_MULT_TT 1 89/* 90 * Some drivers think it's safe to schedule isochronous transfers more than 91 * 256 ms into the future (partly as a result of an old bug in the scheduling 92 * code). In an attempt to avoid trouble, we will use a minimum scheduling 93 * length of 512 frames instead of 256. 94 */ 95#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 96 97#define EHCI_IAA_MSECS 10 /* arbitrary */ 98#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 99#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 100#define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1) 101 /* 5-ms async qh unlink delay */ 102 103/* Initial IRQ latency: faster than hw default */ 104static int log2_irq_thresh = 0; // 0 to 6 105module_param (log2_irq_thresh, int, S_IRUGO); 106MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 107 108/* initial park setting: slower than hw default */ 109static unsigned park = 0; 110module_param (park, uint, S_IRUGO); 111MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 112 113/* for flakey hardware, ignore overcurrent indicators */ 114static bool ignore_oc = 0; 115module_param (ignore_oc, bool, S_IRUGO); 116MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 117 118/* for link power management(LPM) feature */ 119static unsigned int hird; 120module_param(hird, int, S_IRUGO); 121MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us"); 122 123#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 124 125/*-------------------------------------------------------------------------*/ 126 127#include "ehci.h" 128#include "ehci-dbg.c" 129#include "pci-quirks.h" 130 131/*-------------------------------------------------------------------------*/ 132 133static void 134timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) 135{ 136 /* Don't override timeouts which shrink or (later) disable 137 * the async ring; just the I/O watchdog. Note that if a 138 * SHRINK were pending, OFF would never be requested. 139 */ 140 if (timer_pending(&ehci->watchdog) 141 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 142 & ehci->actions)) 143 return; 144 145 if (!test_and_set_bit(action, &ehci->actions)) { 146 unsigned long t; 147 148 switch (action) { 149 case TIMER_IO_WATCHDOG: 150 if (!ehci->need_io_watchdog) 151 return; 152 t = EHCI_IO_JIFFIES; 153 break; 154 case TIMER_ASYNC_OFF: 155 t = EHCI_ASYNC_JIFFIES; 156 break; 157 /* case TIMER_ASYNC_SHRINK: */ 158 default: 159 t = EHCI_SHRINK_JIFFIES; 160 break; 161 } 162 mod_timer(&ehci->watchdog, t + jiffies); 163 } 164} 165 166/*-------------------------------------------------------------------------*/ 167 168/* 169 * handshake - spin reading hc until handshake completes or fails 170 * @ptr: address of hc register to be read 171 * @mask: bits to look at in result of read 172 * @done: value of those bits when handshake succeeds 173 * @usec: timeout in microseconds 174 * 175 * Returns negative errno, or zero on success 176 * 177 * Success happens when the "mask" bits have the specified value (hardware 178 * handshake done). There are two failure modes: "usec" have passed (major 179 * hardware flakeout), or the register reads as all-ones (hardware removed). 180 * 181 * That last failure should_only happen in cases like physical cardbus eject 182 * before driver shutdown. But it also seems to be caused by bugs in cardbus 183 * bridge shutdown: shutting down the bridge before the devices using it. 184 */ 185static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, 186 u32 mask, u32 done, int usec) 187{ 188 u32 result; 189 190 do { 191 result = ehci_readl(ehci, ptr); 192 if (result == ~(u32)0) /* card removed */ 193 return -ENODEV; 194 result &= mask; 195 if (result == done) 196 return 0; 197 udelay (1); 198 usec--; 199 } while (usec > 0); 200 return -ETIMEDOUT; 201} 202 203/* check TDI/ARC silicon is in host mode */ 204static int tdi_in_host_mode (struct ehci_hcd *ehci) 205{ 206 u32 __iomem *reg_ptr; 207 u32 tmp; 208 209 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 210 tmp = ehci_readl(ehci, reg_ptr); 211 return (tmp & 3) == USBMODE_CM_HC; 212} 213 214/* force HC to halt state from unknown (EHCI spec section 2.3) */ 215static int ehci_halt (struct ehci_hcd *ehci) 216{ 217 u32 temp = ehci_readl(ehci, &ehci->regs->status); 218 219 /* disable any irqs left enabled by previous code */ 220 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 221 222 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { 223 return 0; 224 } 225 226 if ((temp & STS_HALT) != 0) 227 return 0; 228 229 temp = ehci_readl(ehci, &ehci->regs->command); 230 temp &= ~CMD_RUN; 231 ehci_writel(ehci, temp, &ehci->regs->command); 232 return handshake (ehci, &ehci->regs->status, 233 STS_HALT, STS_HALT, 16 * 125); 234} 235 236#if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3) 237 238/* 239 * The EHCI controller of the Cell Super Companion Chip used in the 240 * PS3 will stop the root hub after all root hub ports are suspended. 241 * When in this condition handshake will return -ETIMEDOUT. The 242 * STS_HLT bit will not be set, so inspection of the frame index is 243 * used here to test for the condition. If the condition is found 244 * return success to allow the USB suspend to complete. 245 */ 246 247static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, 248 void __iomem *ptr, u32 mask, u32 done, 249 int usec) 250{ 251 unsigned int old_index; 252 int error; 253 254 if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) 255 return -ETIMEDOUT; 256 257 old_index = ehci_read_frame_index(ehci); 258 259 error = handshake(ehci, ptr, mask, done, usec); 260 261 if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index) 262 return 0; 263 264 return error; 265} 266 267#else 268 269static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, 270 void __iomem *ptr, u32 mask, u32 done, 271 int usec) 272{ 273 return -ETIMEDOUT; 274} 275 276#endif 277 278static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, 279 u32 mask, u32 done, int usec) 280{ 281 int error; 282 283 error = handshake(ehci, ptr, mask, done, usec); 284 if (error == -ETIMEDOUT) 285 error = handshake_for_broken_root_hub(ehci, ptr, mask, done, 286 usec); 287 288 if (error) { 289 ehci_halt(ehci); 290 ehci->rh_state = EHCI_RH_HALTED; 291 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", 292 ptr, mask, done, error); 293 } 294 295 return error; 296} 297 298/* put TDI/ARC silicon into EHCI mode */ 299static void tdi_reset (struct ehci_hcd *ehci) 300{ 301 u32 __iomem *reg_ptr; 302 u32 tmp; 303 304 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 305 tmp = ehci_readl(ehci, reg_ptr); 306 tmp |= USBMODE_CM_HC; 307 /* The default byte access to MMR space is LE after 308 * controller reset. Set the required endian mode 309 * for transfer buffers to match the host microprocessor 310 */ 311 if (ehci_big_endian_mmio(ehci)) 312 tmp |= USBMODE_BE; 313 ehci_writel(ehci, tmp, reg_ptr); 314} 315 316/* reset a non-running (STS_HALT == 1) controller */ 317static int ehci_reset (struct ehci_hcd *ehci) 318{ 319 int retval; 320 u32 command = ehci_readl(ehci, &ehci->regs->command); 321 322 /* If the EHCI debug controller is active, special care must be 323 * taken before and after a host controller reset */ 324 if (ehci->debug && !dbgp_reset_prep()) 325 ehci->debug = NULL; 326 327 command |= CMD_RESET; 328 dbg_cmd (ehci, "reset", command); 329 ehci_writel(ehci, command, &ehci->regs->command); 330 ehci->rh_state = EHCI_RH_HALTED; 331 ehci->next_statechange = jiffies; 332 retval = handshake (ehci, &ehci->regs->command, 333 CMD_RESET, 0, 250 * 1000); 334 335 if (ehci->has_hostpc) { 336 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 337 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 338 ehci_writel(ehci, TXFIFO_DEFAULT, 339 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); 340 } 341 if (retval) 342 return retval; 343 344 if (ehci_is_TDI(ehci)) 345 tdi_reset (ehci); 346 347 if (ehci->debug) 348 dbgp_external_startup(); 349 350 ehci->port_c_suspend = ehci->suspended_ports = 351 ehci->resuming_ports = 0; 352 return retval; 353} 354 355/* idle the controller (from running) */ 356static void ehci_quiesce (struct ehci_hcd *ehci) 357{ 358 u32 temp; 359 360#ifdef DEBUG 361 if (ehci->rh_state != EHCI_RH_RUNNING) 362 BUG (); 363#endif 364 365 /* wait for any schedule enables/disables to take effect */ 366 temp = ehci_readl(ehci, &ehci->regs->command) << 10; 367 temp &= STS_ASS | STS_PSS; 368 if (handshake_on_error_set_halt(ehci, &ehci->regs->status, 369 STS_ASS | STS_PSS, temp, 16 * 125)) 370 return; 371 372 /* then disable anything that's still active */ 373 temp = ehci_readl(ehci, &ehci->regs->command); 374 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 375 ehci_writel(ehci, temp, &ehci->regs->command); 376 377 /* hardware can take 16 microframes to turn off ... */ 378 handshake_on_error_set_halt(ehci, &ehci->regs->status, 379 STS_ASS | STS_PSS, 0, 16 * 125); 380} 381 382/*-------------------------------------------------------------------------*/ 383 384static void end_unlink_async(struct ehci_hcd *ehci); 385static void ehci_work(struct ehci_hcd *ehci); 386 387#include "ehci-hub.c" 388#include "ehci-lpm.c" 389#include "ehci-mem.c" 390#include "ehci-q.c" 391#include "ehci-sched.c" 392#include "ehci-sysfs.c" 393 394/*-------------------------------------------------------------------------*/ 395 396static void ehci_iaa_watchdog(unsigned long param) 397{ 398 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 399 unsigned long flags; 400 401 spin_lock_irqsave (&ehci->lock, flags); 402 403 /* Lost IAA irqs wedge things badly; seen first with a vt8235. 404 * So we need this watchdog, but must protect it against both 405 * (a) SMP races against real IAA firing and retriggering, and 406 * (b) clean HC shutdown, when IAA watchdog was pending. 407 */ 408 if (ehci->reclaim 409 && !timer_pending(&ehci->iaa_watchdog) 410 && ehci->rh_state == EHCI_RH_RUNNING) { 411 u32 cmd, status; 412 413 /* If we get here, IAA is *REALLY* late. It's barely 414 * conceivable that the system is so busy that CMD_IAAD 415 * is still legitimately set, so let's be sure it's 416 * clear before we read STS_IAA. (The HC should clear 417 * CMD_IAAD when it sets STS_IAA.) 418 */ 419 cmd = ehci_readl(ehci, &ehci->regs->command); 420 if (cmd & CMD_IAAD) 421 ehci_writel(ehci, cmd & ~CMD_IAAD, 422 &ehci->regs->command); 423 424 /* If IAA is set here it either legitimately triggered 425 * before we cleared IAAD above (but _way_ late, so we'll 426 * still count it as lost) ... or a silicon erratum: 427 * - VIA seems to set IAA without triggering the IRQ; 428 * - IAAD potentially cleared without setting IAA. 429 */ 430 status = ehci_readl(ehci, &ehci->regs->status); 431 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { 432 COUNT (ehci->stats.lost_iaa); 433 ehci_writel(ehci, STS_IAA, &ehci->regs->status); 434 } 435 436 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", 437 status, cmd); 438 end_unlink_async(ehci); 439 } 440 441 spin_unlock_irqrestore(&ehci->lock, flags); 442} 443 444static void ehci_watchdog(unsigned long param) 445{ 446 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 447 unsigned long flags; 448 449 spin_lock_irqsave(&ehci->lock, flags); 450 451 /* stop async processing after it's idled a bit */ 452 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 453 start_unlink_async (ehci, ehci->async); 454 455 /* ehci could run by timer, without IRQs ... */ 456 ehci_work (ehci); 457 458 spin_unlock_irqrestore (&ehci->lock, flags); 459} 460 461/* On some systems, leaving remote wakeup enabled prevents system shutdown. 462 * The firmware seems to think that powering off is a wakeup event! 463 * This routine turns off remote wakeup and everything else, on all ports. 464 */ 465static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 466{ 467 int port = HCS_N_PORTS(ehci->hcs_params); 468 469 while (port--) 470 ehci_writel(ehci, PORT_RWC_BITS, 471 &ehci->regs->port_status[port]); 472} 473 474/* 475 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 476 * Should be called with ehci->lock held. 477 */ 478static void ehci_silence_controller(struct ehci_hcd *ehci) 479{ 480 ehci_halt(ehci); 481 ehci_turn_off_all_ports(ehci); 482 483 /* make BIOS/etc use companion controller during reboot */ 484 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 485 486 /* unblock posted writes */ 487 ehci_readl(ehci, &ehci->regs->configured_flag); 488} 489 490/* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 491 * This forcibly disables dma and IRQs, helping kexec and other cases 492 * where the next system software may expect clean state. 493 */ 494static void ehci_shutdown(struct usb_hcd *hcd) 495{ 496 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 497 498 del_timer_sync(&ehci->watchdog); 499 del_timer_sync(&ehci->iaa_watchdog); 500 501 spin_lock_irq(&ehci->lock); 502 ehci_silence_controller(ehci); 503 spin_unlock_irq(&ehci->lock); 504} 505 506static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 507{ 508 unsigned port; 509 510 if (!HCS_PPC (ehci->hcs_params)) 511 return; 512 513 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 514 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 515 (void) ehci_hub_control(ehci_to_hcd(ehci), 516 is_on ? SetPortFeature : ClearPortFeature, 517 USB_PORT_FEAT_POWER, 518 port--, NULL, 0); 519 /* Flush those writes */ 520 ehci_readl(ehci, &ehci->regs->command); 521 msleep(20); 522} 523 524/*-------------------------------------------------------------------------*/ 525 526/* 527 * ehci_work is called from some interrupts, timers, and so on. 528 * it calls driver completion functions, after dropping ehci->lock. 529 */ 530static void ehci_work (struct ehci_hcd *ehci) 531{ 532 timer_action_done (ehci, TIMER_IO_WATCHDOG); 533 534 /* another CPU may drop ehci->lock during a schedule scan while 535 * it reports urb completions. this flag guards against bogus 536 * attempts at re-entrant schedule scanning. 537 */ 538 if (ehci->scanning) 539 return; 540 ehci->scanning = 1; 541 scan_async (ehci); 542 if (ehci->next_uframe != -1) 543 scan_periodic (ehci); 544 ehci->scanning = 0; 545 546 /* the IO watchdog guards against hardware or driver bugs that 547 * misplace IRQs, and should let us run completely without IRQs. 548 * such lossage has been observed on both VT6202 and VT8235. 549 */ 550 if (ehci->rh_state == EHCI_RH_RUNNING && 551 (ehci->async->qh_next.ptr != NULL || 552 ehci->periodic_sched != 0)) 553 timer_action (ehci, TIMER_IO_WATCHDOG); 554} 555 556/* 557 * Called when the ehci_hcd module is removed. 558 */ 559static void ehci_stop (struct usb_hcd *hcd) 560{ 561 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 562 563 ehci_dbg (ehci, "stop\n"); 564 565 /* no more interrupts ... */ 566 del_timer_sync (&ehci->watchdog); 567 del_timer_sync(&ehci->iaa_watchdog); 568 569 spin_lock_irq(&ehci->lock); 570 if (ehci->rh_state == EHCI_RH_RUNNING) 571 ehci_quiesce (ehci); 572 573 ehci_silence_controller(ehci); 574 ehci_reset (ehci); 575 spin_unlock_irq(&ehci->lock); 576 577 remove_sysfs_files(ehci); 578 remove_debug_files (ehci); 579 580 /* root hub is shut down separately (first, when possible) */ 581 spin_lock_irq (&ehci->lock); 582 if (ehci->async) 583 ehci_work (ehci); 584 spin_unlock_irq (&ehci->lock); 585 ehci_mem_cleanup (ehci); 586 587 if (ehci->amd_pll_fix == 1) 588 usb_amd_dev_put(); 589 590#ifdef EHCI_STATS 591 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 592 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 593 ehci->stats.lost_iaa); 594 ehci_dbg (ehci, "complete %ld unlink %ld\n", 595 ehci->stats.complete, ehci->stats.unlink); 596#endif 597 598 dbg_status (ehci, "ehci_stop completed", 599 ehci_readl(ehci, &ehci->regs->status)); 600} 601 602/* one-time init, only for memory state */ 603static int ehci_init(struct usb_hcd *hcd) 604{ 605 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 606 u32 temp; 607 int retval; 608 u32 hcc_params; 609 struct ehci_qh_hw *hw; 610 611 spin_lock_init(&ehci->lock); 612 613 /* 614 * keep io watchdog by default, those good HCDs could turn off it later 615 */ 616 ehci->need_io_watchdog = 1; 617 init_timer(&ehci->watchdog); 618 ehci->watchdog.function = ehci_watchdog; 619 ehci->watchdog.data = (unsigned long) ehci; 620 621 init_timer(&ehci->iaa_watchdog); 622 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 623 ehci->iaa_watchdog.data = (unsigned long) ehci; 624 625 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 626 627 /* 628 * by default set standard 80% (== 100 usec/uframe) max periodic 629 * bandwidth as required by USB 2.0 630 */ 631 ehci->uframe_periodic_max = 100; 632 633 /* 634 * hw default: 1K periodic list heads, one per frame. 635 * periodic_size can shrink by USBCMD update if hcc_params allows. 636 */ 637 ehci->periodic_size = DEFAULT_I_TDPS; 638 INIT_LIST_HEAD(&ehci->cached_itd_list); 639 INIT_LIST_HEAD(&ehci->cached_sitd_list); 640 641 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 642 /* periodic schedule size can be smaller than default */ 643 switch (EHCI_TUNE_FLS) { 644 case 0: ehci->periodic_size = 1024; break; 645 case 1: ehci->periodic_size = 512; break; 646 case 2: ehci->periodic_size = 256; break; 647 default: BUG(); 648 } 649 } 650 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 651 return retval; 652 653 /* controllers may cache some of the periodic schedule ... */ 654 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 655 ehci->i_thresh = 2 + 8; 656 else // N microframes cached 657 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 658 659 ehci->reclaim = NULL; 660 ehci->next_uframe = -1; 661 ehci->clock_frame = -1; 662 663 /* 664 * dedicate a qh for the async ring head, since we couldn't unlink 665 * a 'real' qh without stopping the async schedule [4.8]. use it 666 * as the 'reclamation list head' too. 667 * its dummy is used in hw_alt_next of many tds, to prevent the qh 668 * from automatically advancing to the next td after short reads. 669 */ 670 ehci->async->qh_next.qh = NULL; 671 hw = ehci->async->hw; 672 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 673 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 674 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */ 675 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 676 hw->hw_qtd_next = EHCI_LIST_END(ehci); 677 ehci->async->qh_state = QH_STATE_LINKED; 678 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 679 680 /* clear interrupt enables, set irq latency */ 681 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 682 log2_irq_thresh = 0; 683 temp = 1 << (16 + log2_irq_thresh); 684 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 685 ehci->has_ppcd = 1; 686 ehci_dbg(ehci, "enable per-port change event\n"); 687 temp |= CMD_PPCEE; 688 } 689 if (HCC_CANPARK(hcc_params)) { 690 /* HW default park == 3, on hardware that supports it (like 691 * NVidia and ALI silicon), maximizes throughput on the async 692 * schedule by avoiding QH fetches between transfers. 693 * 694 * With fast usb storage devices and NForce2, "park" seems to 695 * make problems: throughput reduction (!), data errors... 696 */ 697 if (park) { 698 park = min(park, (unsigned) 3); 699 temp |= CMD_PARK; 700 temp |= park << 8; 701 } 702 ehci_dbg(ehci, "park %d\n", park); 703 } 704 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 705 /* periodic schedule size can be smaller than default */ 706 temp &= ~(3 << 2); 707 temp |= (EHCI_TUNE_FLS << 2); 708 } 709 if (HCC_LPM(hcc_params)) { 710 /* support link power management EHCI 1.1 addendum */ 711 ehci_dbg(ehci, "support lpm\n"); 712 ehci->has_lpm = 1; 713 if (hird > 0xf) { 714 ehci_dbg(ehci, "hird %d invalid, use default 0", 715 hird); 716 hird = 0; 717 } 718 temp |= hird << 24; 719 } 720 ehci->command = temp; 721 722 /* Accept arbitrarily long scatter-gather lists */ 723 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 724 hcd->self.sg_tablesize = ~0; 725 return 0; 726} 727 728/* start HC running; it's halted, ehci_init() has been run (once) */ 729static int ehci_run (struct usb_hcd *hcd) 730{ 731 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 732 u32 temp; 733 u32 hcc_params; 734 735 hcd->uses_new_polling = 1; 736 737 /* EHCI spec section 4.1 */ 738 739 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 740 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 741 742 /* 743 * hcc_params controls whether ehci->regs->segment must (!!!) 744 * be used; it constrains QH/ITD/SITD and QTD locations. 745 * pci_pool consistent memory always uses segment zero. 746 * streaming mappings for I/O buffers, like pci_map_single(), 747 * can return segments above 4GB, if the device allows. 748 * 749 * NOTE: the dma mask is visible through dma_supported(), so 750 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 751 * Scsi_Host.highmem_io, and so forth. It's readonly to all 752 * host side drivers though. 753 */ 754 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 755 if (HCC_64BIT_ADDR(hcc_params)) { 756 ehci_writel(ehci, 0, &ehci->regs->segment); 757#if 0 758// this is deeply broken on almost all architectures 759 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) 760 ehci_info(ehci, "enabled 64bit DMA\n"); 761#endif 762 } 763 764 765 // Philips, Intel, and maybe others need CMD_RUN before the 766 // root hub will detect new devices (why?); NEC doesn't 767 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 768 ehci->command |= CMD_RUN; 769 ehci_writel(ehci, ehci->command, &ehci->regs->command); 770 dbg_cmd (ehci, "init", ehci->command); 771 772 /* 773 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 774 * are explicitly handed to companion controller(s), so no TT is 775 * involved with the root hub. (Except where one is integrated, 776 * and there's no companion controller unless maybe for USB OTG.) 777 * 778 * Turning on the CF flag will transfer ownership of all ports 779 * from the companions to the EHCI controller. If any of the 780 * companions are in the middle of a port reset at the time, it 781 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 782 * guarantees that no resets are in progress. After we set CF, 783 * a short delay lets the hardware catch up; new resets shouldn't 784 * be started before the port switching actions could complete. 785 */ 786 down_write(&ehci_cf_port_reset_rwsem); 787 ehci->rh_state = EHCI_RH_RUNNING; 788 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 789 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 790 msleep(5); 791 up_write(&ehci_cf_port_reset_rwsem); 792 ehci->last_periodic_enable = ktime_get_real(); 793 794 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 795 ehci_info (ehci, 796 "USB %x.%x started, EHCI %x.%02x%s\n", 797 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 798 temp >> 8, temp & 0xff, 799 ignore_oc ? ", overcurrent ignored" : ""); 800 801 ehci_writel(ehci, INTR_MASK, 802 &ehci->regs->intr_enable); /* Turn On Interrupts */ 803 804 /* GRR this is run-once init(), being done every time the HC starts. 805 * So long as they're part of class devices, we can't do it init() 806 * since the class device isn't created that early. 807 */ 808 create_debug_files(ehci); 809 create_sysfs_files(ehci); 810 811 return 0; 812} 813 814static int __maybe_unused ehci_setup (struct usb_hcd *hcd) 815{ 816 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 817 int retval; 818 819 ehci->regs = (void __iomem *)ehci->caps + 820 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 821 dbg_hcs_params(ehci, "reset"); 822 dbg_hcc_params(ehci, "reset"); 823 824 /* cache this readonly data; minimize chip reads */ 825 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 826 827 ehci->sbrn = HCD_USB2; 828 829 retval = ehci_halt(ehci); 830 if (retval) 831 return retval; 832 833 /* data structure init */ 834 retval = ehci_init(hcd); 835 if (retval) 836 return retval; 837 838 ehci_reset(ehci); 839 840 return 0; 841} 842 843/*-------------------------------------------------------------------------*/ 844 845static irqreturn_t ehci_irq (struct usb_hcd *hcd) 846{ 847 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 848 u32 status, masked_status, pcd_status = 0, cmd; 849 int bh; 850 851 spin_lock (&ehci->lock); 852 853 status = ehci_readl(ehci, &ehci->regs->status); 854 855 /* e.g. cardbus physical eject */ 856 if (status == ~(u32) 0) { 857 ehci_dbg (ehci, "device removed\n"); 858 goto dead; 859 } 860 861 /* Shared IRQ? */ 862 masked_status = status & INTR_MASK; 863 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { 864 spin_unlock(&ehci->lock); 865 return IRQ_NONE; 866 } 867 868 /* clear (just) interrupts */ 869 ehci_writel(ehci, masked_status, &ehci->regs->status); 870 cmd = ehci_readl(ehci, &ehci->regs->command); 871 bh = 0; 872 873#ifdef VERBOSE_DEBUG 874 /* unrequested/ignored: Frame List Rollover */ 875 dbg_status (ehci, "irq", status); 876#endif 877 878 /* INT, ERR, and IAA interrupt rates can be throttled */ 879 880 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 881 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 882 if (likely ((status & STS_ERR) == 0)) 883 COUNT (ehci->stats.normal); 884 else 885 COUNT (ehci->stats.error); 886 bh = 1; 887 } 888 889 /* complete the unlinking of some qh [4.15.2.3] */ 890 if (status & STS_IAA) { 891 /* guard against (alleged) silicon errata */ 892 if (cmd & CMD_IAAD) { 893 ehci_writel(ehci, cmd & ~CMD_IAAD, 894 &ehci->regs->command); 895 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 896 } 897 if (ehci->reclaim) { 898 COUNT(ehci->stats.reclaim); 899 end_unlink_async(ehci); 900 } else 901 ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); 902 } 903 904 /* remote wakeup [4.3.1] */ 905 if (status & STS_PCD) { 906 unsigned i = HCS_N_PORTS (ehci->hcs_params); 907 u32 ppcd = 0; 908 909 /* kick root hub later */ 910 pcd_status = status; 911 912 /* resume root hub? */ 913 if (ehci->rh_state == EHCI_RH_SUSPENDED) 914 usb_hcd_resume_root_hub(hcd); 915 916 /* get per-port change detect bits */ 917 if (ehci->has_ppcd) 918 ppcd = status >> 16; 919 920 while (i--) { 921 int pstatus; 922 923 /* leverage per-port change bits feature */ 924 if (ehci->has_ppcd && !(ppcd & (1 << i))) 925 continue; 926 pstatus = ehci_readl(ehci, 927 &ehci->regs->port_status[i]); 928 929 if (pstatus & PORT_OWNER) 930 continue; 931 if (!(test_bit(i, &ehci->suspended_ports) && 932 ((pstatus & PORT_RESUME) || 933 !(pstatus & PORT_SUSPEND)) && 934 (pstatus & PORT_PE) && 935 ehci->reset_done[i] == 0)) 936 continue; 937 938 /* start 20 msec resume signaling from this port, 939 * and make khubd collect PORT_STAT_C_SUSPEND to 940 * stop that signaling. Use 5 ms extra for safety, 941 * like usb_port_resume() does. 942 */ 943 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); 944 set_bit(i, &ehci->resuming_ports); 945 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 946 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 947 } 948 } 949 950 /* PCI errors [4.15.2.4] */ 951 if (unlikely ((status & STS_FATAL) != 0)) { 952 ehci_err(ehci, "fatal error\n"); 953 dbg_cmd(ehci, "fatal", cmd); 954 dbg_status(ehci, "fatal", status); 955 ehci_halt(ehci); 956dead: 957 ehci_reset(ehci); 958 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 959 usb_hc_died(hcd); 960 /* generic layer kills/unlinks all urbs, then 961 * uses ehci_stop to clean up the rest 962 */ 963 bh = 1; 964 } 965 966 if (bh) 967 ehci_work (ehci); 968 spin_unlock (&ehci->lock); 969 if (pcd_status) 970 usb_hcd_poll_rh_status(hcd); 971 return IRQ_HANDLED; 972} 973 974/*-------------------------------------------------------------------------*/ 975 976/* 977 * non-error returns are a promise to giveback() the urb later 978 * we drop ownership so next owner (or urb unlink) can get it 979 * 980 * urb + dev is in hcd.self.controller.urb_list 981 * we're queueing TDs onto software and hardware lists 982 * 983 * hcd-specific init for hcpriv hasn't been done yet 984 * 985 * NOTE: control, bulk, and interrupt share the same code to append TDs 986 * to a (possibly active) QH, and the same QH scanning code. 987 */ 988static int ehci_urb_enqueue ( 989 struct usb_hcd *hcd, 990 struct urb *urb, 991 gfp_t mem_flags 992) { 993 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 994 struct list_head qtd_list; 995 996 INIT_LIST_HEAD (&qtd_list); 997 998 switch (usb_pipetype (urb->pipe)) { 999 case PIPE_CONTROL: 1000 /* qh_completions() code doesn't handle all the fault cases 1001 * in multi-TD control transfers. Even 1KB is rare anyway. 1002 */ 1003 if (urb->transfer_buffer_length > (16 * 1024)) 1004 return -EMSGSIZE; 1005 /* FALLTHROUGH */ 1006 /* case PIPE_BULK: */ 1007 default: 1008 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 1009 return -ENOMEM; 1010 return submit_async(ehci, urb, &qtd_list, mem_flags); 1011 1012 case PIPE_INTERRUPT: 1013 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 1014 return -ENOMEM; 1015 return intr_submit(ehci, urb, &qtd_list, mem_flags); 1016 1017 case PIPE_ISOCHRONOUS: 1018 if (urb->dev->speed == USB_SPEED_HIGH) 1019 return itd_submit (ehci, urb, mem_flags); 1020 else 1021 return sitd_submit (ehci, urb, mem_flags); 1022 } 1023} 1024 1025static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 1026{ 1027 /* failfast */ 1028 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim) 1029 end_unlink_async(ehci); 1030 1031 /* If the QH isn't linked then there's nothing we can do 1032 * unless we were called during a giveback, in which case 1033 * qh_completions() has to deal with it. 1034 */ 1035 if (qh->qh_state != QH_STATE_LINKED) { 1036 if (qh->qh_state == QH_STATE_COMPLETING) 1037 qh->needs_rescan = 1; 1038 return; 1039 } 1040 1041 /* defer till later if busy */ 1042 if (ehci->reclaim) { 1043 struct ehci_qh *last; 1044 1045 for (last = ehci->reclaim; 1046 last->reclaim; 1047 last = last->reclaim) 1048 continue; 1049 qh->qh_state = QH_STATE_UNLINK_WAIT; 1050 last->reclaim = qh; 1051 1052 /* start IAA cycle */ 1053 } else 1054 start_unlink_async (ehci, qh); 1055} 1056 1057/* remove from hardware lists 1058 * completions normally happen asynchronously 1059 */ 1060 1061static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 1062{ 1063 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1064 struct ehci_qh *qh; 1065 unsigned long flags; 1066 int rc; 1067 1068 spin_lock_irqsave (&ehci->lock, flags); 1069 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 1070 if (rc) 1071 goto done; 1072 1073 switch (usb_pipetype (urb->pipe)) { 1074 // case PIPE_CONTROL: 1075 // case PIPE_BULK: 1076 default: 1077 qh = (struct ehci_qh *) urb->hcpriv; 1078 if (!qh) 1079 break; 1080 switch (qh->qh_state) { 1081 case QH_STATE_LINKED: 1082 case QH_STATE_COMPLETING: 1083 unlink_async(ehci, qh); 1084 break; 1085 case QH_STATE_UNLINK: 1086 case QH_STATE_UNLINK_WAIT: 1087 /* already started */ 1088 break; 1089 case QH_STATE_IDLE: 1090 /* QH might be waiting for a Clear-TT-Buffer */ 1091 qh_completions(ehci, qh); 1092 break; 1093 } 1094 break; 1095 1096 case PIPE_INTERRUPT: 1097 qh = (struct ehci_qh *) urb->hcpriv; 1098 if (!qh) 1099 break; 1100 switch (qh->qh_state) { 1101 case QH_STATE_LINKED: 1102 case QH_STATE_COMPLETING: 1103 intr_deschedule (ehci, qh); 1104 break; 1105 case QH_STATE_IDLE: 1106 qh_completions (ehci, qh); 1107 break; 1108 default: 1109 ehci_dbg (ehci, "bogus qh %p state %d\n", 1110 qh, qh->qh_state); 1111 goto done; 1112 } 1113 break; 1114 1115 case PIPE_ISOCHRONOUS: 1116 // itd or sitd ... 1117 1118 // wait till next completion, do it then. 1119 // completion irqs can wait up to 1024 msec, 1120 break; 1121 } 1122done: 1123 spin_unlock_irqrestore (&ehci->lock, flags); 1124 return rc; 1125} 1126 1127/*-------------------------------------------------------------------------*/ 1128 1129// bulk qh holds the data toggle 1130 1131static void 1132ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1133{ 1134 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1135 unsigned long flags; 1136 struct ehci_qh *qh, *tmp; 1137 1138 /* ASSERT: any requests/urbs are being unlinked */ 1139 /* ASSERT: nobody can be submitting urbs for this any more */ 1140 1141rescan: 1142 spin_lock_irqsave (&ehci->lock, flags); 1143 qh = ep->hcpriv; 1144 if (!qh) 1145 goto done; 1146 1147 /* endpoints can be iso streams. for now, we don't 1148 * accelerate iso completions ... so spin a while. 1149 */ 1150 if (qh->hw == NULL) { 1151 ehci_vdbg (ehci, "iso delay\n"); 1152 goto idle_timeout; 1153 } 1154 1155 if (ehci->rh_state != EHCI_RH_RUNNING) 1156 qh->qh_state = QH_STATE_IDLE; 1157 switch (qh->qh_state) { 1158 case QH_STATE_LINKED: 1159 case QH_STATE_COMPLETING: 1160 for (tmp = ehci->async->qh_next.qh; 1161 tmp && tmp != qh; 1162 tmp = tmp->qh_next.qh) 1163 continue; 1164 /* periodic qh self-unlinks on empty, and a COMPLETING qh 1165 * may already be unlinked. 1166 */ 1167 if (tmp) 1168 unlink_async(ehci, qh); 1169 /* FALL THROUGH */ 1170 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1171 case QH_STATE_UNLINK_WAIT: 1172idle_timeout: 1173 spin_unlock_irqrestore (&ehci->lock, flags); 1174 schedule_timeout_uninterruptible(1); 1175 goto rescan; 1176 case QH_STATE_IDLE: /* fully unlinked */ 1177 if (qh->clearing_tt) 1178 goto idle_timeout; 1179 if (list_empty (&qh->qtd_list)) { 1180 qh_put (qh); 1181 break; 1182 } 1183 /* else FALL THROUGH */ 1184 default: 1185 /* caller was supposed to have unlinked any requests; 1186 * that's not our job. just leak this memory. 1187 */ 1188 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1189 qh, ep->desc.bEndpointAddress, qh->qh_state, 1190 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1191 break; 1192 } 1193 ep->hcpriv = NULL; 1194done: 1195 spin_unlock_irqrestore (&ehci->lock, flags); 1196} 1197 1198static void 1199ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1200{ 1201 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1202 struct ehci_qh *qh; 1203 int eptype = usb_endpoint_type(&ep->desc); 1204 int epnum = usb_endpoint_num(&ep->desc); 1205 int is_out = usb_endpoint_dir_out(&ep->desc); 1206 unsigned long flags; 1207 1208 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1209 return; 1210 1211 spin_lock_irqsave(&ehci->lock, flags); 1212 qh = ep->hcpriv; 1213 1214 /* For Bulk and Interrupt endpoints we maintain the toggle state 1215 * in the hardware; the toggle bits in udev aren't used at all. 1216 * When an endpoint is reset by usb_clear_halt() we must reset 1217 * the toggle bit in the QH. 1218 */ 1219 if (qh) { 1220 usb_settoggle(qh->dev, epnum, is_out, 0); 1221 if (!list_empty(&qh->qtd_list)) { 1222 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1223 } else if (qh->qh_state == QH_STATE_LINKED || 1224 qh->qh_state == QH_STATE_COMPLETING) { 1225 1226 /* The toggle value in the QH can't be updated 1227 * while the QH is active. Unlink it now; 1228 * re-linking will call qh_refresh(). 1229 */ 1230 if (eptype == USB_ENDPOINT_XFER_BULK) 1231 unlink_async(ehci, qh); 1232 else 1233 intr_deschedule(ehci, qh); 1234 } 1235 } 1236 spin_unlock_irqrestore(&ehci->lock, flags); 1237} 1238 1239static int ehci_get_frame (struct usb_hcd *hcd) 1240{ 1241 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1242 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; 1243} 1244 1245/*-------------------------------------------------------------------------*/ 1246 1247MODULE_DESCRIPTION(DRIVER_DESC); 1248MODULE_AUTHOR (DRIVER_AUTHOR); 1249MODULE_LICENSE ("GPL"); 1250 1251#ifdef CONFIG_PCI 1252#include "ehci-pci.c" 1253#define PCI_DRIVER ehci_pci_driver 1254#endif 1255 1256#ifdef CONFIG_USB_EHCI_FSL 1257#include "ehci-fsl.c" 1258#define PLATFORM_DRIVER ehci_fsl_driver 1259#endif 1260 1261#ifdef CONFIG_USB_EHCI_MXC 1262#include "ehci-mxc.c" 1263#define PLATFORM_DRIVER ehci_mxc_driver 1264#endif 1265 1266#ifdef CONFIG_USB_EHCI_SH 1267#include "ehci-sh.c" 1268#define PLATFORM_DRIVER ehci_hcd_sh_driver 1269#endif 1270 1271#ifdef CONFIG_MIPS_ALCHEMY 1272#include "ehci-au1xxx.c" 1273#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 1274#endif 1275 1276#ifdef CONFIG_USB_EHCI_HCD_OMAP 1277#include "ehci-omap.c" 1278#define PLATFORM_DRIVER ehci_hcd_omap_driver 1279#endif 1280 1281#ifdef CONFIG_PPC_PS3 1282#include "ehci-ps3.c" 1283#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1284#endif 1285 1286#ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1287#include "ehci-ppc-of.c" 1288#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1289#endif 1290 1291#ifdef CONFIG_XPS_USB_HCD_XILINX 1292#include "ehci-xilinx-of.c" 1293#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1294#endif 1295 1296#ifdef CONFIG_PLAT_ORION 1297#include "ehci-orion.c" 1298#define PLATFORM_DRIVER ehci_orion_driver 1299#endif 1300 1301#ifdef CONFIG_ARCH_IXP4XX 1302#include "ehci-ixp4xx.c" 1303#define PLATFORM_DRIVER ixp4xx_ehci_driver 1304#endif 1305 1306#ifdef CONFIG_USB_W90X900_EHCI 1307#include "ehci-w90x900.c" 1308#define PLATFORM_DRIVER ehci_hcd_w90x900_driver 1309#endif 1310 1311#ifdef CONFIG_ARCH_AT91 1312#include "ehci-atmel.c" 1313#define PLATFORM_DRIVER ehci_atmel_driver 1314#endif 1315 1316#ifdef CONFIG_USB_OCTEON_EHCI 1317#include "ehci-octeon.c" 1318#define PLATFORM_DRIVER ehci_octeon_driver 1319#endif 1320 1321#ifdef CONFIG_USB_CNS3XXX_EHCI 1322#include "ehci-cns3xxx.c" 1323#define PLATFORM_DRIVER cns3xxx_ehci_driver 1324#endif 1325 1326#ifdef CONFIG_ARCH_VT8500 1327#include "ehci-vt8500.c" 1328#define PLATFORM_DRIVER vt8500_ehci_driver 1329#endif 1330 1331#ifdef CONFIG_PLAT_SPEAR 1332#include "ehci-spear.c" 1333#define PLATFORM_DRIVER spear_ehci_hcd_driver 1334#endif 1335 1336#ifdef CONFIG_USB_EHCI_MSM 1337#include "ehci-msm.c" 1338#define PLATFORM_DRIVER ehci_msm_driver 1339#endif 1340 1341#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP 1342#include "ehci-pmcmsp.c" 1343#define PLATFORM_DRIVER ehci_hcd_msp_driver 1344#endif 1345 1346#ifdef CONFIG_USB_EHCI_TEGRA 1347#include "ehci-tegra.c" 1348#define PLATFORM_DRIVER tegra_ehci_driver 1349#endif 1350 1351#ifdef CONFIG_USB_EHCI_S5P 1352#include "ehci-s5p.c" 1353#define PLATFORM_DRIVER s5p_ehci_driver 1354#endif 1355 1356#ifdef CONFIG_SPARC_LEON 1357#include "ehci-grlib.c" 1358#define PLATFORM_DRIVER ehci_grlib_driver 1359#endif 1360 1361#ifdef CONFIG_CPU_XLR 1362#include "ehci-xls.c" 1363#define PLATFORM_DRIVER ehci_xls_driver 1364#endif 1365 1366#ifdef CONFIG_USB_EHCI_MV 1367#include "ehci-mv.c" 1368#define PLATFORM_DRIVER ehci_mv_driver 1369#endif 1370 1371#ifdef CONFIG_MACH_LOONGSON1 1372#include "ehci-ls1x.c" 1373#define PLATFORM_DRIVER ehci_ls1x_driver 1374#endif 1375 1376#ifdef CONFIG_USB_EHCI_HCD_PLATFORM 1377#include "ehci-platform.c" 1378#define PLATFORM_DRIVER ehci_platform_driver 1379#endif 1380 1381#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1382 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1383 !defined(XILINX_OF_PLATFORM_DRIVER) 1384#error "missing bus glue for ehci-hcd" 1385#endif 1386 1387static int __init ehci_hcd_init(void) 1388{ 1389 int retval = 0; 1390 1391 if (usb_disabled()) 1392 return -ENODEV; 1393 1394 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1395 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1396 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1397 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1398 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1399 " before uhci_hcd and ohci_hcd, not after\n"); 1400 1401 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1402 hcd_name, 1403 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1404 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1405 1406#ifdef DEBUG 1407 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1408 if (!ehci_debug_root) { 1409 retval = -ENOENT; 1410 goto err_debug; 1411 } 1412#endif 1413 1414#ifdef PLATFORM_DRIVER 1415 retval = platform_driver_register(&PLATFORM_DRIVER); 1416 if (retval < 0) 1417 goto clean0; 1418#endif 1419 1420#ifdef PCI_DRIVER 1421 retval = pci_register_driver(&PCI_DRIVER); 1422 if (retval < 0) 1423 goto clean1; 1424#endif 1425 1426#ifdef PS3_SYSTEM_BUS_DRIVER 1427 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1428 if (retval < 0) 1429 goto clean2; 1430#endif 1431 1432#ifdef OF_PLATFORM_DRIVER 1433 retval = platform_driver_register(&OF_PLATFORM_DRIVER); 1434 if (retval < 0) 1435 goto clean3; 1436#endif 1437 1438#ifdef XILINX_OF_PLATFORM_DRIVER 1439 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); 1440 if (retval < 0) 1441 goto clean4; 1442#endif 1443 return retval; 1444 1445#ifdef XILINX_OF_PLATFORM_DRIVER 1446 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ 1447clean4: 1448#endif 1449#ifdef OF_PLATFORM_DRIVER 1450 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1451clean3: 1452#endif 1453#ifdef PS3_SYSTEM_BUS_DRIVER 1454 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1455clean2: 1456#endif 1457#ifdef PCI_DRIVER 1458 pci_unregister_driver(&PCI_DRIVER); 1459clean1: 1460#endif 1461#ifdef PLATFORM_DRIVER 1462 platform_driver_unregister(&PLATFORM_DRIVER); 1463clean0: 1464#endif 1465#ifdef DEBUG 1466 debugfs_remove(ehci_debug_root); 1467 ehci_debug_root = NULL; 1468err_debug: 1469#endif 1470 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1471 return retval; 1472} 1473module_init(ehci_hcd_init); 1474 1475static void __exit ehci_hcd_cleanup(void) 1476{ 1477#ifdef XILINX_OF_PLATFORM_DRIVER 1478 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); 1479#endif 1480#ifdef OF_PLATFORM_DRIVER 1481 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1482#endif 1483#ifdef PLATFORM_DRIVER 1484 platform_driver_unregister(&PLATFORM_DRIVER); 1485#endif 1486#ifdef PCI_DRIVER 1487 pci_unregister_driver(&PCI_DRIVER); 1488#endif 1489#ifdef PS3_SYSTEM_BUS_DRIVER 1490 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1491#endif 1492#ifdef DEBUG 1493 debugfs_remove(ehci_debug_root); 1494#endif 1495 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1496} 1497module_exit(ehci_hcd_cleanup); 1498 1499