ehci-pci.c revision 3d091a6f703906c5680855ff29bd94d051c8c6d8
1/* 2 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 3 * 4 * Copyright (c) 2000-2004 by David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21#ifndef CONFIG_PCI 22#error "This file is PCI bus glue. CONFIG_PCI must be defined." 23#endif 24 25/*-------------------------------------------------------------------------*/ 26 27/* called after powerup, by probe or system-pm "wakeup" */ 28static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 29{ 30 int retval; 31 32 /* we expect static quirk code to handle the "extended capabilities" 33 * (currently just BIOS handoff) allowed starting with EHCI 0.96 34 */ 35 36 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 37 retval = pci_set_mwi(pdev); 38 if (!retval) 39 ehci_dbg(ehci, "MWI active\n"); 40 41 return 0; 42} 43 44/* called during probe() after chip reset completes */ 45static int ehci_pci_setup(struct usb_hcd *hcd) 46{ 47 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 48 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 49 struct pci_dev *p_smbus; 50 u8 rev; 51 u32 temp; 52 int retval; 53 54 switch (pdev->vendor) { 55 case PCI_VENDOR_ID_TOSHIBA_2: 56 /* celleb's companion chip */ 57 if (pdev->device == 0x01b5) { 58#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 59 ehci->big_endian_mmio = 1; 60#else 61 ehci_warn(ehci, 62 "unsupported big endian Toshiba quirk\n"); 63#endif 64 } 65 break; 66 } 67 68 ehci->caps = hcd->regs; 69 ehci->regs = hcd->regs + 70 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); 71 72 dbg_hcs_params(ehci, "reset"); 73 dbg_hcc_params(ehci, "reset"); 74 75 /* ehci_init() causes memory for DMA transfers to be 76 * allocated. Thus, any vendor-specific workarounds based on 77 * limiting the type of memory used for DMA transfers must 78 * happen before ehci_init() is called. */ 79 switch (pdev->vendor) { 80 case PCI_VENDOR_ID_NVIDIA: 81 /* NVidia reports that certain chips don't handle 82 * QH, ITD, or SITD addresses above 2GB. (But TD, 83 * data buffer, and periodic schedule are normal.) 84 */ 85 switch (pdev->device) { 86 case 0x003c: /* MCP04 */ 87 case 0x005b: /* CK804 */ 88 case 0x00d8: /* CK8 */ 89 case 0x00e8: /* CK8S */ 90 if (pci_set_consistent_dma_mask(pdev, 91 DMA_BIT_MASK(31)) < 0) 92 ehci_warn(ehci, "can't enable NVidia " 93 "workaround for >2GB RAM\n"); 94 break; 95 } 96 break; 97 } 98 99 /* cache this readonly data; minimize chip reads */ 100 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 101 102 retval = ehci_halt(ehci); 103 if (retval) 104 return retval; 105 106 if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) || 107 (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) { 108 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may 109 * read/write memory space which does not belong to it when 110 * there is NULL pointer with T-bit set to 1 in the frame list 111 * table. To avoid the issue, the frame list link pointer 112 * should always contain a valid pointer to a inactive qh. 113 */ 114 ehci->use_dummy_qh = 1; 115 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI " 116 "dummy qh workaround\n"); 117 } 118 119 /* data structure init */ 120 retval = ehci_init(hcd); 121 if (retval) 122 return retval; 123 124 switch (pdev->vendor) { 125 case PCI_VENDOR_ID_NEC: 126 ehci->need_io_watchdog = 0; 127 break; 128 case PCI_VENDOR_ID_INTEL: 129 ehci->need_io_watchdog = 0; 130 ehci->fs_i_thresh = 1; 131 if (pdev->device == 0x27cc) { 132 ehci->broken_periodic = 1; 133 ehci_info(ehci, "using broken periodic workaround\n"); 134 } 135 if (pdev->device == 0x0806 || pdev->device == 0x0811 136 || pdev->device == 0x0829) { 137 ehci_info(ehci, "disable lpm for langwell/penwell\n"); 138 ehci->has_lpm = 0; 139 } 140 break; 141 case PCI_VENDOR_ID_TDI: 142 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 143 hcd->has_tt = 1; 144 tdi_reset(ehci); 145 } 146 break; 147 case PCI_VENDOR_ID_AMD: 148 /* AMD8111 EHCI doesn't work, according to AMD errata */ 149 if (pdev->device == 0x7463) { 150 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 151 retval = -EIO; 152 goto done; 153 } 154 break; 155 case PCI_VENDOR_ID_NVIDIA: 156 switch (pdev->device) { 157 /* Some NForce2 chips have problems with selective suspend; 158 * fixed in newer silicon. 159 */ 160 case 0x0068: 161 if (pdev->revision < 0xa4) 162 ehci->no_selective_suspend = 1; 163 break; 164 } 165 break; 166 case PCI_VENDOR_ID_VIA: 167 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { 168 u8 tmp; 169 170 /* The VT6212 defaults to a 1 usec EHCI sleep time which 171 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes 172 * that sleep time use the conventional 10 usec. 173 */ 174 pci_read_config_byte(pdev, 0x4b, &tmp); 175 if (tmp & 0x20) 176 break; 177 pci_write_config_byte(pdev, 0x4b, tmp | 0x20); 178 } 179 break; 180 case PCI_VENDOR_ID_ATI: 181 /* SB600 and old version of SB700 have a bug in EHCI controller, 182 * which causes usb devices lose response in some cases. 183 */ 184 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { 185 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 186 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 187 NULL); 188 if (!p_smbus) 189 break; 190 rev = p_smbus->revision; 191 if ((pdev->device == 0x4386) || (rev == 0x3a) 192 || (rev == 0x3b)) { 193 u8 tmp; 194 ehci_info(ehci, "applying AMD SB600/SB700 USB " 195 "freeze workaround\n"); 196 pci_read_config_byte(pdev, 0x53, &tmp); 197 pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); 198 } 199 pci_dev_put(p_smbus); 200 } 201 break; 202 } 203 204 /* optional debug port, normally in the first BAR */ 205 temp = pci_find_capability(pdev, 0x0a); 206 if (temp) { 207 pci_read_config_dword(pdev, temp, &temp); 208 temp >>= 16; 209 if ((temp & (3 << 13)) == (1 << 13)) { 210 temp &= 0x1fff; 211 ehci->debug = ehci_to_hcd(ehci)->regs + temp; 212 temp = ehci_readl(ehci, &ehci->debug->control); 213 ehci_info(ehci, "debug port %d%s\n", 214 HCS_DEBUG_PORT(ehci->hcs_params), 215 (temp & DBGP_ENABLED) 216 ? " IN USE" 217 : ""); 218 if (!(temp & DBGP_ENABLED)) 219 ehci->debug = NULL; 220 } 221 } 222 223 ehci_reset(ehci); 224 225 /* at least the Genesys GL880S needs fixup here */ 226 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 227 temp &= 0x0f; 228 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 229 ehci_dbg(ehci, "bogus port configuration: " 230 "cc=%d x pcc=%d < ports=%d\n", 231 HCS_N_CC(ehci->hcs_params), 232 HCS_N_PCC(ehci->hcs_params), 233 HCS_N_PORTS(ehci->hcs_params)); 234 235 switch (pdev->vendor) { 236 case 0x17a0: /* GENESYS */ 237 /* GL880S: should be PORTS=2 */ 238 temp |= (ehci->hcs_params & ~0xf); 239 ehci->hcs_params = temp; 240 break; 241 case PCI_VENDOR_ID_NVIDIA: 242 /* NF4: should be PCC=10 */ 243 break; 244 } 245 } 246 247 /* Serial Bus Release Number is at PCI 0x60 offset */ 248 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 249 250 /* Keep this around for a while just in case some EHCI 251 * implementation uses legacy PCI PM support. This test 252 * can be removed on 17 Dec 2009 if the dev_warn() hasn't 253 * been triggered by then. 254 */ 255 if (!device_can_wakeup(&pdev->dev)) { 256 u16 port_wake; 257 258 pci_read_config_word(pdev, 0x62, &port_wake); 259 if (port_wake & 0x0001) { 260 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); 261 device_set_wakeup_capable(&pdev->dev, 1); 262 } 263 } 264 265#ifdef CONFIG_USB_SUSPEND 266 /* REVISIT: the controller works fine for wakeup iff the root hub 267 * itself is "globally" suspended, but usbcore currently doesn't 268 * understand such things. 269 * 270 * System suspend currently expects to be able to suspend the entire 271 * device tree, device-at-a-time. If we failed selective suspend 272 * reports, system suspend would fail; so the root hub code must claim 273 * success. That's lying to usbcore, and it matters for runtime 274 * PM scenarios with selective suspend and remote wakeup... 275 */ 276 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) 277 ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); 278#endif 279 280 ehci_port_power(ehci, 1); 281 retval = ehci_pci_reinit(ehci, pdev); 282done: 283 return retval; 284} 285 286/*-------------------------------------------------------------------------*/ 287 288#ifdef CONFIG_PM 289 290/* suspend/resume, section 4.3 */ 291 292/* These routines rely on the PCI bus glue 293 * to handle powerdown and wakeup, and currently also on 294 * transceivers that don't need any software attention to set up 295 * the right sort of wakeup. 296 * Also they depend on separate root hub suspend/resume. 297 */ 298 299static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 300{ 301 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 302 unsigned long flags; 303 int rc = 0; 304 305 if (time_before(jiffies, ehci->next_statechange)) 306 msleep(10); 307 308 /* Root hub was already suspended. Disable irq emission and 309 * mark HW unaccessible. The PM and USB cores make sure that 310 * the root hub is either suspended or stopped. 311 */ 312 spin_lock_irqsave (&ehci->lock, flags); 313 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); 314 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 315 (void)ehci_readl(ehci, &ehci->regs->intr_enable); 316 317 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 318 spin_unlock_irqrestore (&ehci->lock, flags); 319 320 // could save FLADJ in case of Vaux power loss 321 // ... we'd only use it to handle clock skew 322 323 return rc; 324} 325 326static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) 327{ 328 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 329 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 330 331 // maybe restore FLADJ 332 333 if (time_before(jiffies, ehci->next_statechange)) 334 msleep(100); 335 336 /* Mark hardware accessible again as we are out of D3 state by now */ 337 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 338 339 /* If CF is still set and we aren't resuming from hibernation 340 * then we maintained PCI Vaux power. 341 * Just undo the effect of ehci_pci_suspend(). 342 */ 343 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && 344 !hibernated) { 345 int mask = INTR_MASK; 346 347 ehci_prepare_ports_for_controller_resume(ehci); 348 if (!hcd->self.root_hub->do_remote_wakeup) 349 mask &= ~STS_PCD; 350 ehci_writel(ehci, mask, &ehci->regs->intr_enable); 351 ehci_readl(ehci, &ehci->regs->intr_enable); 352 return 0; 353 } 354 355 usb_root_hub_lost_power(hcd->self.root_hub); 356 357 /* Else reset, to cope with power loss or flush-to-storage 358 * style "resume" having let BIOS kick in during reboot. 359 */ 360 (void) ehci_halt(ehci); 361 (void) ehci_reset(ehci); 362 (void) ehci_pci_reinit(ehci, pdev); 363 364 /* emptying the schedule aborts any urbs */ 365 spin_lock_irq(&ehci->lock); 366 if (ehci->reclaim) 367 end_unlink_async(ehci); 368 ehci_work(ehci); 369 spin_unlock_irq(&ehci->lock); 370 371 ehci_writel(ehci, ehci->command, &ehci->regs->command); 372 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 373 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 374 375 /* here we "know" root ports should always stay powered */ 376 ehci_port_power(ehci, 1); 377 378 hcd->state = HC_STATE_SUSPENDED; 379 return 0; 380} 381#endif 382 383static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev) 384{ 385 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 386 int rc = 0; 387 388 if (!udev->parent) /* udev is root hub itself, impossible */ 389 rc = -1; 390 /* we only support lpm device connected to root hub yet */ 391 if (ehci->has_lpm && !udev->parent->parent) { 392 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum); 393 if (!rc) 394 rc = ehci_lpm_check(ehci, udev->portnum); 395 } 396 return rc; 397} 398 399static const struct hc_driver ehci_pci_hc_driver = { 400 .description = hcd_name, 401 .product_desc = "EHCI Host Controller", 402 .hcd_priv_size = sizeof(struct ehci_hcd), 403 404 /* 405 * generic hardware linkage 406 */ 407 .irq = ehci_irq, 408 .flags = HCD_MEMORY | HCD_USB2, 409 410 /* 411 * basic lifecycle operations 412 */ 413 .reset = ehci_pci_setup, 414 .start = ehci_run, 415#ifdef CONFIG_PM 416 .pci_suspend = ehci_pci_suspend, 417 .pci_resume = ehci_pci_resume, 418#endif 419 .stop = ehci_stop, 420 .shutdown = ehci_shutdown, 421 422 /* 423 * managing i/o requests and associated device resources 424 */ 425 .urb_enqueue = ehci_urb_enqueue, 426 .urb_dequeue = ehci_urb_dequeue, 427 .endpoint_disable = ehci_endpoint_disable, 428 .endpoint_reset = ehci_endpoint_reset, 429 430 /* 431 * scheduling support 432 */ 433 .get_frame_number = ehci_get_frame, 434 435 /* 436 * root hub support 437 */ 438 .hub_status_data = ehci_hub_status_data, 439 .hub_control = ehci_hub_control, 440 .bus_suspend = ehci_bus_suspend, 441 .bus_resume = ehci_bus_resume, 442 .relinquish_port = ehci_relinquish_port, 443 .port_handed_over = ehci_port_handed_over, 444 445 /* 446 * call back when device connected and addressed 447 */ 448 .update_device = ehci_update_device, 449 450 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 451}; 452 453/*-------------------------------------------------------------------------*/ 454 455/* PCI driver selection metadata; PCI hotplugging uses this */ 456static const struct pci_device_id pci_ids [] = { { 457 /* handle any USB 2.0 EHCI controller */ 458 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), 459 .driver_data = (unsigned long) &ehci_pci_hc_driver, 460 }, 461 { /* end: all zeroes */ } 462}; 463MODULE_DEVICE_TABLE(pci, pci_ids); 464 465/* pci driver glue; this is a "new style" PCI driver module */ 466static struct pci_driver ehci_pci_driver = { 467 .name = (char *) hcd_name, 468 .id_table = pci_ids, 469 470 .probe = usb_hcd_pci_probe, 471 .remove = usb_hcd_pci_remove, 472 .shutdown = usb_hcd_pci_shutdown, 473 474#ifdef CONFIG_PM_SLEEP 475 .driver = { 476 .pm = &usb_hcd_pci_pm_ops 477 }, 478#endif 479}; 480