ehci-q.c revision 7dedacf4270a810fadcca887ac85d267b5f1882d
1/*
2 * Copyright (C) 2001-2004 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* this file is part of ehci-hcd.c */
20
21/*-------------------------------------------------------------------------*/
22
23/*
24 * EHCI hardware queue manipulation ... the core.  QH/QTD manipulation.
25 *
26 * Control, bulk, and interrupt traffic all use "qh" lists.  They list "qtd"
27 * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
28 * buffers needed for the larger number).  We use one QH per endpoint, queue
29 * multiple urbs (all three types) per endpoint.  URBs may need several qtds.
30 *
31 * ISO traffic uses "ISO TD" (itd, and sitd) records, and (along with
32 * interrupts) needs careful scheduling.  Performance improvements can be
33 * an ongoing challenge.  That's in "ehci-sched.c".
34 *
35 * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
36 * or otherwise through transaction translators (TTs) in USB 2.0 hubs using
37 * (b) special fields in qh entries or (c) split iso entries.  TTs will
38 * buffer low/full speed data so the host collects it at high speed.
39 */
40
41/*-------------------------------------------------------------------------*/
42
43/* fill a qtd, returning how much of the buffer we were able to queue up */
44
45static int
46qtd_fill (struct ehci_qtd *qtd, dma_addr_t buf, size_t len,
47		int token, int maxpacket)
48{
49	int	i, count;
50	u64	addr = buf;
51
52	/* one buffer entry per 4K ... first might be short or unaligned */
53	qtd->hw_buf [0] = cpu_to_le32 ((u32)addr);
54	qtd->hw_buf_hi [0] = cpu_to_le32 ((u32)(addr >> 32));
55	count = 0x1000 - (buf & 0x0fff);	/* rest of that page */
56	if (likely (len < count))		/* ... iff needed */
57		count = len;
58	else {
59		buf +=  0x1000;
60		buf &= ~0x0fff;
61
62		/* per-qtd limit: from 16K to 20K (best alignment) */
63		for (i = 1; count < len && i < 5; i++) {
64			addr = buf;
65			qtd->hw_buf [i] = cpu_to_le32 ((u32)addr);
66			qtd->hw_buf_hi [i] = cpu_to_le32 ((u32)(addr >> 32));
67			buf += 0x1000;
68			if ((count + 0x1000) < len)
69				count += 0x1000;
70			else
71				count = len;
72		}
73
74		/* short packets may only terminate transfers */
75		if (count != len)
76			count -= (count % maxpacket);
77	}
78	qtd->hw_token = cpu_to_le32 ((count << 16) | token);
79	qtd->length = count;
80
81	return count;
82}
83
84/*-------------------------------------------------------------------------*/
85
86static inline void
87qh_update (struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd)
88{
89	/* writes to an active overlay are unsafe */
90	BUG_ON(qh->qh_state != QH_STATE_IDLE);
91
92	qh->hw_qtd_next = QTD_NEXT (qtd->qtd_dma);
93	qh->hw_alt_next = EHCI_LIST_END;
94
95	/* Except for control endpoints, we make hardware maintain data
96	 * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
97	 * and set the pseudo-toggle in udev. Only usb_clear_halt() will
98	 * ever clear it.
99	 */
100	if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) {
101		unsigned	is_out, epnum;
102
103		is_out = !(qtd->hw_token & cpu_to_le32(1 << 8));
104		epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f;
105		if (unlikely (!usb_gettoggle (qh->dev, epnum, is_out))) {
106			qh->hw_token &= ~__constant_cpu_to_le32 (QTD_TOGGLE);
107			usb_settoggle (qh->dev, epnum, is_out, 1);
108		}
109	}
110
111	/* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
112	wmb ();
113	qh->hw_token &= __constant_cpu_to_le32 (QTD_TOGGLE | QTD_STS_PING);
114}
115
116/* if it weren't for a common silicon quirk (writing the dummy into the qh
117 * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
118 * recovery (including urb dequeue) would need software changes to a QH...
119 */
120static void
121qh_refresh (struct ehci_hcd *ehci, struct ehci_qh *qh)
122{
123	struct ehci_qtd *qtd;
124
125	if (list_empty (&qh->qtd_list))
126		qtd = qh->dummy;
127	else {
128		qtd = list_entry (qh->qtd_list.next,
129				struct ehci_qtd, qtd_list);
130		/* first qtd may already be partially processed */
131		if (cpu_to_le32 (qtd->qtd_dma) == qh->hw_current)
132			qtd = NULL;
133	}
134
135	if (qtd)
136		qh_update (ehci, qh, qtd);
137}
138
139/*-------------------------------------------------------------------------*/
140
141static void qtd_copy_status (
142	struct ehci_hcd *ehci,
143	struct urb *urb,
144	size_t length,
145	u32 token
146)
147{
148	/* count IN/OUT bytes, not SETUP (even short packets) */
149	if (likely (QTD_PID (token) != 2))
150		urb->actual_length += length - QTD_LENGTH (token);
151
152	/* don't modify error codes */
153	if (unlikely (urb->status != -EINPROGRESS))
154		return;
155
156	/* force cleanup after short read; not always an error */
157	if (unlikely (IS_SHORT_READ (token)))
158		urb->status = -EREMOTEIO;
159
160	/* serious "can't proceed" faults reported by the hardware */
161	if (token & QTD_STS_HALT) {
162		if (token & QTD_STS_BABBLE) {
163			/* FIXME "must" disable babbling device's port too */
164			urb->status = -EOVERFLOW;
165		} else if (token & QTD_STS_MMF) {
166			/* fs/ls interrupt xfer missed the complete-split */
167			urb->status = -EPROTO;
168		} else if (token & QTD_STS_DBE) {
169			urb->status = (QTD_PID (token) == 1) /* IN ? */
170				? -ENOSR  /* hc couldn't read data */
171				: -ECOMM; /* hc couldn't write data */
172		} else if (token & QTD_STS_XACT) {
173			/* timeout, bad crc, wrong PID, etc; retried */
174			if (QTD_CERR (token))
175				urb->status = -EPIPE;
176			else {
177				ehci_dbg (ehci, "devpath %s ep%d%s 3strikes\n",
178					urb->dev->devpath,
179					usb_pipeendpoint (urb->pipe),
180					usb_pipein (urb->pipe) ? "in" : "out");
181				urb->status = -EPROTO;
182			}
183		/* CERR nonzero + no errors + halt --> stall */
184		} else if (QTD_CERR (token))
185			urb->status = -EPIPE;
186		else	/* unknown */
187			urb->status = -EPROTO;
188
189		ehci_vdbg (ehci,
190			"dev%d ep%d%s qtd token %08x --> status %d\n",
191			usb_pipedevice (urb->pipe),
192			usb_pipeendpoint (urb->pipe),
193			usb_pipein (urb->pipe) ? "in" : "out",
194			token, urb->status);
195
196		/* if async CSPLIT failed, try cleaning out the TT buffer */
197		if (urb->status != -EPIPE
198				&& urb->dev->tt && !usb_pipeint (urb->pipe)
199				&& ((token & QTD_STS_MMF) != 0
200					|| QTD_CERR(token) == 0)
201				&& (!ehci_is_TDI(ehci)
202                	                || urb->dev->tt->hub !=
203					   ehci_to_hcd(ehci)->self.root_hub)) {
204#ifdef DEBUG
205			struct usb_device *tt = urb->dev->tt->hub;
206			dev_dbg (&tt->dev,
207				"clear tt buffer port %d, a%d ep%d t%08x\n",
208				urb->dev->ttport, urb->dev->devnum,
209				usb_pipeendpoint (urb->pipe), token);
210#endif /* DEBUG */
211			usb_hub_tt_clear_buffer (urb->dev, urb->pipe);
212		}
213	}
214}
215
216static void
217ehci_urb_done (struct ehci_hcd *ehci, struct urb *urb, struct pt_regs *regs)
218__releases(ehci->lock)
219__acquires(ehci->lock)
220{
221	if (likely (urb->hcpriv != NULL)) {
222		struct ehci_qh	*qh = (struct ehci_qh *) urb->hcpriv;
223
224		/* S-mask in a QH means it's an interrupt urb */
225		if ((qh->hw_info2 & __constant_cpu_to_le32 (QH_SMASK)) != 0) {
226
227			/* ... update hc-wide periodic stats (for usbfs) */
228			ehci_to_hcd(ehci)->self.bandwidth_int_reqs--;
229		}
230		qh_put (qh);
231	}
232
233	spin_lock (&urb->lock);
234	urb->hcpriv = NULL;
235	switch (urb->status) {
236	case -EINPROGRESS:		/* success */
237		urb->status = 0;
238	default:			/* fault */
239		COUNT (ehci->stats.complete);
240		break;
241	case -EREMOTEIO:		/* fault or normal */
242		if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
243			urb->status = 0;
244		COUNT (ehci->stats.complete);
245		break;
246	case -ECONNRESET:		/* canceled */
247	case -ENOENT:
248		COUNT (ehci->stats.unlink);
249		break;
250	}
251	spin_unlock (&urb->lock);
252
253#ifdef EHCI_URB_TRACE
254	ehci_dbg (ehci,
255		"%s %s urb %p ep%d%s status %d len %d/%d\n",
256		__FUNCTION__, urb->dev->devpath, urb,
257		usb_pipeendpoint (urb->pipe),
258		usb_pipein (urb->pipe) ? "in" : "out",
259		urb->status,
260		urb->actual_length, urb->transfer_buffer_length);
261#endif
262
263	/* complete() can reenter this HCD */
264	spin_unlock (&ehci->lock);
265	usb_hcd_giveback_urb (ehci_to_hcd(ehci), urb, regs);
266	spin_lock (&ehci->lock);
267}
268
269static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh);
270static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh);
271
272static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh);
273static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh);
274
275/*
276 * Process and free completed qtds for a qh, returning URBs to drivers.
277 * Chases up to qh->hw_current.  Returns number of completions called,
278 * indicating how much "real" work we did.
279 */
280#define HALT_BIT __constant_cpu_to_le32(QTD_STS_HALT)
281static unsigned
282qh_completions (struct ehci_hcd *ehci, struct ehci_qh *qh, struct pt_regs *regs)
283{
284	struct ehci_qtd		*last = NULL, *end = qh->dummy;
285	struct list_head	*entry, *tmp;
286	int			stopped;
287	unsigned		count = 0;
288	int			do_status = 0;
289	u8			state;
290
291	if (unlikely (list_empty (&qh->qtd_list)))
292		return count;
293
294	/* completions (or tasks on other cpus) must never clobber HALT
295	 * till we've gone through and cleaned everything up, even when
296	 * they add urbs to this qh's queue or mark them for unlinking.
297	 *
298	 * NOTE:  unlinking expects to be done in queue order.
299	 */
300	state = qh->qh_state;
301	qh->qh_state = QH_STATE_COMPLETING;
302	stopped = (state == QH_STATE_IDLE);
303
304	/* remove de-activated QTDs from front of queue.
305	 * after faults (including short reads), cleanup this urb
306	 * then let the queue advance.
307	 * if queue is stopped, handles unlinks.
308	 */
309	list_for_each_safe (entry, tmp, &qh->qtd_list) {
310		struct ehci_qtd	*qtd;
311		struct urb	*urb;
312		u32		token = 0;
313
314		qtd = list_entry (entry, struct ehci_qtd, qtd_list);
315		urb = qtd->urb;
316
317		/* clean up any state from previous QTD ...*/
318		if (last) {
319			if (likely (last->urb != urb)) {
320				ehci_urb_done (ehci, last->urb, regs);
321				count++;
322			}
323			ehci_qtd_free (ehci, last);
324			last = NULL;
325		}
326
327		/* ignore urbs submitted during completions we reported */
328		if (qtd == end)
329			break;
330
331		/* hardware copies qtd out of qh overlay */
332		rmb ();
333		token = le32_to_cpu (qtd->hw_token);
334
335		/* always clean up qtds the hc de-activated */
336		if ((token & QTD_STS_ACTIVE) == 0) {
337
338			if ((token & QTD_STS_HALT) != 0) {
339				stopped = 1;
340
341			/* magic dummy for some short reads; qh won't advance.
342			 * that silicon quirk can kick in with this dummy too.
343			 */
344			} else if (IS_SHORT_READ (token)
345					&& !(qtd->hw_alt_next & EHCI_LIST_END)) {
346				stopped = 1;
347				goto halt;
348			}
349
350		/* stop scanning when we reach qtds the hc is using */
351		} else if (likely (!stopped
352				&& HC_IS_RUNNING (ehci_to_hcd(ehci)->state))) {
353			break;
354
355		} else {
356			stopped = 1;
357
358			if (unlikely (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)))
359				urb->status = -ESHUTDOWN;
360
361			/* ignore active urbs unless some previous qtd
362			 * for the urb faulted (including short read) or
363			 * its urb was canceled.  we may patch qh or qtds.
364			 */
365			if (likely (urb->status == -EINPROGRESS))
366				continue;
367
368			/* issue status after short control reads */
369			if (unlikely (do_status != 0)
370					&& QTD_PID (token) == 0 /* OUT */) {
371				do_status = 0;
372				continue;
373			}
374
375			/* token in overlay may be most current */
376			if (state == QH_STATE_IDLE
377					&& cpu_to_le32 (qtd->qtd_dma)
378						== qh->hw_current)
379				token = le32_to_cpu (qh->hw_token);
380
381			/* force halt for unlinked or blocked qh, so we'll
382			 * patch the qh later and so that completions can't
383			 * activate it while we "know" it's stopped.
384			 */
385			if ((HALT_BIT & qh->hw_token) == 0) {
386halt:
387				qh->hw_token |= HALT_BIT;
388				wmb ();
389			}
390		}
391
392		/* remove it from the queue */
393		spin_lock (&urb->lock);
394		qtd_copy_status (ehci, urb, qtd->length, token);
395		do_status = (urb->status == -EREMOTEIO)
396				&& usb_pipecontrol (urb->pipe);
397		spin_unlock (&urb->lock);
398
399		if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
400			last = list_entry (qtd->qtd_list.prev,
401					struct ehci_qtd, qtd_list);
402			last->hw_next = qtd->hw_next;
403		}
404		list_del (&qtd->qtd_list);
405		last = qtd;
406	}
407
408	/* last urb's completion might still need calling */
409	if (likely (last != NULL)) {
410		ehci_urb_done (ehci, last->urb, regs);
411		count++;
412		ehci_qtd_free (ehci, last);
413	}
414
415	/* restore original state; caller must unlink or relink */
416	qh->qh_state = state;
417
418	/* be sure the hardware's done with the qh before refreshing
419	 * it after fault cleanup, or recovering from silicon wrongly
420	 * overlaying the dummy qtd (which reduces DMA chatter).
421	 */
422	if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) {
423		switch (state) {
424		case QH_STATE_IDLE:
425			qh_refresh(ehci, qh);
426			break;
427		case QH_STATE_LINKED:
428			/* should be rare for periodic transfers,
429			 * except maybe high bandwidth ...
430			 */
431			if ((__constant_cpu_to_le32 (QH_SMASK)
432					& qh->hw_info2) != 0) {
433				intr_deschedule (ehci, qh);
434				(void) qh_schedule (ehci, qh);
435			} else
436				unlink_async (ehci, qh);
437			break;
438		/* otherwise, unlink already started */
439		}
440	}
441
442	return count;
443}
444
445/*-------------------------------------------------------------------------*/
446
447// high bandwidth multiplier, as encoded in highspeed endpoint descriptors
448#define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
449// ... and packet size, for any kind of endpoint descriptor
450#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
451
452/*
453 * reverse of qh_urb_transaction:  free a list of TDs.
454 * used for cleanup after errors, before HC sees an URB's TDs.
455 */
456static void qtd_list_free (
457	struct ehci_hcd		*ehci,
458	struct urb		*urb,
459	struct list_head	*qtd_list
460) {
461	struct list_head	*entry, *temp;
462
463	list_for_each_safe (entry, temp, qtd_list) {
464		struct ehci_qtd	*qtd;
465
466		qtd = list_entry (entry, struct ehci_qtd, qtd_list);
467		list_del (&qtd->qtd_list);
468		ehci_qtd_free (ehci, qtd);
469	}
470}
471
472/*
473 * create a list of filled qtds for this URB; won't link into qh.
474 */
475static struct list_head *
476qh_urb_transaction (
477	struct ehci_hcd		*ehci,
478	struct urb		*urb,
479	struct list_head	*head,
480	int			flags
481) {
482	struct ehci_qtd		*qtd, *qtd_prev;
483	dma_addr_t		buf;
484	int			len, maxpacket;
485	int			is_input;
486	u32			token;
487
488	/*
489	 * URBs map to sequences of QTDs:  one logical transaction
490	 */
491	qtd = ehci_qtd_alloc (ehci, flags);
492	if (unlikely (!qtd))
493		return NULL;
494	list_add_tail (&qtd->qtd_list, head);
495	qtd->urb = urb;
496
497	token = QTD_STS_ACTIVE;
498	token |= (EHCI_TUNE_CERR << 10);
499	/* for split transactions, SplitXState initialized to zero */
500
501	len = urb->transfer_buffer_length;
502	is_input = usb_pipein (urb->pipe);
503	if (usb_pipecontrol (urb->pipe)) {
504		/* SETUP pid */
505		qtd_fill (qtd, urb->setup_dma, sizeof (struct usb_ctrlrequest),
506			token | (2 /* "setup" */ << 8), 8);
507
508		/* ... and always at least one more pid */
509		token ^= QTD_TOGGLE;
510		qtd_prev = qtd;
511		qtd = ehci_qtd_alloc (ehci, flags);
512		if (unlikely (!qtd))
513			goto cleanup;
514		qtd->urb = urb;
515		qtd_prev->hw_next = QTD_NEXT (qtd->qtd_dma);
516		list_add_tail (&qtd->qtd_list, head);
517	}
518
519	/*
520	 * data transfer stage:  buffer setup
521	 */
522	if (likely (len > 0))
523		buf = urb->transfer_dma;
524	else
525		buf = 0;
526
527	/* for zero length DATA stages, STATUS is always IN */
528	if (!buf || is_input)
529		token |= (1 /* "in" */ << 8);
530	/* else it's already initted to "out" pid (0 << 8) */
531
532	maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
533
534	/*
535	 * buffer gets wrapped in one or more qtds;
536	 * last one may be "short" (including zero len)
537	 * and may serve as a control status ack
538	 */
539	for (;;) {
540		int this_qtd_len;
541
542		this_qtd_len = qtd_fill (qtd, buf, len, token, maxpacket);
543		len -= this_qtd_len;
544		buf += this_qtd_len;
545		if (is_input)
546			qtd->hw_alt_next = ehci->async->hw_alt_next;
547
548		/* qh makes control packets use qtd toggle; maybe switch it */
549		if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
550			token ^= QTD_TOGGLE;
551
552		if (likely (len <= 0))
553			break;
554
555		qtd_prev = qtd;
556		qtd = ehci_qtd_alloc (ehci, flags);
557		if (unlikely (!qtd))
558			goto cleanup;
559		qtd->urb = urb;
560		qtd_prev->hw_next = QTD_NEXT (qtd->qtd_dma);
561		list_add_tail (&qtd->qtd_list, head);
562	}
563
564	/* unless the bulk/interrupt caller wants a chance to clean
565	 * up after short reads, hc should advance qh past this urb
566	 */
567	if (likely ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
568				|| usb_pipecontrol (urb->pipe)))
569		qtd->hw_alt_next = EHCI_LIST_END;
570
571	/*
572	 * control requests may need a terminating data "status" ack;
573	 * bulk ones may need a terminating short packet (zero length).
574	 */
575	if (likely (buf != 0)) {
576		int	one_more = 0;
577
578		if (usb_pipecontrol (urb->pipe)) {
579			one_more = 1;
580			token ^= 0x0100;	/* "in" <--> "out"  */
581			token |= QTD_TOGGLE;	/* force DATA1 */
582		} else if (usb_pipebulk (urb->pipe)
583				&& (urb->transfer_flags & URB_ZERO_PACKET)
584				&& !(urb->transfer_buffer_length % maxpacket)) {
585			one_more = 1;
586		}
587		if (one_more) {
588			qtd_prev = qtd;
589			qtd = ehci_qtd_alloc (ehci, flags);
590			if (unlikely (!qtd))
591				goto cleanup;
592			qtd->urb = urb;
593			qtd_prev->hw_next = QTD_NEXT (qtd->qtd_dma);
594			list_add_tail (&qtd->qtd_list, head);
595
596			/* never any data in such packets */
597			qtd_fill (qtd, 0, 0, token, 0);
598		}
599	}
600
601	/* by default, enable interrupt on urb completion */
602	if (likely (!(urb->transfer_flags & URB_NO_INTERRUPT)))
603		qtd->hw_token |= __constant_cpu_to_le32 (QTD_IOC);
604	return head;
605
606cleanup:
607	qtd_list_free (ehci, urb, head);
608	return NULL;
609}
610
611/*-------------------------------------------------------------------------*/
612
613// Would be best to create all qh's from config descriptors,
614// when each interface/altsetting is established.  Unlink
615// any previous qh and cancel its urbs first; endpoints are
616// implicitly reset then (data toggle too).
617// That'd mean updating how usbcore talks to HCDs. (2.7?)
618
619
620/*
621 * Each QH holds a qtd list; a QH is used for everything except iso.
622 *
623 * For interrupt urbs, the scheduler must set the microframe scheduling
624 * mask(s) each time the QH gets scheduled.  For highspeed, that's
625 * just one microframe in the s-mask.  For split interrupt transactions
626 * there are additional complications: c-mask, maybe FSTNs.
627 */
628static struct ehci_qh *
629qh_make (
630	struct ehci_hcd		*ehci,
631	struct urb		*urb,
632	int			flags
633) {
634	struct ehci_qh		*qh = ehci_qh_alloc (ehci, flags);
635	u32			info1 = 0, info2 = 0;
636	int			is_input, type;
637	int			maxp = 0;
638
639	if (!qh)
640		return qh;
641
642	/*
643	 * init endpoint/device data for this QH
644	 */
645	info1 |= usb_pipeendpoint (urb->pipe) << 8;
646	info1 |= usb_pipedevice (urb->pipe) << 0;
647
648	is_input = usb_pipein (urb->pipe);
649	type = usb_pipetype (urb->pipe);
650	maxp = usb_maxpacket (urb->dev, urb->pipe, !is_input);
651
652	/* Compute interrupt scheduling parameters just once, and save.
653	 * - allowing for high bandwidth, how many nsec/uframe are used?
654	 * - split transactions need a second CSPLIT uframe; same question
655	 * - splits also need a schedule gap (for full/low speed I/O)
656	 * - qh has a polling interval
657	 *
658	 * For control/bulk requests, the HC or TT handles these.
659	 */
660	if (type == PIPE_INTERRUPT) {
661		qh->usecs = NS_TO_US (usb_calc_bus_time (USB_SPEED_HIGH, is_input, 0,
662				hb_mult (maxp) * max_packet (maxp)));
663		qh->start = NO_FRAME;
664
665		if (urb->dev->speed == USB_SPEED_HIGH) {
666			qh->c_usecs = 0;
667			qh->gap_uf = 0;
668
669			qh->period = urb->interval >> 3;
670			if (qh->period == 0 && urb->interval != 1) {
671				/* NOTE interval 2 or 4 uframes could work.
672				 * But interval 1 scheduling is simpler, and
673				 * includes high bandwidth.
674				 */
675				dbg ("intr period %d uframes, NYET!",
676						urb->interval);
677				goto done;
678			}
679		} else {
680			/* gap is f(FS/LS transfer times) */
681			qh->gap_uf = 1 + usb_calc_bus_time (urb->dev->speed,
682					is_input, 0, maxp) / (125 * 1000);
683
684			/* FIXME this just approximates SPLIT/CSPLIT times */
685			if (is_input) {		// SPLIT, gap, CSPLIT+DATA
686				qh->c_usecs = qh->usecs + HS_USECS (0);
687				qh->usecs = HS_USECS (1);
688			} else {		// SPLIT+DATA, gap, CSPLIT
689				qh->usecs += HS_USECS (1);
690				qh->c_usecs = HS_USECS (0);
691			}
692
693			qh->period = urb->interval;
694		}
695	}
696
697	/* support for tt scheduling, and access to toggles */
698	qh->dev = usb_get_dev (urb->dev);
699
700	/* using TT? */
701	switch (urb->dev->speed) {
702	case USB_SPEED_LOW:
703		info1 |= (1 << 12);	/* EPS "low" */
704		/* FALL THROUGH */
705
706	case USB_SPEED_FULL:
707		/* EPS 0 means "full" */
708		if (type != PIPE_INTERRUPT)
709			info1 |= (EHCI_TUNE_RL_TT << 28);
710		if (type == PIPE_CONTROL) {
711			info1 |= (1 << 27);	/* for TT */
712			info1 |= 1 << 14;	/* toggle from qtd */
713		}
714		info1 |= maxp << 16;
715
716		info2 |= (EHCI_TUNE_MULT_TT << 30);
717		info2 |= urb->dev->ttport << 23;
718
719		/* set the address of the TT; for TDI's integrated
720		 * root hub tt, leave it zeroed.
721		 */
722		if (!ehci_is_TDI(ehci)
723				|| urb->dev->tt->hub !=
724					ehci_to_hcd(ehci)->self.root_hub)
725			info2 |= urb->dev->tt->hub->devnum << 16;
726
727		/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets c-mask } */
728
729		break;
730
731	case USB_SPEED_HIGH:		/* no TT involved */
732		info1 |= (2 << 12);	/* EPS "high" */
733		if (type == PIPE_CONTROL) {
734			info1 |= (EHCI_TUNE_RL_HS << 28);
735			info1 |= 64 << 16;	/* usb2 fixed maxpacket */
736			info1 |= 1 << 14;	/* toggle from qtd */
737			info2 |= (EHCI_TUNE_MULT_HS << 30);
738		} else if (type == PIPE_BULK) {
739			info1 |= (EHCI_TUNE_RL_HS << 28);
740			info1 |= 512 << 16;	/* usb2 fixed maxpacket */
741			info2 |= (EHCI_TUNE_MULT_HS << 30);
742		} else {		/* PIPE_INTERRUPT */
743			info1 |= max_packet (maxp) << 16;
744			info2 |= hb_mult (maxp) << 30;
745		}
746		break;
747	default:
748 		dbg ("bogus dev %p speed %d", urb->dev, urb->dev->speed);
749done:
750		qh_put (qh);
751		return NULL;
752	}
753
754	/* NOTE:  if (PIPE_INTERRUPT) { scheduler sets s-mask } */
755
756	/* init as live, toggle clear, advance to dummy */
757	qh->qh_state = QH_STATE_IDLE;
758	qh->hw_info1 = cpu_to_le32 (info1);
759	qh->hw_info2 = cpu_to_le32 (info2);
760	usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), !is_input, 1);
761	qh_refresh (ehci, qh);
762	return qh;
763}
764
765/*-------------------------------------------------------------------------*/
766
767/* move qh (and its qtds) onto async queue; maybe enable queue.  */
768
769static void qh_link_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
770{
771	__le32		dma = QH_NEXT (qh->qh_dma);
772	struct ehci_qh	*head;
773
774	/* (re)start the async schedule? */
775	head = ehci->async;
776	timer_action_done (ehci, TIMER_ASYNC_OFF);
777	if (!head->qh_next.qh) {
778		u32	cmd = readl (&ehci->regs->command);
779
780		if (!(cmd & CMD_ASE)) {
781			/* in case a clear of CMD_ASE didn't take yet */
782			(void) handshake (&ehci->regs->status, STS_ASS, 0, 150);
783			cmd |= CMD_ASE | CMD_RUN;
784			writel (cmd, &ehci->regs->command);
785			ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
786			/* posted write need not be known to HC yet ... */
787		}
788	}
789
790	/* clear halt and/or toggle; and maybe recover from silicon quirk */
791	if (qh->qh_state == QH_STATE_IDLE)
792		qh_refresh (ehci, qh);
793
794	/* splice right after start */
795	qh->qh_next = head->qh_next;
796	qh->hw_next = head->hw_next;
797	wmb ();
798
799	head->qh_next.qh = qh;
800	head->hw_next = dma;
801
802	qh->qh_state = QH_STATE_LINKED;
803	/* qtd completions reported later by interrupt */
804}
805
806/*-------------------------------------------------------------------------*/
807
808#define	QH_ADDR_MASK	__constant_cpu_to_le32(0x7f)
809
810/*
811 * For control/bulk/interrupt, return QH with these TDs appended.
812 * Allocates and initializes the QH if necessary.
813 * Returns null if it can't allocate a QH it needs to.
814 * If the QH has TDs (urbs) already, that's great.
815 */
816static struct ehci_qh *qh_append_tds (
817	struct ehci_hcd		*ehci,
818	struct urb		*urb,
819	struct list_head	*qtd_list,
820	int			epnum,
821	void			**ptr
822)
823{
824	struct ehci_qh		*qh = NULL;
825
826	qh = (struct ehci_qh *) *ptr;
827	if (unlikely (qh == NULL)) {
828		/* can't sleep here, we have ehci->lock... */
829		qh = qh_make (ehci, urb, GFP_ATOMIC);
830		*ptr = qh;
831	}
832	if (likely (qh != NULL)) {
833		struct ehci_qtd	*qtd;
834
835		if (unlikely (list_empty (qtd_list)))
836			qtd = NULL;
837		else
838			qtd = list_entry (qtd_list->next, struct ehci_qtd,
839					qtd_list);
840
841		/* control qh may need patching ... */
842		if (unlikely (epnum == 0)) {
843
844                        /* usb_reset_device() briefly reverts to address 0 */
845                        if (usb_pipedevice (urb->pipe) == 0)
846                                qh->hw_info1 &= ~QH_ADDR_MASK;
847		}
848
849		/* just one way to queue requests: swap with the dummy qtd.
850		 * only hc or qh_refresh() ever modify the overlay.
851		 */
852		if (likely (qtd != NULL)) {
853			struct ehci_qtd		*dummy;
854			dma_addr_t		dma;
855			__le32			token;
856
857			/* to avoid racing the HC, use the dummy td instead of
858			 * the first td of our list (becomes new dummy).  both
859			 * tds stay deactivated until we're done, when the
860			 * HC is allowed to fetch the old dummy (4.10.2).
861			 */
862			token = qtd->hw_token;
863			qtd->hw_token = HALT_BIT;
864			wmb ();
865			dummy = qh->dummy;
866
867			dma = dummy->qtd_dma;
868			*dummy = *qtd;
869			dummy->qtd_dma = dma;
870
871			list_del (&qtd->qtd_list);
872			list_add (&dummy->qtd_list, qtd_list);
873			__list_splice (qtd_list, qh->qtd_list.prev);
874
875			ehci_qtd_init (qtd, qtd->qtd_dma);
876			qh->dummy = qtd;
877
878			/* hc must see the new dummy at list end */
879			dma = qtd->qtd_dma;
880			qtd = list_entry (qh->qtd_list.prev,
881					struct ehci_qtd, qtd_list);
882			qtd->hw_next = QTD_NEXT (dma);
883
884			/* let the hc process these next qtds */
885			wmb ();
886			dummy->hw_token = token;
887
888			urb->hcpriv = qh_get (qh);
889		}
890	}
891	return qh;
892}
893
894/*-------------------------------------------------------------------------*/
895
896static int
897submit_async (
898	struct ehci_hcd		*ehci,
899	struct usb_host_endpoint *ep,
900	struct urb		*urb,
901	struct list_head	*qtd_list,
902	unsigned		mem_flags
903) {
904	struct ehci_qtd		*qtd;
905	int			epnum;
906	unsigned long		flags;
907	struct ehci_qh		*qh = NULL;
908
909	qtd = list_entry (qtd_list->next, struct ehci_qtd, qtd_list);
910	epnum = ep->desc.bEndpointAddress;
911
912#ifdef EHCI_URB_TRACE
913	ehci_dbg (ehci,
914		"%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
915		__FUNCTION__, urb->dev->devpath, urb,
916		epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
917		urb->transfer_buffer_length,
918		qtd, ep->hcpriv);
919#endif
920
921	spin_lock_irqsave (&ehci->lock, flags);
922	qh = qh_append_tds (ehci, urb, qtd_list, epnum, &ep->hcpriv);
923
924	/* Control/bulk operations through TTs don't need scheduling,
925	 * the HC and TT handle it when the TT has a buffer ready.
926	 */
927	if (likely (qh != NULL)) {
928		if (likely (qh->qh_state == QH_STATE_IDLE))
929			qh_link_async (ehci, qh_get (qh));
930	}
931	spin_unlock_irqrestore (&ehci->lock, flags);
932	if (unlikely (qh == NULL)) {
933		qtd_list_free (ehci, urb, qtd_list);
934		return -ENOMEM;
935	}
936	return 0;
937}
938
939/*-------------------------------------------------------------------------*/
940
941/* the async qh for the qtds being reclaimed are now unlinked from the HC */
942
943static void end_unlink_async (struct ehci_hcd *ehci, struct pt_regs *regs)
944{
945	struct ehci_qh		*qh = ehci->reclaim;
946	struct ehci_qh		*next;
947
948	timer_action_done (ehci, TIMER_IAA_WATCHDOG);
949
950	// qh->hw_next = cpu_to_le32 (qh->qh_dma);
951	qh->qh_state = QH_STATE_IDLE;
952	qh->qh_next.qh = NULL;
953	qh_put (qh);			// refcount from reclaim
954
955	/* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
956	next = qh->reclaim;
957	ehci->reclaim = next;
958	ehci->reclaim_ready = 0;
959	qh->reclaim = NULL;
960
961	qh_completions (ehci, qh, regs);
962
963	if (!list_empty (&qh->qtd_list)
964			&& HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
965		qh_link_async (ehci, qh);
966	else {
967		qh_put (qh);		// refcount from async list
968
969		/* it's not free to turn the async schedule on/off; leave it
970		 * active but idle for a while once it empties.
971		 */
972		if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
973				&& ehci->async->qh_next.qh == NULL)
974			timer_action (ehci, TIMER_ASYNC_OFF);
975	}
976
977	if (next) {
978		ehci->reclaim = NULL;
979		start_unlink_async (ehci, next);
980	}
981}
982
983/* makes sure the async qh will become idle */
984/* caller must own ehci->lock */
985
986static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
987{
988	int		cmd = readl (&ehci->regs->command);
989	struct ehci_qh	*prev;
990
991#ifdef DEBUG
992	assert_spin_locked(&ehci->lock);
993	if (ehci->reclaim
994			|| (qh->qh_state != QH_STATE_LINKED
995				&& qh->qh_state != QH_STATE_UNLINK_WAIT)
996			)
997		BUG ();
998#endif
999
1000	/* stop async schedule right now? */
1001	if (unlikely (qh == ehci->async)) {
1002		/* can't get here without STS_ASS set */
1003		if (ehci_to_hcd(ehci)->state != HC_STATE_HALT) {
1004			writel (cmd & ~CMD_ASE, &ehci->regs->command);
1005			wmb ();
1006			// handshake later, if we need to
1007		}
1008		timer_action_done (ehci, TIMER_ASYNC_OFF);
1009		return;
1010	}
1011
1012	qh->qh_state = QH_STATE_UNLINK;
1013	ehci->reclaim = qh = qh_get (qh);
1014
1015	prev = ehci->async;
1016	while (prev->qh_next.qh != qh)
1017		prev = prev->qh_next.qh;
1018
1019	prev->hw_next = qh->hw_next;
1020	prev->qh_next = qh->qh_next;
1021	wmb ();
1022
1023	if (unlikely (ehci_to_hcd(ehci)->state == HC_STATE_HALT)) {
1024		/* if (unlikely (qh->reclaim != 0))
1025		 * 	this will recurse, probably not much
1026		 */
1027		end_unlink_async (ehci, NULL);
1028		return;
1029	}
1030
1031	ehci->reclaim_ready = 0;
1032	cmd |= CMD_IAAD;
1033	writel (cmd, &ehci->regs->command);
1034	(void) readl (&ehci->regs->command);
1035	timer_action (ehci, TIMER_IAA_WATCHDOG);
1036}
1037
1038/*-------------------------------------------------------------------------*/
1039
1040static void
1041scan_async (struct ehci_hcd *ehci, struct pt_regs *regs)
1042{
1043	struct ehci_qh		*qh;
1044	enum ehci_timer_action	action = TIMER_IO_WATCHDOG;
1045
1046	if (!++(ehci->stamp))
1047		ehci->stamp++;
1048	timer_action_done (ehci, TIMER_ASYNC_SHRINK);
1049rescan:
1050	qh = ehci->async->qh_next.qh;
1051	if (likely (qh != NULL)) {
1052		do {
1053			/* clean any finished work for this qh */
1054			if (!list_empty (&qh->qtd_list)
1055					&& qh->stamp != ehci->stamp) {
1056				int temp;
1057
1058				/* unlinks could happen here; completion
1059				 * reporting drops the lock.  rescan using
1060				 * the latest schedule, but don't rescan
1061				 * qhs we already finished (no looping).
1062				 */
1063				qh = qh_get (qh);
1064				qh->stamp = ehci->stamp;
1065				temp = qh_completions (ehci, qh, regs);
1066				qh_put (qh);
1067				if (temp != 0) {
1068					goto rescan;
1069				}
1070			}
1071
1072			/* unlink idle entries, reducing HC PCI usage as well
1073			 * as HCD schedule-scanning costs.  delay for any qh
1074			 * we just scanned, there's a not-unusual case that it
1075			 * doesn't stay idle for long.
1076			 * (plus, avoids some kind of re-activation race.)
1077			 */
1078			if (list_empty (&qh->qtd_list)) {
1079				if (qh->stamp == ehci->stamp)
1080					action = TIMER_ASYNC_SHRINK;
1081				else if (!ehci->reclaim
1082					    && qh->qh_state == QH_STATE_LINKED)
1083					start_unlink_async (ehci, qh);
1084			}
1085
1086			qh = qh->qh_next.qh;
1087		} while (qh);
1088	}
1089	if (action == TIMER_ASYNC_SHRINK)
1090		timer_action (ehci, TIMER_ASYNC_SHRINK);
1091}
1092