1550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* Copyright (C) 2005-2006 by Texas Instruments */ 2550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 3550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#ifndef _CPPI_DMA_H_ 4550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define _CPPI_DMA_H_ 5550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 6550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include <linux/slab.h> 7550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include <linux/list.h> 8550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include <linux/errno.h> 9550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include <linux/dmapool.h> 10550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 11550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include "musb_dma.h" 12550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include "musb_core.h" 13550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 14550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 15550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* FIXME fully isolate CPPI from DaVinci ... the "CPPI generic" registers 16550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * would seem to be shared with the TUSB6020 (over VLYNQ). 17550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 18550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 19550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#include "davinci.h" 20550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 21550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 22550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* CPPI RX/TX state RAM */ 23550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 24550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistruct cppi_tx_stateram { 25550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tx_head; /* "DMA packet" head descriptor */ 26550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tx_buf; 27550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tx_current; /* current descriptor */ 28550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tx_buf_current; 29550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tx_info; /* flags, remaining buflen */ 30550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tx_rem_len; 31550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tx_dummy; /* unused */ 32550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 tx_complete; 33550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi}; 34550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 35550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistruct cppi_rx_stateram { 36550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 rx_skipbytes; 37550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 rx_head; 38550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 rx_sop; /* "DMA packet" head descriptor */ 39550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 rx_current; /* current descriptor */ 40550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 rx_buf_current; 41550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 rx_len_len; 42550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 rx_cnt_cnt; 43550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 rx_complete; 44550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi}; 45550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 46550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* hw_options bits in CPPI buffer descriptors */ 47550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_SOP_SET ((u32)(1 << 31)) 48550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_EOP_SET ((u32)(1 << 30)) 49550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */ 50550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_EOQ_MASK ((u32)(1 << 28)) 51550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */ 52550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */ 53550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 54550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_RECV_PKTLEN_MASK 0xFFFF 55550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_BUFFER_LEN_MASK 0xFFFF 56550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 57550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_TEAR_READY ((u32)(1 << 31)) 58550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 59550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* CPPI data structure definitions */ 60550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 61550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */ 62550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 63550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistruct cppi_descriptor { 64550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* hardware overlay */ 65550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 hw_next; /* next buffer descriptor Pointer */ 66550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 hw_bufp; /* i/o buffer pointer */ 67550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 hw_off_len; /* buffer_offset16, buffer_length16 */ 68550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 hw_options; /* flags: SOP, EOP etc*/ 69550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 70550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *next; 71550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t dma; /* address of this descriptor */ 72550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 buflen; /* for RX: original buffer length */ 73550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN))); 74550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 75550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 76550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistruct cppi; 77550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 78550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* CPPI Channel Control structure */ 79550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistruct cppi_channel { 80550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct dma_channel channel; 81550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 82550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* back pointer to the DMA controller structure */ 83550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi *controller; 84550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 85550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* which direction of which endpoint? */ 86550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct musb_hw_ep *hw_ep; 87550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi bool transmit; 88550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u8 index; 89550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 90550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* DMA modes: RNDIS or "transparent" */ 91550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u8 is_rndis; 92550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 93550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* book keeping for current transfer request */ 94550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi dma_addr_t buf_dma; 95550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 buf_len; 96550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 maxpacket; 97550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi u32 offset; /* dma requested */ 98550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 99550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *state_ram; /* CPPI state */ 100550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 101550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *freelist; 102550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 103550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* BD management fields */ 104550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *head; 105550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *tail; 106550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct cppi_descriptor *last_processed; 107550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 108550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi /* use tx_complete in host role to track endpoints waiting for 109550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi * FIFONOTEMPTY to clear. 110550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi */ 111550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct list_head tx_complete; 112550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi}; 113550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 114550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi/* CPPI DMA controller object */ 115550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbistruct cppi { 116550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct dma_controller controller; 117550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct musb *musb; 118550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *mregs; /* Mentor regs */ 119550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi void __iomem *tibase; /* TI/CPPI regs */ 120550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 12191e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov int irq; 12291e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov 123c767c1c6f1febbd1351cc152bba6e37889322d17David Brownell struct cppi_channel tx[4]; 124c767c1c6f1febbd1351cc152bba6e37889322d17David Brownell struct cppi_channel rx[4]; 125550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 126550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct dma_pool *pool; 127550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 128550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi struct list_head tx_complete; 129550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi}; 130550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 13191e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyov/* CPPI IRQ handler */ 13291e9c4fec7ee777213859aa1a18bf0b885527637Sergei Shtylyovextern irqreturn_t cppi_interrupt(int, void *); 133550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi 134550a7375fe720924241f0eb76e4a5c1a3eb8c32fFelipe Balbi#endif /* end of ifndef _CPPI_DMA_H_ */ 135