cppi_dma.h revision 550a7375fe720924241f0eb76e4a5c1a3eb8c32f 
1/* Copyright (C) 2005-2006 by Texas Instruments */
2
3#ifndef _CPPI_DMA_H_
4#define _CPPI_DMA_H_
5
6#include <linux/slab.h>
7#include <linux/list.h>
8#include <linux/smp_lock.h>
9#include <linux/errno.h>
10#include <linux/dmapool.h>
11
12#include "musb_dma.h"
13#include "musb_core.h"
14
15
16/* FIXME fully isolate CPPI from DaVinci ... the "CPPI generic" registers
17 * would seem to be shared with the TUSB6020 (over VLYNQ).
18 */
19
20#include "davinci.h"
21
22
23/* CPPI RX/TX state RAM */
24
25struct cppi_tx_stateram {
26	u32 tx_head;			/* "DMA packet" head descriptor */
27	u32 tx_buf;
28	u32 tx_current;			/* current descriptor */
29	u32 tx_buf_current;
30	u32 tx_info;			/* flags, remaining buflen */
31	u32 tx_rem_len;
32	u32 tx_dummy;			/* unused */
33	u32 tx_complete;
34};
35
36struct cppi_rx_stateram {
37	u32 rx_skipbytes;
38	u32 rx_head;
39	u32 rx_sop;			/* "DMA packet" head descriptor */
40	u32 rx_current;			/* current descriptor */
41	u32 rx_buf_current;
42	u32 rx_len_len;
43	u32 rx_cnt_cnt;
44	u32 rx_complete;
45};
46
47/* hw_options bits in CPPI buffer descriptors */
48#define CPPI_SOP_SET	((u32)(1 << 31))
49#define CPPI_EOP_SET	((u32)(1 << 30))
50#define CPPI_OWN_SET	((u32)(1 << 29))	/* owned by cppi */
51#define CPPI_EOQ_MASK	((u32)(1 << 28))
52#define CPPI_ZERO_SET	((u32)(1 << 23))	/* rx saw zlp; tx issues one */
53#define CPPI_RXABT_MASK	((u32)(1 << 19))	/* need more rx buffers */
54
55#define CPPI_RECV_PKTLEN_MASK 0xFFFF
56#define CPPI_BUFFER_LEN_MASK 0xFFFF
57
58#define CPPI_TEAR_READY ((u32)(1 << 31))
59
60/* CPPI data structure definitions */
61
62#define	CPPI_DESCRIPTOR_ALIGN	16	/* bytes; 5-dec docs say 4-byte align */
63
64struct cppi_descriptor {
65	/* hardware overlay */
66	u32		hw_next;	/* next buffer descriptor Pointer */
67	u32		hw_bufp;	/* i/o buffer pointer */
68	u32		hw_off_len;	/* buffer_offset16, buffer_length16 */
69	u32		hw_options;	/* flags:  SOP, EOP etc*/
70
71	struct cppi_descriptor *next;
72	dma_addr_t	dma;		/* address of this descriptor */
73	u32		buflen;		/* for RX: original buffer length */
74} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN)));
75
76
77struct cppi;
78
79/* CPPI  Channel Control structure */
80struct cppi_channel {
81	struct dma_channel	channel;
82
83	/* back pointer to the DMA controller structure */
84	struct cppi		*controller;
85
86	/* which direction of which endpoint? */
87	struct musb_hw_ep	*hw_ep;
88	bool			transmit;
89	u8			index;
90
91	/* DMA modes:  RNDIS or "transparent" */
92	u8			is_rndis;
93
94	/* book keeping for current transfer request */
95	dma_addr_t		buf_dma;
96	u32			buf_len;
97	u32			maxpacket;
98	u32			offset;		/* dma requested */
99
100	void __iomem		*state_ram;	/* CPPI state */
101
102	struct cppi_descriptor	*freelist;
103
104	/* BD management fields */
105	struct cppi_descriptor	*head;
106	struct cppi_descriptor	*tail;
107	struct cppi_descriptor	*last_processed;
108
109	/* use tx_complete in host role to track endpoints waiting for
110	 * FIFONOTEMPTY to clear.
111	 */
112	struct list_head	tx_complete;
113};
114
115/* CPPI DMA controller object */
116struct cppi {
117	struct dma_controller		controller;
118	struct musb			*musb;
119	void __iomem			*mregs;		/* Mentor regs */
120	void __iomem			*tibase;	/* TI/CPPI regs */
121
122	struct cppi_channel		tx[MUSB_C_NUM_EPT - 1];
123	struct cppi_channel		rx[MUSB_C_NUM_EPR - 1];
124
125	struct dma_pool			*pool;
126
127	struct list_head		tx_complete;
128};
129
130/* irq handling hook */
131extern void cppi_completion(struct musb *, u32 rx, u32 tx);
132
133#endif				/* end of ifndef _CPPI_DMA_H_ */
134