intelfbhw.c revision 16109b3f4c1f2635afd32eb6d49348590de2cb25
1/* 2 * intelfb 3 * 4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips. 5 * 6 * Copyright � 2002, 2003 David Dawes <dawes@xfree86.org> 7 * 2004 Sylvain Meyer 8 * 9 * This driver consists of two parts. The first part (intelfbdrv.c) provides 10 * the basic fbdev interfaces, is derived in part from the radeonfb and 11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c) 12 * provides the code to program the hardware. Most of it is derived from 13 * the i810/i830 XFree86 driver. The HW-specific code is covered here 14 * under a dual license (GPL and MIT/XFree86 license). 15 * 16 * Author: David Dawes 17 * 18 */ 19 20/* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */ 21 22#include <linux/config.h> 23#include <linux/module.h> 24#include <linux/kernel.h> 25#include <linux/errno.h> 26#include <linux/string.h> 27#include <linux/mm.h> 28#include <linux/tty.h> 29#include <linux/slab.h> 30#include <linux/delay.h> 31#include <linux/fb.h> 32#include <linux/ioport.h> 33#include <linux/init.h> 34#include <linux/pci.h> 35#include <linux/vmalloc.h> 36#include <linux/pagemap.h> 37 38#include <asm/io.h> 39 40#include "intelfb.h" 41#include "intelfbhw.h" 42 43struct pll_min_max { 44 int min_m, max_m; 45 int min_m1, max_m1; 46 int min_m2, max_m2; 47 int min_n, max_n; 48 int min_p, max_p; 49 int min_p1, max_p1; 50 int min_vco_freq, max_vco_freq; 51 int p_transition_clock; 52 int p_inc_lo, p_inc_hi; 53}; 54 55#define PLLS_I8xx 0 56#define PLLS_I9xx 1 57#define PLLS_MAX 2 58 59struct pll_min_max plls[PLLS_MAX] = { 60 { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx 61 { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 } //I9xx 62}; 63 64int 65intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo) 66{ 67 u32 tmp; 68 if (!pdev || !dinfo) 69 return 1; 70 71 switch (pdev->device) { 72 case PCI_DEVICE_ID_INTEL_830M: 73 dinfo->name = "Intel(R) 830M"; 74 dinfo->chipset = INTEL_830M; 75 dinfo->mobile = 1; 76 dinfo->pll_index = PLLS_I8xx; 77 return 0; 78 case PCI_DEVICE_ID_INTEL_845G: 79 dinfo->name = "Intel(R) 845G"; 80 dinfo->chipset = INTEL_845G; 81 dinfo->mobile = 0; 82 dinfo->pll_index = PLLS_I8xx; 83 return 0; 84 case PCI_DEVICE_ID_INTEL_85XGM: 85 tmp = 0; 86 dinfo->mobile = 1; 87 dinfo->pll_index = PLLS_I8xx; 88 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp); 89 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) & 90 INTEL_85X_VARIANT_MASK) { 91 case INTEL_VAR_855GME: 92 dinfo->name = "Intel(R) 855GME"; 93 dinfo->chipset = INTEL_855GME; 94 return 0; 95 case INTEL_VAR_855GM: 96 dinfo->name = "Intel(R) 855GM"; 97 dinfo->chipset = INTEL_855GM; 98 return 0; 99 case INTEL_VAR_852GME: 100 dinfo->name = "Intel(R) 852GME"; 101 dinfo->chipset = INTEL_852GME; 102 return 0; 103 case INTEL_VAR_852GM: 104 dinfo->name = "Intel(R) 852GM"; 105 dinfo->chipset = INTEL_852GM; 106 return 0; 107 default: 108 dinfo->name = "Intel(R) 852GM/855GM"; 109 dinfo->chipset = INTEL_85XGM; 110 return 0; 111 } 112 break; 113 case PCI_DEVICE_ID_INTEL_865G: 114 dinfo->name = "Intel(R) 865G"; 115 dinfo->chipset = INTEL_865G; 116 dinfo->mobile = 0; 117 dinfo->pll_index = PLLS_I8xx; 118 return 0; 119 case PCI_DEVICE_ID_INTEL_915G: 120 dinfo->name = "Intel(R) 915G"; 121 dinfo->chipset = INTEL_915G; 122 dinfo->mobile = 0; 123 dinfo->pll_index = PLLS_I9xx; 124 return 0; 125 case PCI_DEVICE_ID_INTEL_915GM: 126 dinfo->name = "Intel(R) 915GM"; 127 dinfo->chipset = INTEL_915GM; 128 dinfo->mobile = 1; 129 dinfo->pll_index = PLLS_I9xx; 130 return 0; 131 default: 132 return 1; 133 } 134} 135 136int 137intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size, 138 int *stolen_size) 139{ 140 struct pci_dev *bridge_dev; 141 u16 tmp; 142 143 if (!pdev || !aperture_size || !stolen_size) 144 return 1; 145 146 /* Find the bridge device. It is always 0:0.0 */ 147 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) { 148 ERR_MSG("cannot find bridge device\n"); 149 return 1; 150 } 151 152 /* Get the fb aperture size and "stolen" memory amount. */ 153 tmp = 0; 154 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); 155 switch (pdev->device) { 156 case PCI_DEVICE_ID_INTEL_830M: 157 case PCI_DEVICE_ID_INTEL_845G: 158 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) 159 *aperture_size = MB(64); 160 else 161 *aperture_size = MB(128); 162 switch (tmp & INTEL_830_GMCH_GMS_MASK) { 163 case INTEL_830_GMCH_GMS_STOLEN_512: 164 *stolen_size = KB(512) - KB(132); 165 return 0; 166 case INTEL_830_GMCH_GMS_STOLEN_1024: 167 *stolen_size = MB(1) - KB(132); 168 return 0; 169 case INTEL_830_GMCH_GMS_STOLEN_8192: 170 *stolen_size = MB(8) - KB(132); 171 return 0; 172 case INTEL_830_GMCH_GMS_LOCAL: 173 ERR_MSG("only local memory found\n"); 174 return 1; 175 case INTEL_830_GMCH_GMS_DISABLED: 176 ERR_MSG("video memory is disabled\n"); 177 return 1; 178 default: 179 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n", 180 tmp & INTEL_830_GMCH_GMS_MASK); 181 return 1; 182 } 183 break; 184 default: 185 *aperture_size = MB(128); 186 switch (tmp & INTEL_855_GMCH_GMS_MASK) { 187 case INTEL_855_GMCH_GMS_STOLEN_1M: 188 *stolen_size = MB(1) - KB(132); 189 return 0; 190 case INTEL_855_GMCH_GMS_STOLEN_4M: 191 *stolen_size = MB(4) - KB(132); 192 return 0; 193 case INTEL_855_GMCH_GMS_STOLEN_8M: 194 *stolen_size = MB(8) - KB(132); 195 return 0; 196 case INTEL_855_GMCH_GMS_STOLEN_16M: 197 *stolen_size = MB(16) - KB(132); 198 return 0; 199 case INTEL_855_GMCH_GMS_STOLEN_32M: 200 *stolen_size = MB(32) - KB(132); 201 return 0; 202 case INTEL_915G_GMCH_GMS_STOLEN_48M: 203 *stolen_size = MB(48) - KB(132); 204 return 0; 205 case INTEL_915G_GMCH_GMS_STOLEN_64M: 206 *stolen_size = MB(64) - KB(132); 207 return 0; 208 case INTEL_855_GMCH_GMS_DISABLED: 209 ERR_MSG("video memory is disabled\n"); 210 return 0; 211 default: 212 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n", 213 tmp & INTEL_855_GMCH_GMS_MASK); 214 return 1; 215 } 216 } 217} 218 219int 220intelfbhw_check_non_crt(struct intelfb_info *dinfo) 221{ 222 int dvo = 0; 223 224 if (INREG(LVDS) & PORT_ENABLE) 225 dvo |= LVDS_PORT; 226 if (INREG(DVOA) & PORT_ENABLE) 227 dvo |= DVOA_PORT; 228 if (INREG(DVOB) & PORT_ENABLE) 229 dvo |= DVOB_PORT; 230 if (INREG(DVOC) & PORT_ENABLE) 231 dvo |= DVOC_PORT; 232 233 return dvo; 234} 235 236const char * 237intelfbhw_dvo_to_string(int dvo) 238{ 239 if (dvo & DVOA_PORT) 240 return "DVO port A"; 241 else if (dvo & DVOB_PORT) 242 return "DVO port B"; 243 else if (dvo & DVOC_PORT) 244 return "DVO port C"; 245 else if (dvo & LVDS_PORT) 246 return "LVDS port"; 247 else 248 return NULL; 249} 250 251 252int 253intelfbhw_validate_mode(struct intelfb_info *dinfo, 254 struct fb_var_screeninfo *var) 255{ 256 int bytes_per_pixel; 257 int tmp; 258 259#if VERBOSE > 0 260 DBG_MSG("intelfbhw_validate_mode\n"); 261#endif 262 263 bytes_per_pixel = var->bits_per_pixel / 8; 264 if (bytes_per_pixel == 3) 265 bytes_per_pixel = 4; 266 267 /* Check if enough video memory. */ 268 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel; 269 if (tmp > dinfo->fb.size) { 270 WRN_MSG("Not enough video ram for mode " 271 "(%d KByte vs %d KByte).\n", 272 BtoKB(tmp), BtoKB(dinfo->fb.size)); 273 return 1; 274 } 275 276 /* Check if x/y limits are OK. */ 277 if (var->xres - 1 > HACTIVE_MASK) { 278 WRN_MSG("X resolution too large (%d vs %d).\n", 279 var->xres, HACTIVE_MASK + 1); 280 return 1; 281 } 282 if (var->yres - 1 > VACTIVE_MASK) { 283 WRN_MSG("Y resolution too large (%d vs %d).\n", 284 var->yres, VACTIVE_MASK + 1); 285 return 1; 286 } 287 288 /* Check for interlaced/doublescan modes. */ 289 if (var->vmode & FB_VMODE_INTERLACED) { 290 WRN_MSG("Mode is interlaced.\n"); 291 return 1; 292 } 293 if (var->vmode & FB_VMODE_DOUBLE) { 294 WRN_MSG("Mode is double-scan.\n"); 295 return 1; 296 } 297 298 /* Check if clock is OK. */ 299 tmp = 1000000000 / var->pixclock; 300 if (tmp < MIN_CLOCK) { 301 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n", 302 (tmp + 500) / 1000, MIN_CLOCK / 1000); 303 return 1; 304 } 305 if (tmp > MAX_CLOCK) { 306 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n", 307 (tmp + 500) / 1000, MAX_CLOCK / 1000); 308 return 1; 309 } 310 311 return 0; 312} 313 314int 315intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 316{ 317 struct intelfb_info *dinfo = GET_DINFO(info); 318 u32 offset, xoffset, yoffset; 319 320#if VERBOSE > 0 321 DBG_MSG("intelfbhw_pan_display\n"); 322#endif 323 324 xoffset = ROUND_DOWN_TO(var->xoffset, 8); 325 yoffset = var->yoffset; 326 327 if ((xoffset + var->xres > var->xres_virtual) || 328 (yoffset + var->yres > var->yres_virtual)) 329 return -EINVAL; 330 331 offset = (yoffset * dinfo->pitch) + 332 (xoffset * var->bits_per_pixel) / 8; 333 334 offset += dinfo->fb.offset << 12; 335 336 OUTREG(DSPABASE, offset); 337 338 return 0; 339} 340 341/* Blank the screen. */ 342void 343intelfbhw_do_blank(int blank, struct fb_info *info) 344{ 345 struct intelfb_info *dinfo = GET_DINFO(info); 346 u32 tmp; 347 348#if VERBOSE > 0 349 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank); 350#endif 351 352 /* Turn plane A on or off */ 353 tmp = INREG(DSPACNTR); 354 if (blank) 355 tmp &= ~DISPPLANE_PLANE_ENABLE; 356 else 357 tmp |= DISPPLANE_PLANE_ENABLE; 358 OUTREG(DSPACNTR, tmp); 359 /* Flush */ 360 tmp = INREG(DSPABASE); 361 OUTREG(DSPABASE, tmp); 362 363 /* Turn off/on the HW cursor */ 364#if VERBOSE > 0 365 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on); 366#endif 367 if (dinfo->cursor_on) { 368 if (blank) { 369 intelfbhw_cursor_hide(dinfo); 370 } else { 371 intelfbhw_cursor_show(dinfo); 372 } 373 dinfo->cursor_on = 1; 374 } 375 dinfo->cursor_blanked = blank; 376 377 /* Set DPMS level */ 378 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK; 379 switch (blank) { 380 case FB_BLANK_UNBLANK: 381 case FB_BLANK_NORMAL: 382 tmp |= ADPA_DPMS_D0; 383 break; 384 case FB_BLANK_VSYNC_SUSPEND: 385 tmp |= ADPA_DPMS_D1; 386 break; 387 case FB_BLANK_HSYNC_SUSPEND: 388 tmp |= ADPA_DPMS_D2; 389 break; 390 case FB_BLANK_POWERDOWN: 391 tmp |= ADPA_DPMS_D3; 392 break; 393 } 394 OUTREG(ADPA, tmp); 395 396 return; 397} 398 399 400void 401intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno, 402 unsigned red, unsigned green, unsigned blue, 403 unsigned transp) 404{ 405#if VERBOSE > 0 406 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n", 407 regno, red, green, blue); 408#endif 409 410 u32 palette_reg = (dinfo->pipe == PIPE_A) ? 411 PALETTE_A : PALETTE_B; 412 413 OUTREG(palette_reg + (regno << 2), 414 (red << PALETTE_8_RED_SHIFT) | 415 (green << PALETTE_8_GREEN_SHIFT) | 416 (blue << PALETTE_8_BLUE_SHIFT)); 417} 418 419 420int 421intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, 422 int flag) 423{ 424 int i; 425 426#if VERBOSE > 0 427 DBG_MSG("intelfbhw_read_hw_state\n"); 428#endif 429 430 if (!hw || !dinfo) 431 return -1; 432 433 /* Read in as much of the HW state as possible. */ 434 hw->vga0_divisor = INREG(VGA0_DIVISOR); 435 hw->vga1_divisor = INREG(VGA1_DIVISOR); 436 hw->vga_pd = INREG(VGAPD); 437 hw->dpll_a = INREG(DPLL_A); 438 hw->dpll_b = INREG(DPLL_B); 439 hw->fpa0 = INREG(FPA0); 440 hw->fpa1 = INREG(FPA1); 441 hw->fpb0 = INREG(FPB0); 442 hw->fpb1 = INREG(FPB1); 443 444 if (flag == 1) 445 return flag; 446 447#if 0 448 /* This seems to be a problem with the 852GM/855GM */ 449 for (i = 0; i < PALETTE_8_ENTRIES; i++) { 450 hw->palette_a[i] = INREG(PALETTE_A + (i << 2)); 451 hw->palette_b[i] = INREG(PALETTE_B + (i << 2)); 452 } 453#endif 454 455 if (flag == 2) 456 return flag; 457 458 hw->htotal_a = INREG(HTOTAL_A); 459 hw->hblank_a = INREG(HBLANK_A); 460 hw->hsync_a = INREG(HSYNC_A); 461 hw->vtotal_a = INREG(VTOTAL_A); 462 hw->vblank_a = INREG(VBLANK_A); 463 hw->vsync_a = INREG(VSYNC_A); 464 hw->src_size_a = INREG(SRC_SIZE_A); 465 hw->bclrpat_a = INREG(BCLRPAT_A); 466 hw->htotal_b = INREG(HTOTAL_B); 467 hw->hblank_b = INREG(HBLANK_B); 468 hw->hsync_b = INREG(HSYNC_B); 469 hw->vtotal_b = INREG(VTOTAL_B); 470 hw->vblank_b = INREG(VBLANK_B); 471 hw->vsync_b = INREG(VSYNC_B); 472 hw->src_size_b = INREG(SRC_SIZE_B); 473 hw->bclrpat_b = INREG(BCLRPAT_B); 474 475 if (flag == 3) 476 return flag; 477 478 hw->adpa = INREG(ADPA); 479 hw->dvoa = INREG(DVOA); 480 hw->dvob = INREG(DVOB); 481 hw->dvoc = INREG(DVOC); 482 hw->dvoa_srcdim = INREG(DVOA_SRCDIM); 483 hw->dvob_srcdim = INREG(DVOB_SRCDIM); 484 hw->dvoc_srcdim = INREG(DVOC_SRCDIM); 485 hw->lvds = INREG(LVDS); 486 487 if (flag == 4) 488 return flag; 489 490 hw->pipe_a_conf = INREG(PIPEACONF); 491 hw->pipe_b_conf = INREG(PIPEBCONF); 492 hw->disp_arb = INREG(DISPARB); 493 494 if (flag == 5) 495 return flag; 496 497 hw->cursor_a_control = INREG(CURSOR_A_CONTROL); 498 hw->cursor_b_control = INREG(CURSOR_B_CONTROL); 499 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR); 500 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR); 501 502 if (flag == 6) 503 return flag; 504 505 for (i = 0; i < 4; i++) { 506 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2)); 507 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2)); 508 } 509 510 if (flag == 7) 511 return flag; 512 513 hw->cursor_size = INREG(CURSOR_SIZE); 514 515 if (flag == 8) 516 return flag; 517 518 hw->disp_a_ctrl = INREG(DSPACNTR); 519 hw->disp_b_ctrl = INREG(DSPBCNTR); 520 hw->disp_a_base = INREG(DSPABASE); 521 hw->disp_b_base = INREG(DSPBBASE); 522 hw->disp_a_stride = INREG(DSPASTRIDE); 523 hw->disp_b_stride = INREG(DSPBSTRIDE); 524 525 if (flag == 9) 526 return flag; 527 528 hw->vgacntrl = INREG(VGACNTRL); 529 530 if (flag == 10) 531 return flag; 532 533 hw->add_id = INREG(ADD_ID); 534 535 if (flag == 11) 536 return flag; 537 538 for (i = 0; i < 7; i++) { 539 hw->swf0x[i] = INREG(SWF00 + (i << 2)); 540 hw->swf1x[i] = INREG(SWF10 + (i << 2)); 541 if (i < 3) 542 hw->swf3x[i] = INREG(SWF30 + (i << 2)); 543 } 544 545 for (i = 0; i < 8; i++) 546 hw->fence[i] = INREG(FENCE + (i << 2)); 547 548 hw->instpm = INREG(INSTPM); 549 hw->mem_mode = INREG(MEM_MODE); 550 hw->fw_blc_0 = INREG(FW_BLC_0); 551 hw->fw_blc_1 = INREG(FW_BLC_1); 552 553 return 0; 554} 555 556 557static int calc_vclock3(int index, int m, int n, int p) 558{ 559 return PLL_REFCLK * m / n / p; 560} 561 562static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2) 563{ 564 switch(index) 565 { 566 case PLLS_I9xx: 567 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / 568 ((p1)) * (p2 ? 10 : 5))); 569 case PLLS_I8xx: 570 default: 571 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / 572 ((p1+2) * (1 << (p2 + 1))))); 573 } 574} 575 576void 577intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) 578{ 579#if REGDUMP 580 int i, m1, m2, n, p1, p2; 581 int index = dinfo->pll_index; 582 DBG_MSG("intelfbhw_print_hw_state\n"); 583 584 if (!hw || !dinfo) 585 return; 586 /* Read in as much of the HW state as possible. */ 587 printk("hw state dump start\n"); 588 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor); 589 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor); 590 printk(" VGAPD: 0x%08x\n", hw->vga_pd); 591 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 592 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 593 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 594 if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2) 595 p1 = 0; 596 else 597 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK; 598 p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK; 599 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 600 m1, m2, n, p1, p2); 601 printk(" VGA0: clock is %d\n", 602 calc_vclock(index, m1, m2, n, p1, p2)); 603 604 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 605 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 606 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 607 if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2) 608 p1 = 0; 609 else 610 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK; 611 p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK; 612 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 613 m1, m2, n, p1, p2); 614 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); 615 616 printk(" DPLL_A: 0x%08x\n", hw->dpll_a); 617 printk(" DPLL_B: 0x%08x\n", hw->dpll_b); 618 printk(" FPA0: 0x%08x\n", hw->fpa0); 619 printk(" FPA1: 0x%08x\n", hw->fpa1); 620 printk(" FPB0: 0x%08x\n", hw->fpb0); 621 printk(" FPB1: 0x%08x\n", hw->fpb1); 622 623 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 624 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 625 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 626 if (hw->dpll_a & DPLL_P1_FORCE_DIV2) 627 p1 = 0; 628 else 629 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; 630 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; 631 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 632 m1, m2, n, p1, p2); 633 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); 634 635 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 636 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 637 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 638 if (hw->dpll_a & DPLL_P1_FORCE_DIV2) 639 p1 = 0; 640 else 641 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; 642 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; 643 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 644 m1, m2, n, p1, p2); 645 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); 646 647#if 0 648 printk(" PALETTE_A:\n"); 649 for (i = 0; i < PALETTE_8_ENTRIES) 650 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]); 651 printk(" PALETTE_B:\n"); 652 for (i = 0; i < PALETTE_8_ENTRIES) 653 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]); 654#endif 655 656 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); 657 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a); 658 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a); 659 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a); 660 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a); 661 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a); 662 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a); 663 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a); 664 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b); 665 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b); 666 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b); 667 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b); 668 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b); 669 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b); 670 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b); 671 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b); 672 673 printk(" ADPA: 0x%08x\n", hw->adpa); 674 printk(" DVOA: 0x%08x\n", hw->dvoa); 675 printk(" DVOB: 0x%08x\n", hw->dvob); 676 printk(" DVOC: 0x%08x\n", hw->dvoc); 677 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim); 678 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim); 679 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim); 680 printk(" LVDS: 0x%08x\n", hw->lvds); 681 682 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf); 683 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf); 684 printk(" DISPARB: 0x%08x\n", hw->disp_arb); 685 686 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control); 687 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control); 688 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base); 689 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base); 690 691 printk(" CURSOR_A_PALETTE: "); 692 for (i = 0; i < 4; i++) { 693 printk("0x%08x", hw->cursor_a_palette[i]); 694 if (i < 3) 695 printk(", "); 696 } 697 printk("\n"); 698 printk(" CURSOR_B_PALETTE: "); 699 for (i = 0; i < 4; i++) { 700 printk("0x%08x", hw->cursor_b_palette[i]); 701 if (i < 3) 702 printk(", "); 703 } 704 printk("\n"); 705 706 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size); 707 708 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl); 709 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl); 710 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base); 711 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base); 712 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride); 713 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride); 714 715 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl); 716 printk(" ADD_ID: 0x%08x\n", hw->add_id); 717 718 for (i = 0; i < 7; i++) { 719 printk(" SWF0%d 0x%08x\n", i, 720 hw->swf0x[i]); 721 } 722 for (i = 0; i < 7; i++) { 723 printk(" SWF1%d 0x%08x\n", i, 724 hw->swf1x[i]); 725 } 726 for (i = 0; i < 3; i++) { 727 printk(" SWF3%d 0x%08x\n", i, 728 hw->swf3x[i]); 729 } 730 for (i = 0; i < 8; i++) 731 printk(" FENCE%d 0x%08x\n", i, 732 hw->fence[i]); 733 734 printk(" INSTPM 0x%08x\n", hw->instpm); 735 printk(" MEM_MODE 0x%08x\n", hw->mem_mode); 736 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); 737 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1); 738 739 printk("hw state dump end\n"); 740#endif 741} 742 743 744 745/* Split the M parameter into M1 and M2. */ 746static int 747splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2) 748{ 749 int m1, m2; 750 int testm; 751 /* no point optimising too much - brute force m */ 752 for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) 753 { 754 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) 755 { 756 testm = ( 5 * ( m1 + 2 )) + (m2 + 2); 757 if (testm == m) 758 { 759 *retm1 = (unsigned int)m1; 760 *retm2 = (unsigned int)m2; 761 return 0; 762 } 763 } 764 } 765 return 1; 766} 767 768/* Split the P parameter into P1 and P2. */ 769static int 770splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2) 771{ 772 int p1, p2; 773 774 if (index == PLLS_I9xx) 775 { 776 p1 = (p / 10) + 1; 777 p2 = 0; 778 779 *retp1 = (unsigned int)p1; 780 *retp2 = (unsigned int)p2; 781 return 0; 782 } 783 784 if (index == PLLS_I8xx) 785 { 786 if (p % 4 == 0) 787 p2 = 1; 788 else 789 p2 = 0; 790 p1 = (p / (1 << (p2 + 1))) - 2; 791 if (p % 4 == 0 && p1 < plls[index].min_p1) { 792 p2 = 0; 793 p1 = (p / (1 << (p2 + 1))) - 2; 794 } 795 if (p1 < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) { 796 return 1; 797 } else { 798 *retp1 = (unsigned int)p1; 799 *retp2 = (unsigned int)p2; 800 return 0; 801 } 802 } 803 return 1; 804} 805 806static int 807calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1, 808 u32 *retp2, u32 *retclock) 809{ 810 u32 m1, m2, n, p1, p2, n1; 811 u32 f_vco, p, p_best = 0, m, f_out; 812 u32 err_max, err_target, err_best = 10000000; 813 u32 n_best = 0, m_best = 0, f_best, f_err; 814 u32 p_min, p_max, p_inc, div_min, div_max; 815 816 /* Accept 0.5% difference, but aim for 0.1% */ 817 err_max = 5 * clock / 1000; 818 err_target = clock / 1000; 819 820 DBG_MSG("Clock is %d\n", clock); 821 822 div_max = plls[index].max_vco_freq / clock; 823 div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock; 824 825 if (clock <= plls[index].p_transition_clock) 826 p_inc = plls[index].p_inc_lo; 827 else 828 p_inc = plls[index].p_inc_hi; 829 p_min = ROUND_UP_TO(div_min, p_inc); 830 p_max = ROUND_DOWN_TO(div_max, p_inc); 831 if (p_min < plls[index].min_p) 832 p_min = plls[index].min_p; 833 if (p_max > plls[index].max_p) 834 p_max = plls[index].max_p; 835 836 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc); 837 838 p = p_min; 839 do { 840 if (splitp(index, p, &p1, &p2)) { 841 WRN_MSG("cannot split p = %d\n", p); 842 p += p_inc; 843 continue; 844 } 845 n = plls[index].min_n; 846 f_vco = clock * p; 847 848 do { 849 m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK; 850 if (m < plls[index].min_m) 851 m = plls[index].min_m; 852 if (m > plls[index].max_m) 853 m = plls[index].max_m; 854 f_out = calc_vclock3(index, m, n, p); 855 if (splitm(index, m, &m1, &m2)) { 856 WRN_MSG("cannot split m = %d\n", m); 857 n++; 858 continue; 859 } 860 if (clock > f_out) 861 f_err = clock - f_out; 862 else 863 f_err = f_out - clock; 864 865 if (f_err < err_best) { 866 m_best = m; 867 n_best = n; 868 p_best = p; 869 f_best = f_out; 870 err_best = f_err; 871 } 872 n++; 873 } while ((n <= plls[index].max_n) && (f_out >= clock)); 874 p += p_inc; 875 } while ((p <= p_max)); 876 877 if (!m_best) { 878 WRN_MSG("cannot find parameters for clock %d\n", clock); 879 return 1; 880 } 881 m = m_best; 882 n = n_best; 883 p = p_best; 884 splitm(index, m, &m1, &m2); 885 splitp(index, p, &p1, &p2); 886 n1 = n - 2; 887 888 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), " 889 "f: %d (%d), VCO: %d\n", 890 m, m1, m2, n, n1, p, p1, p2, 891 calc_vclock3(index, m, n, p), 892 calc_vclock(index, m1, m2, n1, p1, p2), 893 calc_vclock3(index, m, n, p) * p); 894 *retm1 = m1; 895 *retm2 = m2; 896 *retn = n1; 897 *retp1 = p1; 898 *retp2 = p2; 899 *retclock = calc_vclock(index, m1, m2, n1, p1, p2); 900 901 return 0; 902} 903 904static __inline__ int 905check_overflow(u32 value, u32 limit, const char *description) 906{ 907 if (value > limit) { 908 WRN_MSG("%s value %d exceeds limit %d\n", 909 description, value, limit); 910 return 1; 911 } 912 return 0; 913} 914 915/* It is assumed that hw is filled in with the initial state information. */ 916int 917intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, 918 struct fb_var_screeninfo *var) 919{ 920 int pipe = PIPE_A; 921 u32 *dpll, *fp0, *fp1; 922 u32 m1, m2, n, p1, p2, clock_target, clock; 923 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive; 924 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive; 925 u32 vsync_pol, hsync_pol; 926 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf; 927 928 DBG_MSG("intelfbhw_mode_to_hw\n"); 929 930 /* Disable VGA */ 931 hw->vgacntrl |= VGA_DISABLE; 932 933 /* Check whether pipe A or pipe B is enabled. */ 934 if (hw->pipe_a_conf & PIPECONF_ENABLE) 935 pipe = PIPE_A; 936 else if (hw->pipe_b_conf & PIPECONF_ENABLE) 937 pipe = PIPE_B; 938 939 /* Set which pipe's registers will be set. */ 940 if (pipe == PIPE_B) { 941 dpll = &hw->dpll_b; 942 fp0 = &hw->fpb0; 943 fp1 = &hw->fpb1; 944 hs = &hw->hsync_b; 945 hb = &hw->hblank_b; 946 ht = &hw->htotal_b; 947 vs = &hw->vsync_b; 948 vb = &hw->vblank_b; 949 vt = &hw->vtotal_b; 950 ss = &hw->src_size_b; 951 pipe_conf = &hw->pipe_b_conf; 952 } else { 953 dpll = &hw->dpll_a; 954 fp0 = &hw->fpa0; 955 fp1 = &hw->fpa1; 956 hs = &hw->hsync_a; 957 hb = &hw->hblank_a; 958 ht = &hw->htotal_a; 959 vs = &hw->vsync_a; 960 vb = &hw->vblank_a; 961 vt = &hw->vtotal_a; 962 ss = &hw->src_size_a; 963 pipe_conf = &hw->pipe_a_conf; 964 } 965 966 /* Use ADPA register for sync control. */ 967 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY; 968 969 /* sync polarity */ 970 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 971 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW; 972 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 973 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW; 974 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) | 975 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT)); 976 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) | 977 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT); 978 979 /* Connect correct pipe to the analog port DAC */ 980 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT); 981 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT); 982 983 /* Set DPMS state to D0 (on) */ 984 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK; 985 hw->adpa |= ADPA_DPMS_D0; 986 987 hw->adpa |= ADPA_DAC_ENABLE; 988 989 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); 990 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK); 991 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0); 992 993 /* Desired clock in kHz */ 994 clock_target = 1000000000 / var->pixclock; 995 996 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) { 997 WRN_MSG("calc_pll_params failed\n"); 998 return 1; 999 } 1000 1001 /* Check for overflow. */ 1002 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter")) 1003 return 1; 1004 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter")) 1005 return 1; 1006 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter")) 1007 return 1; 1008 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter")) 1009 return 1; 1010 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter")) 1011 return 1; 1012 1013 *dpll &= ~DPLL_P1_FORCE_DIV2; 1014 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) | 1015 (DPLL_P1_MASK << DPLL_P1_SHIFT)); 1016 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT); 1017 *fp0 = (n << FP_N_DIVISOR_SHIFT) | 1018 (m1 << FP_M1_DIVISOR_SHIFT) | 1019 (m2 << FP_M2_DIVISOR_SHIFT); 1020 *fp1 = *fp0; 1021 1022 hw->dvob &= ~PORT_ENABLE; 1023 hw->dvoc &= ~PORT_ENABLE; 1024 1025 /* Use display plane A. */ 1026 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE; 1027 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE; 1028 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK; 1029 switch (intelfb_var_to_depth(var)) { 1030 case 8: 1031 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE; 1032 break; 1033 case 15: 1034 hw->disp_a_ctrl |= DISPPLANE_15_16BPP; 1035 break; 1036 case 16: 1037 hw->disp_a_ctrl |= DISPPLANE_16BPP; 1038 break; 1039 case 24: 1040 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA; 1041 break; 1042 } 1043 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT); 1044 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT); 1045 1046 /* Set CRTC registers. */ 1047 hactive = var->xres; 1048 hsync_start = hactive + var->right_margin; 1049 hsync_end = hsync_start + var->hsync_len; 1050 htotal = hsync_end + var->left_margin; 1051 hblank_start = hactive; 1052 hblank_end = htotal; 1053 1054 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n", 1055 hactive, hsync_start, hsync_end, htotal, hblank_start, 1056 hblank_end); 1057 1058 vactive = var->yres; 1059 vsync_start = vactive + var->lower_margin; 1060 vsync_end = vsync_start + var->vsync_len; 1061 vtotal = vsync_end + var->upper_margin; 1062 vblank_start = vactive; 1063 vblank_end = vtotal; 1064 vblank_end = vsync_end + 1; 1065 1066 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n", 1067 vactive, vsync_start, vsync_end, vtotal, vblank_start, 1068 vblank_end); 1069 1070 /* Adjust for register values, and check for overflow. */ 1071 hactive--; 1072 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive")) 1073 return 1; 1074 hsync_start--; 1075 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start")) 1076 return 1; 1077 hsync_end--; 1078 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end")) 1079 return 1; 1080 htotal--; 1081 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal")) 1082 return 1; 1083 hblank_start--; 1084 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start")) 1085 return 1; 1086 hblank_end--; 1087 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end")) 1088 return 1; 1089 1090 vactive--; 1091 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive")) 1092 return 1; 1093 vsync_start--; 1094 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start")) 1095 return 1; 1096 vsync_end--; 1097 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end")) 1098 return 1; 1099 vtotal--; 1100 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal")) 1101 return 1; 1102 vblank_start--; 1103 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start")) 1104 return 1; 1105 vblank_end--; 1106 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end")) 1107 return 1; 1108 1109 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT); 1110 *hb = (hblank_start << HBLANKSTART_SHIFT) | 1111 (hblank_end << HSYNCEND_SHIFT); 1112 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT); 1113 1114 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT); 1115 *vb = (vblank_start << VBLANKSTART_SHIFT) | 1116 (vblank_end << VSYNCEND_SHIFT); 1117 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT); 1118 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) | 1119 (vactive << SRC_SIZE_VERT_SHIFT); 1120 1121 hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8; 1122 DBG_MSG("pitch is %d\n", hw->disp_a_stride); 1123 1124 hw->disp_a_base = hw->disp_a_stride * var->yoffset + 1125 var->xoffset * var->bits_per_pixel / 8; 1126 1127 hw->disp_a_base += dinfo->fb.offset << 12; 1128 1129 /* Check stride alignment. */ 1130 if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) { 1131 WRN_MSG("display stride %d has bad alignment %d\n", 1132 hw->disp_a_stride, STRIDE_ALIGNMENT); 1133 return 1; 1134 } 1135 1136 /* Set the palette to 8-bit mode. */ 1137 *pipe_conf &= ~PIPECONF_GAMMA; 1138 return 0; 1139} 1140 1141/* Program a (non-VGA) video mode. */ 1142int 1143intelfbhw_program_mode(struct intelfb_info *dinfo, 1144 const struct intelfb_hwstate *hw, int blank) 1145{ 1146 int pipe = PIPE_A; 1147 u32 tmp; 1148 const u32 *dpll, *fp0, *fp1, *pipe_conf; 1149 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss; 1150 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg; 1151 u32 hsync_reg, htotal_reg, hblank_reg; 1152 u32 vsync_reg, vtotal_reg, vblank_reg; 1153 u32 src_size_reg; 1154 1155 /* Assume single pipe, display plane A, analog CRT. */ 1156 1157#if VERBOSE > 0 1158 DBG_MSG("intelfbhw_program_mode\n"); 1159#endif 1160 1161 /* Disable VGA */ 1162 tmp = INREG(VGACNTRL); 1163 tmp |= VGA_DISABLE; 1164 OUTREG(VGACNTRL, tmp); 1165 1166 /* Check whether pipe A or pipe B is enabled. */ 1167 if (hw->pipe_a_conf & PIPECONF_ENABLE) 1168 pipe = PIPE_A; 1169 else if (hw->pipe_b_conf & PIPECONF_ENABLE) 1170 pipe = PIPE_B; 1171 1172 dinfo->pipe = pipe; 1173 1174 if (pipe == PIPE_B) { 1175 dpll = &hw->dpll_b; 1176 fp0 = &hw->fpb0; 1177 fp1 = &hw->fpb1; 1178 pipe_conf = &hw->pipe_b_conf; 1179 hs = &hw->hsync_b; 1180 hb = &hw->hblank_b; 1181 ht = &hw->htotal_b; 1182 vs = &hw->vsync_b; 1183 vb = &hw->vblank_b; 1184 vt = &hw->vtotal_b; 1185 ss = &hw->src_size_b; 1186 dpll_reg = DPLL_B; 1187 fp0_reg = FPB0; 1188 fp1_reg = FPB1; 1189 pipe_conf_reg = PIPEBCONF; 1190 hsync_reg = HSYNC_B; 1191 htotal_reg = HTOTAL_B; 1192 hblank_reg = HBLANK_B; 1193 vsync_reg = VSYNC_B; 1194 vtotal_reg = VTOTAL_B; 1195 vblank_reg = VBLANK_B; 1196 src_size_reg = SRC_SIZE_B; 1197 } else { 1198 dpll = &hw->dpll_a; 1199 fp0 = &hw->fpa0; 1200 fp1 = &hw->fpa1; 1201 pipe_conf = &hw->pipe_a_conf; 1202 hs = &hw->hsync_a; 1203 hb = &hw->hblank_a; 1204 ht = &hw->htotal_a; 1205 vs = &hw->vsync_a; 1206 vb = &hw->vblank_a; 1207 vt = &hw->vtotal_a; 1208 ss = &hw->src_size_a; 1209 dpll_reg = DPLL_A; 1210 fp0_reg = FPA0; 1211 fp1_reg = FPA1; 1212 pipe_conf_reg = PIPEACONF; 1213 hsync_reg = HSYNC_A; 1214 htotal_reg = HTOTAL_A; 1215 hblank_reg = HBLANK_A; 1216 vsync_reg = VSYNC_A; 1217 vtotal_reg = VTOTAL_A; 1218 vblank_reg = VBLANK_A; 1219 src_size_reg = SRC_SIZE_A; 1220 } 1221 1222 /* Disable planes A and B. */ 1223 tmp = INREG(DSPACNTR); 1224 tmp &= ~DISPPLANE_PLANE_ENABLE; 1225 OUTREG(DSPACNTR, tmp); 1226 tmp = INREG(DSPBCNTR); 1227 tmp &= ~DISPPLANE_PLANE_ENABLE; 1228 OUTREG(DSPBCNTR, tmp); 1229 1230 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */ 1231 mdelay(20); 1232 1233 /* Disable Sync */ 1234 tmp = INREG(ADPA); 1235 tmp &= ~ADPA_DPMS_CONTROL_MASK; 1236 tmp |= ADPA_DPMS_D3; 1237 OUTREG(ADPA, tmp); 1238 1239 /* turn off pipe */ 1240 tmp = INREG(pipe_conf_reg); 1241 tmp &= ~PIPECONF_ENABLE; 1242 OUTREG(pipe_conf_reg, tmp); 1243 1244 /* turn off PLL */ 1245 tmp = INREG(dpll_reg); 1246 dpll_reg &= ~DPLL_VCO_ENABLE; 1247 OUTREG(dpll_reg, tmp); 1248 1249 /* Set PLL parameters */ 1250 OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE); 1251 OUTREG(fp0_reg, *fp0); 1252 OUTREG(fp1_reg, *fp1); 1253 1254 /* Set pipe parameters */ 1255 OUTREG(hsync_reg, *hs); 1256 OUTREG(hblank_reg, *hb); 1257 OUTREG(htotal_reg, *ht); 1258 OUTREG(vsync_reg, *vs); 1259 OUTREG(vblank_reg, *vb); 1260 OUTREG(vtotal_reg, *vt); 1261 OUTREG(src_size_reg, *ss); 1262 1263 /* Set DVOs B/C */ 1264 OUTREG(DVOB, hw->dvob); 1265 OUTREG(DVOC, hw->dvoc); 1266 1267 /* Set ADPA */ 1268 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3); 1269 1270 /* Enable PLL */ 1271 tmp = INREG(dpll_reg); 1272 tmp |= DPLL_VCO_ENABLE; 1273 OUTREG(dpll_reg, tmp); 1274 1275 /* Enable pipe */ 1276 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE); 1277 1278 /* Enable sync */ 1279 tmp = INREG(ADPA); 1280 tmp &= ~ADPA_DPMS_CONTROL_MASK; 1281 tmp |= ADPA_DPMS_D0; 1282 OUTREG(ADPA, tmp); 1283 1284 /* setup display plane */ 1285 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) { 1286 /* 1287 * i830M errata: the display plane must be enabled 1288 * to allow writes to the other bits in the plane 1289 * control register. 1290 */ 1291 tmp = INREG(DSPACNTR); 1292 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) { 1293 tmp |= DISPPLANE_PLANE_ENABLE; 1294 OUTREG(DSPACNTR, tmp); 1295 OUTREG(DSPACNTR, 1296 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE); 1297 mdelay(1); 1298 } 1299 } 1300 1301 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); 1302 OUTREG(DSPASTRIDE, hw->disp_a_stride); 1303 OUTREG(DSPABASE, hw->disp_a_base); 1304 1305 /* Enable plane */ 1306 if (!blank) { 1307 tmp = INREG(DSPACNTR); 1308 tmp |= DISPPLANE_PLANE_ENABLE; 1309 OUTREG(DSPACNTR, tmp); 1310 OUTREG(DSPABASE, hw->disp_a_base); 1311 } 1312 1313 return 0; 1314} 1315 1316/* forward declarations */ 1317static void refresh_ring(struct intelfb_info *dinfo); 1318static void reset_state(struct intelfb_info *dinfo); 1319static void do_flush(struct intelfb_info *dinfo); 1320 1321static int 1322wait_ring(struct intelfb_info *dinfo, int n) 1323{ 1324 int i = 0; 1325 unsigned long end; 1326 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; 1327 1328#if VERBOSE > 0 1329 DBG_MSG("wait_ring: %d\n", n); 1330#endif 1331 1332 end = jiffies + (HZ * 3); 1333 while (dinfo->ring_space < n) { 1334 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) & 1335 RING_HEAD_MASK); 1336 if (dinfo->ring_tail + RING_MIN_FREE < 1337 (u32 __iomem) dinfo->ring_head) 1338 dinfo->ring_space = (u32 __iomem) dinfo->ring_head 1339 - (dinfo->ring_tail + RING_MIN_FREE); 1340 else 1341 dinfo->ring_space = (dinfo->ring.size + 1342 (u32 __iomem) dinfo->ring_head) 1343 - (dinfo->ring_tail + RING_MIN_FREE); 1344 if ((u32 __iomem) dinfo->ring_head != last_head) { 1345 end = jiffies + (HZ * 3); 1346 last_head = (u32 __iomem) dinfo->ring_head; 1347 } 1348 i++; 1349 if (time_before(end, jiffies)) { 1350 if (!i) { 1351 /* Try again */ 1352 reset_state(dinfo); 1353 refresh_ring(dinfo); 1354 do_flush(dinfo); 1355 end = jiffies + (HZ * 3); 1356 i = 1; 1357 } else { 1358 WRN_MSG("ring buffer : space: %d wanted %d\n", 1359 dinfo->ring_space, n); 1360 WRN_MSG("lockup - turning off hardware " 1361 "acceleration\n"); 1362 dinfo->ring_lockup = 1; 1363 break; 1364 } 1365 } 1366 udelay(1); 1367 } 1368 return i; 1369} 1370 1371static void 1372do_flush(struct intelfb_info *dinfo) { 1373 START_RING(2); 1374 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); 1375 OUT_RING(MI_NOOP); 1376 ADVANCE_RING(); 1377} 1378 1379void 1380intelfbhw_do_sync(struct intelfb_info *dinfo) 1381{ 1382#if VERBOSE > 0 1383 DBG_MSG("intelfbhw_do_sync\n"); 1384#endif 1385 1386 if (!dinfo->accel) 1387 return; 1388 1389 /* 1390 * Send a flush, then wait until the ring is empty. This is what 1391 * the XFree86 driver does, and actually it doesn't seem a lot worse 1392 * than the recommended method (both have problems). 1393 */ 1394 do_flush(dinfo); 1395 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE); 1396 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE; 1397} 1398 1399static void 1400refresh_ring(struct intelfb_info *dinfo) 1401{ 1402#if VERBOSE > 0 1403 DBG_MSG("refresh_ring\n"); 1404#endif 1405 1406 dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) & 1407 RING_HEAD_MASK); 1408 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; 1409 if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head) 1410 dinfo->ring_space = (u32 __iomem) dinfo->ring_head 1411 - (dinfo->ring_tail + RING_MIN_FREE); 1412 else 1413 dinfo->ring_space = (dinfo->ring.size + 1414 (u32 __iomem) dinfo->ring_head) 1415 - (dinfo->ring_tail + RING_MIN_FREE); 1416} 1417 1418static void 1419reset_state(struct intelfb_info *dinfo) 1420{ 1421 int i; 1422 u32 tmp; 1423 1424#if VERBOSE > 0 1425 DBG_MSG("reset_state\n"); 1426#endif 1427 1428 for (i = 0; i < FENCE_NUM; i++) 1429 OUTREG(FENCE + (i << 2), 0); 1430 1431 /* Flush the ring buffer if it's enabled. */ 1432 tmp = INREG(PRI_RING_LENGTH); 1433 if (tmp & RING_ENABLE) { 1434#if VERBOSE > 0 1435 DBG_MSG("reset_state: ring was enabled\n"); 1436#endif 1437 refresh_ring(dinfo); 1438 intelfbhw_do_sync(dinfo); 1439 DO_RING_IDLE(); 1440 } 1441 1442 OUTREG(PRI_RING_LENGTH, 0); 1443 OUTREG(PRI_RING_HEAD, 0); 1444 OUTREG(PRI_RING_TAIL, 0); 1445 OUTREG(PRI_RING_START, 0); 1446} 1447 1448/* Stop the 2D engine, and turn off the ring buffer. */ 1449void 1450intelfbhw_2d_stop(struct intelfb_info *dinfo) 1451{ 1452#if VERBOSE > 0 1453 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel, 1454 dinfo->ring_active); 1455#endif 1456 1457 if (!dinfo->accel) 1458 return; 1459 1460 dinfo->ring_active = 0; 1461 reset_state(dinfo); 1462} 1463 1464/* 1465 * Enable the ring buffer, and initialise the 2D engine. 1466 * It is assumed that the graphics engine has been stopped by previously 1467 * calling intelfb_2d_stop(). 1468 */ 1469void 1470intelfbhw_2d_start(struct intelfb_info *dinfo) 1471{ 1472#if VERBOSE > 0 1473 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n", 1474 dinfo->accel, dinfo->ring_active); 1475#endif 1476 1477 if (!dinfo->accel) 1478 return; 1479 1480 /* Initialise the primary ring buffer. */ 1481 OUTREG(PRI_RING_LENGTH, 0); 1482 OUTREG(PRI_RING_TAIL, 0); 1483 OUTREG(PRI_RING_HEAD, 0); 1484 1485 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK); 1486 OUTREG(PRI_RING_LENGTH, 1487 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) | 1488 RING_NO_REPORT | RING_ENABLE); 1489 refresh_ring(dinfo); 1490 dinfo->ring_active = 1; 1491} 1492 1493/* 2D fillrect (solid fill or invert) */ 1494void 1495intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h, 1496 u32 color, u32 pitch, u32 bpp, u32 rop) 1497{ 1498 u32 br00, br09, br13, br14, br16; 1499 1500#if VERBOSE > 0 1501 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, " 1502 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop); 1503#endif 1504 1505 br00 = COLOR_BLT_CMD; 1506 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8)); 1507 br13 = (rop << ROP_SHIFT) | pitch; 1508 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT); 1509 br16 = color; 1510 1511 switch (bpp) { 1512 case 8: 1513 br13 |= COLOR_DEPTH_8; 1514 break; 1515 case 16: 1516 br13 |= COLOR_DEPTH_16; 1517 break; 1518 case 32: 1519 br13 |= COLOR_DEPTH_32; 1520 br00 |= WRITE_ALPHA | WRITE_RGB; 1521 break; 1522 } 1523 1524 START_RING(6); 1525 OUT_RING(br00); 1526 OUT_RING(br13); 1527 OUT_RING(br14); 1528 OUT_RING(br09); 1529 OUT_RING(br16); 1530 OUT_RING(MI_NOOP); 1531 ADVANCE_RING(); 1532 1533#if VERBOSE > 0 1534 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head, 1535 dinfo->ring_tail, dinfo->ring_space); 1536#endif 1537} 1538 1539void 1540intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury, 1541 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp) 1542{ 1543 u32 br00, br09, br11, br12, br13, br22, br23, br26; 1544 1545#if VERBOSE > 0 1546 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n", 1547 curx, cury, dstx, dsty, w, h, pitch, bpp); 1548#endif 1549 1550 br00 = XY_SRC_COPY_BLT_CMD; 1551 br09 = dinfo->fb_start; 1552 br11 = (pitch << PITCH_SHIFT); 1553 br12 = dinfo->fb_start; 1554 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT); 1555 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT); 1556 br23 = ((dstx + w) << WIDTH_SHIFT) | 1557 ((dsty + h) << HEIGHT_SHIFT); 1558 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT); 1559 1560 switch (bpp) { 1561 case 8: 1562 br13 |= COLOR_DEPTH_8; 1563 break; 1564 case 16: 1565 br13 |= COLOR_DEPTH_16; 1566 break; 1567 case 32: 1568 br13 |= COLOR_DEPTH_32; 1569 br00 |= WRITE_ALPHA | WRITE_RGB; 1570 break; 1571 } 1572 1573 START_RING(8); 1574 OUT_RING(br00); 1575 OUT_RING(br13); 1576 OUT_RING(br22); 1577 OUT_RING(br23); 1578 OUT_RING(br09); 1579 OUT_RING(br26); 1580 OUT_RING(br11); 1581 OUT_RING(br12); 1582 ADVANCE_RING(); 1583} 1584 1585int 1586intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w, 1587 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp) 1588{ 1589 int nbytes, ndwords, pad, tmp; 1590 u32 br00, br09, br13, br18, br19, br22, br23; 1591 int dat, ix, iy, iw; 1592 int i, j; 1593 1594#if VERBOSE > 0 1595 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h); 1596#endif 1597 1598 /* size in bytes of a padded scanline */ 1599 nbytes = ROUND_UP_TO(w, 16) / 8; 1600 1601 /* Total bytes of padded scanline data to write out. */ 1602 nbytes = nbytes * h; 1603 1604 /* 1605 * Check if the glyph data exceeds the immediate mode limit. 1606 * It would take a large font (1K pixels) to hit this limit. 1607 */ 1608 if (nbytes > MAX_MONO_IMM_SIZE) 1609 return 0; 1610 1611 /* Src data is packaged a dword (32-bit) at a time. */ 1612 ndwords = ROUND_UP_TO(nbytes, 4) / 4; 1613 1614 /* 1615 * Ring has to be padded to a quad word. But because the command starts 1616 with 7 bytes, pad only if there is an even number of ndwords 1617 */ 1618 pad = !(ndwords % 2); 1619 1620 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords; 1621 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp; 1622 br09 = dinfo->fb_start; 1623 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT); 1624 br18 = bg; 1625 br19 = fg; 1626 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT); 1627 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT); 1628 1629 switch (bpp) { 1630 case 8: 1631 br13 |= COLOR_DEPTH_8; 1632 break; 1633 case 16: 1634 br13 |= COLOR_DEPTH_16; 1635 break; 1636 case 32: 1637 br13 |= COLOR_DEPTH_32; 1638 br00 |= WRITE_ALPHA | WRITE_RGB; 1639 break; 1640 } 1641 1642 START_RING(8 + ndwords); 1643 OUT_RING(br00); 1644 OUT_RING(br13); 1645 OUT_RING(br22); 1646 OUT_RING(br23); 1647 OUT_RING(br09); 1648 OUT_RING(br18); 1649 OUT_RING(br19); 1650 ix = iy = 0; 1651 iw = ROUND_UP_TO(w, 8) / 8; 1652 while (ndwords--) { 1653 dat = 0; 1654 for (j = 0; j < 2; ++j) { 1655 for (i = 0; i < 2; ++i) { 1656 if (ix != iw || i == 0) 1657 dat |= cdat[iy*iw + ix++] << (i+j*2)*8; 1658 } 1659 if (ix == iw && iy != (h-1)) { 1660 ix = 0; 1661 ++iy; 1662 } 1663 } 1664 OUT_RING(dat); 1665 } 1666 if (pad) 1667 OUT_RING(MI_NOOP); 1668 ADVANCE_RING(); 1669 1670 return 1; 1671} 1672 1673/* HW cursor functions. */ 1674void 1675intelfbhw_cursor_init(struct intelfb_info *dinfo) 1676{ 1677 u32 tmp; 1678 1679#if VERBOSE > 0 1680 DBG_MSG("intelfbhw_cursor_init\n"); 1681#endif 1682 1683 if (dinfo->mobile) { 1684 if (!dinfo->cursor.physical) 1685 return; 1686 tmp = INREG(CURSOR_A_CONTROL); 1687 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE | 1688 CURSOR_MEM_TYPE_LOCAL | 1689 (1 << CURSOR_PIPE_SELECT_SHIFT)); 1690 tmp |= CURSOR_MODE_DISABLE; 1691 OUTREG(CURSOR_A_CONTROL, tmp); 1692 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); 1693 } else { 1694 tmp = INREG(CURSOR_CONTROL); 1695 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE | 1696 CURSOR_ENABLE | CURSOR_STRIDE_MASK); 1697 tmp = CURSOR_FORMAT_3C; 1698 OUTREG(CURSOR_CONTROL, tmp); 1699 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12); 1700 tmp = (64 << CURSOR_SIZE_H_SHIFT) | 1701 (64 << CURSOR_SIZE_V_SHIFT); 1702 OUTREG(CURSOR_SIZE, tmp); 1703 } 1704} 1705 1706void 1707intelfbhw_cursor_hide(struct intelfb_info *dinfo) 1708{ 1709 u32 tmp; 1710 1711#if VERBOSE > 0 1712 DBG_MSG("intelfbhw_cursor_hide\n"); 1713#endif 1714 1715 dinfo->cursor_on = 0; 1716 if (dinfo->mobile) { 1717 if (!dinfo->cursor.physical) 1718 return; 1719 tmp = INREG(CURSOR_A_CONTROL); 1720 tmp &= ~CURSOR_MODE_MASK; 1721 tmp |= CURSOR_MODE_DISABLE; 1722 OUTREG(CURSOR_A_CONTROL, tmp); 1723 /* Flush changes */ 1724 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); 1725 } else { 1726 tmp = INREG(CURSOR_CONTROL); 1727 tmp &= ~CURSOR_ENABLE; 1728 OUTREG(CURSOR_CONTROL, tmp); 1729 } 1730} 1731 1732void 1733intelfbhw_cursor_show(struct intelfb_info *dinfo) 1734{ 1735 u32 tmp; 1736 1737#if VERBOSE > 0 1738 DBG_MSG("intelfbhw_cursor_show\n"); 1739#endif 1740 1741 dinfo->cursor_on = 1; 1742 1743 if (dinfo->cursor_blanked) 1744 return; 1745 1746 if (dinfo->mobile) { 1747 if (!dinfo->cursor.physical) 1748 return; 1749 tmp = INREG(CURSOR_A_CONTROL); 1750 tmp &= ~CURSOR_MODE_MASK; 1751 tmp |= CURSOR_MODE_64_4C_AX; 1752 OUTREG(CURSOR_A_CONTROL, tmp); 1753 /* Flush changes */ 1754 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); 1755 } else { 1756 tmp = INREG(CURSOR_CONTROL); 1757 tmp |= CURSOR_ENABLE; 1758 OUTREG(CURSOR_CONTROL, tmp); 1759 } 1760} 1761 1762void 1763intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y) 1764{ 1765 u32 tmp; 1766 1767#if VERBOSE > 0 1768 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y); 1769#endif 1770 1771 /* 1772 * Sets the position. The coordinates are assumed to already 1773 * have any offset adjusted. Assume that the cursor is never 1774 * completely off-screen, and that x, y are always >= 0. 1775 */ 1776 1777 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) | 1778 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 1779 OUTREG(CURSOR_A_POSITION, tmp); 1780} 1781 1782void 1783intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg) 1784{ 1785#if VERBOSE > 0 1786 DBG_MSG("intelfbhw_cursor_setcolor\n"); 1787#endif 1788 1789 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK); 1790 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK); 1791 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK); 1792 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK); 1793} 1794 1795void 1796intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height, 1797 u8 *data) 1798{ 1799 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual; 1800 int i, j, w = width / 8; 1801 int mod = width % 8, t_mask, d_mask; 1802 1803#if VERBOSE > 0 1804 DBG_MSG("intelfbhw_cursor_load\n"); 1805#endif 1806 1807 if (!dinfo->cursor.virtual) 1808 return; 1809 1810 t_mask = 0xff >> mod; 1811 d_mask = ~(0xff >> mod); 1812 for (i = height; i--; ) { 1813 for (j = 0; j < w; j++) { 1814 writeb(0x00, addr + j); 1815 writeb(*(data++), addr + j+8); 1816 } 1817 if (mod) { 1818 writeb(t_mask, addr + j); 1819 writeb(*(data++) & d_mask, addr + j+8); 1820 } 1821 addr += 16; 1822 } 1823} 1824 1825void 1826intelfbhw_cursor_reset(struct intelfb_info *dinfo) { 1827 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual; 1828 int i, j; 1829 1830#if VERBOSE > 0 1831 DBG_MSG("intelfbhw_cursor_reset\n"); 1832#endif 1833 1834 if (!dinfo->cursor.virtual) 1835 return; 1836 1837 for (i = 64; i--; ) { 1838 for (j = 0; j < 8; j++) { 1839 writeb(0xff, addr + j+0); 1840 writeb(0x00, addr + j+8); 1841 } 1842 addr += 16; 1843 } 1844} 1845