ti_hdmi.h revision 60634a28bc5467ade316574c4aa728c5bff7947e 
1/*
2 * ti_hdmi.h
3 *
4 * HDMI driver definition for TI OMAP4, DM81xx, DM38xx  Processor.
5 *
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program.  If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef _TI_HDMI_H
22#define _TI_HDMI_H
23
24struct hdmi_ip_data;
25
26enum hdmi_pll_pwr {
27	HDMI_PLLPWRCMD_ALLOFF = 0,
28	HDMI_PLLPWRCMD_PLLONLY = 1,
29	HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
30	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
31};
32
33enum hdmi_core_hdmi_dvi {
34	HDMI_DVI = 0,
35	HDMI_HDMI = 1
36};
37
38enum hdmi_clk_refsel {
39	HDMI_REFSEL_PCLK = 0,
40	HDMI_REFSEL_REF1 = 1,
41	HDMI_REFSEL_REF2 = 2,
42	HDMI_REFSEL_SYSCLK = 3
43};
44
45struct hdmi_video_timings {
46	u16 x_res;
47	u16 y_res;
48	/* Unit: KHz */
49	u32 pixel_clock;
50	u16 hsw;
51	u16 hfp;
52	u16 hbp;
53	u16 vsw;
54	u16 vfp;
55	u16 vbp;
56};
57
58/* HDMI timing structure */
59struct hdmi_timings {
60	struct hdmi_video_timings timings;
61	int vsync_pol;
62	int hsync_pol;
63};
64
65struct hdmi_cm {
66	int	code;
67	int	mode;
68};
69
70struct hdmi_config {
71	struct hdmi_timings timings;
72	u16	interlace;
73	struct hdmi_cm cm;
74};
75
76/* HDMI PLL structure */
77struct hdmi_pll_info {
78	u16 regn;
79	u16 regm;
80	u32 regmf;
81	u16 regm2;
82	u16 regsd;
83	u16 dcofreq;
84	enum hdmi_clk_refsel refsel;
85};
86
87struct ti_hdmi_ip_ops {
88
89	void (*video_configure)(struct hdmi_ip_data *ip_data);
90
91	int (*phy_enable)(struct hdmi_ip_data *ip_data);
92
93	void (*phy_disable)(struct hdmi_ip_data *ip_data);
94
95	int (*read_edid)(struct hdmi_ip_data *ip_data,
96			u8 *pedid, u16 max_length);
97
98	int (*pll_enable)(struct hdmi_ip_data *ip_data);
99
100	void (*pll_disable)(struct hdmi_ip_data *ip_data);
101
102	void (*video_enable)(struct hdmi_ip_data *ip_data, bool start);
103};
104
105struct hdmi_ip_data {
106	void __iomem	*base_wp;	/* HDMI wrapper */
107	unsigned long	core_sys_offset;
108	unsigned long	core_av_offset;
109	unsigned long	pll_offset;
110	unsigned long	phy_offset;
111	const struct ti_hdmi_ip_ops *ops;
112	struct hdmi_config cfg;
113	struct hdmi_pll_info pll_data;
114};
115int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
116void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
117int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
118					u8 *pedid, u16 max_length);
119void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
120int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
121void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
122void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
123#endif
124