fbdev.c revision 599a52d12629394236d785615808845823875868
1/* 2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver 3 * 4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com> 5 * 6 * Copyright 1999-2000 Jeff Garzik 7 * 8 * Contributors: 9 * 10 * Ani Joshi: Lots of debugging and cleanup work, really helped 11 * get the driver going 12 * 13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization 14 * 15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr 16 * 17 * Paul Richards: Bug fixes, updates 18 * 19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven 20 * Includes riva_hw.c from nVidia, see copyright below. 21 * KGI code provided the basis for state storage, init, and mode switching. 22 * 23 * This file is subject to the terms and conditions of the GNU General Public 24 * License. See the file COPYING in the main directory of this archive 25 * for more details. 26 * 27 * Known bugs and issues: 28 * restoring text mode fails 29 * doublescan modes are broken 30 */ 31 32#include <linux/module.h> 33#include <linux/kernel.h> 34#include <linux/errno.h> 35#include <linux/string.h> 36#include <linux/mm.h> 37#include <linux/slab.h> 38#include <linux/delay.h> 39#include <linux/fb.h> 40#include <linux/init.h> 41#include <linux/pci.h> 42#include <linux/backlight.h> 43#include <linux/bitrev.h> 44#ifdef CONFIG_MTRR 45#include <asm/mtrr.h> 46#endif 47#ifdef CONFIG_PPC_OF 48#include <asm/prom.h> 49#include <asm/pci-bridge.h> 50#endif 51#ifdef CONFIG_PMAC_BACKLIGHT 52#include <asm/machdep.h> 53#include <asm/backlight.h> 54#endif 55 56#include "rivafb.h" 57#include "nvreg.h" 58 59#ifndef CONFIG_PCI /* sanity check */ 60#error This driver requires PCI support. 61#endif 62 63/* version number of this driver */ 64#define RIVAFB_VERSION "0.9.5b" 65 66/* ------------------------------------------------------------------------- * 67 * 68 * various helpful macros and constants 69 * 70 * ------------------------------------------------------------------------- */ 71#ifdef CONFIG_FB_RIVA_DEBUG 72#define NVTRACE printk 73#else 74#define NVTRACE if(0) printk 75#endif 76 77#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__) 78#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__) 79 80#ifdef CONFIG_FB_RIVA_DEBUG 81#define assert(expr) \ 82 if(!(expr)) { \ 83 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 84 #expr,__FILE__,__FUNCTION__,__LINE__); \ 85 BUG(); \ 86 } 87#else 88#define assert(expr) 89#endif 90 91#define PFX "rivafb: " 92 93/* macro that allows you to set overflow bits */ 94#define SetBitField(value,from,to) SetBF(to,GetBF(value,from)) 95#define SetBit(n) (1<<(n)) 96#define Set8Bits(value) ((value)&0xff) 97 98/* HW cursor parameters */ 99#define MAX_CURS 32 100 101/* ------------------------------------------------------------------------- * 102 * 103 * prototypes 104 * 105 * ------------------------------------------------------------------------- */ 106 107static int rivafb_blank(int blank, struct fb_info *info); 108 109/* ------------------------------------------------------------------------- * 110 * 111 * card identification 112 * 113 * ------------------------------------------------------------------------- */ 114 115static struct pci_device_id rivafb_pci_tbl[] = { 116 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128, 117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT, 119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2, 121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2, 123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2, 125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2, 127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2, 129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR, 131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR, 133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO, 135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX, 137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2, 139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO, 141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR, 143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS, 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2, 147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA, 149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO, 151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 152 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460, 153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 154 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440, 155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 156 // NF2/IGP version, GeForce 4 MX, NV18 157 { PCI_VENDOR_ID_NVIDIA, 0x01f0, 158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420, 160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO, 162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO, 164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32, 166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL, 168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64, 170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200, 172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL, 174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL, 176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2, 178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3, 180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1, 182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 197 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL, 198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 199 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200, 200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 201 { 0, } /* terminate list */ 202}; 203MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl); 204 205/* ------------------------------------------------------------------------- * 206 * 207 * global variables 208 * 209 * ------------------------------------------------------------------------- */ 210 211/* command line data, set in rivafb_setup() */ 212static int flatpanel __devinitdata = -1; /* Autodetect later */ 213static int forceCRTC __devinitdata = -1; 214static int noaccel __devinitdata = 0; 215#ifdef CONFIG_MTRR 216static int nomtrr __devinitdata = 0; 217#endif 218 219static char *mode_option __devinitdata = NULL; 220static int strictmode = 0; 221 222static struct fb_fix_screeninfo __devinitdata rivafb_fix = { 223 .type = FB_TYPE_PACKED_PIXELS, 224 .xpanstep = 1, 225 .ypanstep = 1, 226}; 227 228static struct fb_var_screeninfo __devinitdata rivafb_default_var = { 229 .xres = 640, 230 .yres = 480, 231 .xres_virtual = 640, 232 .yres_virtual = 480, 233 .bits_per_pixel = 8, 234 .red = {0, 8, 0}, 235 .green = {0, 8, 0}, 236 .blue = {0, 8, 0}, 237 .transp = {0, 0, 0}, 238 .activate = FB_ACTIVATE_NOW, 239 .height = -1, 240 .width = -1, 241 .pixclock = 39721, 242 .left_margin = 40, 243 .right_margin = 24, 244 .upper_margin = 32, 245 .lower_margin = 11, 246 .hsync_len = 96, 247 .vsync_len = 2, 248 .vmode = FB_VMODE_NONINTERLACED 249}; 250 251/* from GGI */ 252static const struct riva_regs reg_template = { 253 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ 254 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 255 0x41, 0x01, 0x0F, 0x00, 0x00}, 256 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */ 257 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */ 259 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */ 261 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */ 263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 264 0x00, /* 0x40 */ 265 }, 266 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */ 267 0xFF}, 268 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */ 269 0xEB /* MISC */ 270}; 271 272/* 273 * Backlight control 274 */ 275#ifdef CONFIG_FB_RIVA_BACKLIGHT 276/* We do not have any information about which values are allowed, thus 277 * we used safe values. 278 */ 279#define MIN_LEVEL 0x158 280#define MAX_LEVEL 0x534 281#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX) 282 283static struct backlight_properties riva_bl_data; 284 285static int riva_bl_get_level_brightness(struct riva_par *par, 286 int level) 287{ 288 struct fb_info *info = pci_get_drvdata(par->pdev); 289 int nlevel; 290 291 /* Get and convert the value */ 292 /* No locking on bl_curve since accessing a single value */ 293 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP; 294 295 if (nlevel < 0) 296 nlevel = 0; 297 else if (nlevel < MIN_LEVEL) 298 nlevel = MIN_LEVEL; 299 else if (nlevel > MAX_LEVEL) 300 nlevel = MAX_LEVEL; 301 302 return nlevel; 303} 304 305static int riva_bl_update_status(struct backlight_device *bd) 306{ 307 struct riva_par *par = class_get_devdata(&bd->class_dev); 308 U032 tmp_pcrt, tmp_pmc; 309 int level; 310 311 if (bd->props.power != FB_BLANK_UNBLANK || 312 bd->props.fb_blank != FB_BLANK_UNBLANK) 313 level = 0; 314 else 315 level = bd->props.brightness; 316 317 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF; 318 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC; 319 if(level > 0) { 320 tmp_pcrt |= 0x1; 321 tmp_pmc |= (1 << 31); /* backlight bit */ 322 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */ 323 } 324 par->riva.PCRTC0[0x081C/4] = tmp_pcrt; 325 par->riva.PMC[0x10F0/4] = tmp_pmc; 326 327 return 0; 328} 329 330static int riva_bl_get_brightness(struct backlight_device *bd) 331{ 332 return bd->props.brightness; 333} 334 335static struct backlight_ops riva_bl_ops = { 336 .get_brightness = riva_bl_get_brightness, 337 .update_status = riva_bl_update_status, 338}; 339 340static void riva_bl_init(struct riva_par *par) 341{ 342 struct fb_info *info = pci_get_drvdata(par->pdev); 343 struct backlight_device *bd; 344 char name[12]; 345 346 if (!par->FlatPanel) 347 return; 348 349#ifdef CONFIG_PMAC_BACKLIGHT 350 if (!machine_is(powermac) || 351 !pmac_has_backlight_type("mnca")) 352 return; 353#endif 354 355 snprintf(name, sizeof(name), "rivabl%d", info->node); 356 357 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops); 358 if (IS_ERR(bd)) { 359 info->bl_dev = NULL; 360 printk(KERN_WARNING "riva: Backlight registration failed\n"); 361 goto error; 362 } 363 364 info->bl_dev = bd; 365 fb_bl_default_curve(info, 0, 366 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL, 367 FB_BACKLIGHT_MAX); 368 369 bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 370 bd->props.brightness = riva_bl_data.max_brightness; 371 bd->props.power = FB_BLANK_UNBLANK; 372 backlight_update_status(bd); 373 374 printk("riva: Backlight initialized (%s)\n", name); 375 376 return; 377 378error: 379 return; 380} 381 382static void riva_bl_exit(struct fb_info *info) 383{ 384 struct backlight_device *bd = info->bl_dev; 385 386 backlight_device_unregister(bd); 387 printk("riva: Backlight unloaded\n"); 388} 389#else 390static inline void riva_bl_init(struct riva_par *par) {} 391static inline void riva_bl_exit(struct fb_info *info) {} 392#endif /* CONFIG_FB_RIVA_BACKLIGHT */ 393 394/* ------------------------------------------------------------------------- * 395 * 396 * MMIO access macros 397 * 398 * ------------------------------------------------------------------------- */ 399 400static inline void CRTCout(struct riva_par *par, unsigned char index, 401 unsigned char val) 402{ 403 VGA_WR08(par->riva.PCIO, 0x3d4, index); 404 VGA_WR08(par->riva.PCIO, 0x3d5, val); 405} 406 407static inline unsigned char CRTCin(struct riva_par *par, 408 unsigned char index) 409{ 410 VGA_WR08(par->riva.PCIO, 0x3d4, index); 411 return (VGA_RD08(par->riva.PCIO, 0x3d5)); 412} 413 414static inline void GRAout(struct riva_par *par, unsigned char index, 415 unsigned char val) 416{ 417 VGA_WR08(par->riva.PVIO, 0x3ce, index); 418 VGA_WR08(par->riva.PVIO, 0x3cf, val); 419} 420 421static inline unsigned char GRAin(struct riva_par *par, 422 unsigned char index) 423{ 424 VGA_WR08(par->riva.PVIO, 0x3ce, index); 425 return (VGA_RD08(par->riva.PVIO, 0x3cf)); 426} 427 428static inline void SEQout(struct riva_par *par, unsigned char index, 429 unsigned char val) 430{ 431 VGA_WR08(par->riva.PVIO, 0x3c4, index); 432 VGA_WR08(par->riva.PVIO, 0x3c5, val); 433} 434 435static inline unsigned char SEQin(struct riva_par *par, 436 unsigned char index) 437{ 438 VGA_WR08(par->riva.PVIO, 0x3c4, index); 439 return (VGA_RD08(par->riva.PVIO, 0x3c5)); 440} 441 442static inline void ATTRout(struct riva_par *par, unsigned char index, 443 unsigned char val) 444{ 445 VGA_WR08(par->riva.PCIO, 0x3c0, index); 446 VGA_WR08(par->riva.PCIO, 0x3c0, val); 447} 448 449static inline unsigned char ATTRin(struct riva_par *par, 450 unsigned char index) 451{ 452 VGA_WR08(par->riva.PCIO, 0x3c0, index); 453 return (VGA_RD08(par->riva.PCIO, 0x3c1)); 454} 455 456static inline void MISCout(struct riva_par *par, unsigned char val) 457{ 458 VGA_WR08(par->riva.PVIO, 0x3c2, val); 459} 460 461static inline unsigned char MISCin(struct riva_par *par) 462{ 463 return (VGA_RD08(par->riva.PVIO, 0x3cc)); 464} 465 466static inline void reverse_order(u32 *l) 467{ 468 u8 *a = (u8 *)l; 469 a[0] = bitrev8(a[0]); 470 a[1] = bitrev8(a[1]); 471 a[2] = bitrev8(a[2]); 472 a[3] = bitrev8(a[3]); 473} 474 475/* ------------------------------------------------------------------------- * 476 * 477 * cursor stuff 478 * 479 * ------------------------------------------------------------------------- */ 480 481/** 482 * rivafb_load_cursor_image - load cursor image to hardware 483 * @data: address to monochrome bitmap (1 = foreground color, 0 = background) 484 * @par: pointer to private data 485 * @w: width of cursor image in pixels 486 * @h: height of cursor image in scanlines 487 * @bg: background color (ARGB1555) - alpha bit determines opacity 488 * @fg: foreground color (ARGB1555) 489 * 490 * DESCRIPTiON: 491 * Loads cursor image based on a monochrome source and mask bitmap. The 492 * image bits determines the color of the pixel, 0 for background, 1 for 493 * foreground. Only the affected region (as determined by @w and @h 494 * parameters) will be updated. 495 * 496 * CALLED FROM: 497 * rivafb_cursor() 498 */ 499static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8, 500 u16 bg, u16 fg, u32 w, u32 h) 501{ 502 int i, j, k = 0; 503 u32 b, tmp; 504 u32 *data = (u32 *)data8; 505 bg = le16_to_cpu(bg); 506 fg = le16_to_cpu(fg); 507 508 w = (w + 1) & ~1; 509 510 for (i = 0; i < h; i++) { 511 b = *data++; 512 reverse_order(&b); 513 514 for (j = 0; j < w/2; j++) { 515 tmp = 0; 516#if defined (__BIG_ENDIAN) 517 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 518 b <<= 1; 519 tmp |= (b & (1 << 31)) ? fg : bg; 520 b <<= 1; 521#else 522 tmp = (b & 1) ? fg : bg; 523 b >>= 1; 524 tmp |= (b & 1) ? fg << 16 : bg << 16; 525 b >>= 1; 526#endif 527 writel(tmp, &par->riva.CURSOR[k++]); 528 } 529 k += (MAX_CURS - w)/2; 530 } 531} 532 533/* ------------------------------------------------------------------------- * 534 * 535 * general utility functions 536 * 537 * ------------------------------------------------------------------------- */ 538 539/** 540 * riva_wclut - set CLUT entry 541 * @chip: pointer to RIVA_HW_INST object 542 * @regnum: register number 543 * @red: red component 544 * @green: green component 545 * @blue: blue component 546 * 547 * DESCRIPTION: 548 * Sets color register @regnum. 549 * 550 * CALLED FROM: 551 * rivafb_setcolreg() 552 */ 553static void riva_wclut(RIVA_HW_INST *chip, 554 unsigned char regnum, unsigned char red, 555 unsigned char green, unsigned char blue) 556{ 557 VGA_WR08(chip->PDIO, 0x3c8, regnum); 558 VGA_WR08(chip->PDIO, 0x3c9, red); 559 VGA_WR08(chip->PDIO, 0x3c9, green); 560 VGA_WR08(chip->PDIO, 0x3c9, blue); 561} 562 563/** 564 * riva_rclut - read fromCLUT register 565 * @chip: pointer to RIVA_HW_INST object 566 * @regnum: register number 567 * @red: red component 568 * @green: green component 569 * @blue: blue component 570 * 571 * DESCRIPTION: 572 * Reads red, green, and blue from color register @regnum. 573 * 574 * CALLED FROM: 575 * rivafb_setcolreg() 576 */ 577static void riva_rclut(RIVA_HW_INST *chip, 578 unsigned char regnum, unsigned char *red, 579 unsigned char *green, unsigned char *blue) 580{ 581 582 VGA_WR08(chip->PDIO, 0x3c7, regnum); 583 *red = VGA_RD08(chip->PDIO, 0x3c9); 584 *green = VGA_RD08(chip->PDIO, 0x3c9); 585 *blue = VGA_RD08(chip->PDIO, 0x3c9); 586} 587 588/** 589 * riva_save_state - saves current chip state 590 * @par: pointer to riva_par object containing info for current riva board 591 * @regs: pointer to riva_regs object 592 * 593 * DESCRIPTION: 594 * Saves current chip state to @regs. 595 * 596 * CALLED FROM: 597 * rivafb_probe() 598 */ 599/* from GGI */ 600static void riva_save_state(struct riva_par *par, struct riva_regs *regs) 601{ 602 int i; 603 604 NVTRACE_ENTER(); 605 par->riva.LockUnlock(&par->riva, 0); 606 607 par->riva.UnloadStateExt(&par->riva, ®s->ext); 608 609 regs->misc_output = MISCin(par); 610 611 for (i = 0; i < NUM_CRT_REGS; i++) 612 regs->crtc[i] = CRTCin(par, i); 613 614 for (i = 0; i < NUM_ATC_REGS; i++) 615 regs->attr[i] = ATTRin(par, i); 616 617 for (i = 0; i < NUM_GRC_REGS; i++) 618 regs->gra[i] = GRAin(par, i); 619 620 for (i = 0; i < NUM_SEQ_REGS; i++) 621 regs->seq[i] = SEQin(par, i); 622 NVTRACE_LEAVE(); 623} 624 625/** 626 * riva_load_state - loads current chip state 627 * @par: pointer to riva_par object containing info for current riva board 628 * @regs: pointer to riva_regs object 629 * 630 * DESCRIPTION: 631 * Loads chip state from @regs. 632 * 633 * CALLED FROM: 634 * riva_load_video_mode() 635 * rivafb_probe() 636 * rivafb_remove() 637 */ 638/* from GGI */ 639static void riva_load_state(struct riva_par *par, struct riva_regs *regs) 640{ 641 RIVA_HW_STATE *state = ®s->ext; 642 int i; 643 644 NVTRACE_ENTER(); 645 CRTCout(par, 0x11, 0x00); 646 647 par->riva.LockUnlock(&par->riva, 0); 648 649 par->riva.LoadStateExt(&par->riva, state); 650 651 MISCout(par, regs->misc_output); 652 653 for (i = 0; i < NUM_CRT_REGS; i++) { 654 switch (i) { 655 case 0x19: 656 case 0x20 ... 0x40: 657 break; 658 default: 659 CRTCout(par, i, regs->crtc[i]); 660 } 661 } 662 663 for (i = 0; i < NUM_ATC_REGS; i++) 664 ATTRout(par, i, regs->attr[i]); 665 666 for (i = 0; i < NUM_GRC_REGS; i++) 667 GRAout(par, i, regs->gra[i]); 668 669 for (i = 0; i < NUM_SEQ_REGS; i++) 670 SEQout(par, i, regs->seq[i]); 671 NVTRACE_LEAVE(); 672} 673 674/** 675 * riva_load_video_mode - calculate timings 676 * @info: pointer to fb_info object containing info for current riva board 677 * 678 * DESCRIPTION: 679 * Calculate some timings and then send em off to riva_load_state(). 680 * 681 * CALLED FROM: 682 * rivafb_set_par() 683 */ 684static int riva_load_video_mode(struct fb_info *info) 685{ 686 int bpp, width, hDisplaySize, hDisplay, hStart, 687 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock; 688 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd; 689 int rc; 690 struct riva_par *par = info->par; 691 struct riva_regs newmode; 692 693 NVTRACE_ENTER(); 694 /* time to calculate */ 695 rivafb_blank(FB_BLANK_NORMAL, info); 696 697 bpp = info->var.bits_per_pixel; 698 if (bpp == 16 && info->var.green.length == 5) 699 bpp = 15; 700 width = info->var.xres_virtual; 701 hDisplaySize = info->var.xres; 702 hDisplay = (hDisplaySize / 8) - 1; 703 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1; 704 hEnd = (hDisplaySize + info->var.right_margin + 705 info->var.hsync_len) / 8 - 1; 706 hTotal = (hDisplaySize + info->var.right_margin + 707 info->var.hsync_len + info->var.left_margin) / 8 - 5; 708 hBlankStart = hDisplay; 709 hBlankEnd = hTotal + 4; 710 711 height = info->var.yres_virtual; 712 vDisplay = info->var.yres - 1; 713 vStart = info->var.yres + info->var.lower_margin - 1; 714 vEnd = info->var.yres + info->var.lower_margin + 715 info->var.vsync_len - 1; 716 vTotal = info->var.yres + info->var.lower_margin + 717 info->var.vsync_len + info->var.upper_margin + 2; 718 vBlankStart = vDisplay; 719 vBlankEnd = vTotal + 1; 720 dotClock = 1000000000 / info->var.pixclock; 721 722 memcpy(&newmode, ®_template, sizeof(struct riva_regs)); 723 724 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 725 vTotal |= 1; 726 727 if (par->FlatPanel) { 728 vStart = vTotal - 3; 729 vEnd = vTotal - 2; 730 vBlankStart = vStart; 731 hStart = hTotal - 3; 732 hEnd = hTotal - 2; 733 hBlankEnd = hTotal + 4; 734 } 735 736 newmode.crtc[0x0] = Set8Bits (hTotal); 737 newmode.crtc[0x1] = Set8Bits (hDisplay); 738 newmode.crtc[0x2] = Set8Bits (hBlankStart); 739 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7); 740 newmode.crtc[0x4] = Set8Bits (hStart); 741 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7) 742 | SetBitField (hEnd, 4: 0, 4:0); 743 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0); 744 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0) 745 | SetBitField (vDisplay, 8: 8, 1:1) 746 | SetBitField (vStart, 8: 8, 2:2) 747 | SetBitField (vBlankStart, 8: 8, 3:3) 748 | SetBit (4) 749 | SetBitField (vTotal, 9: 9, 5:5) 750 | SetBitField (vDisplay, 9: 9, 6:6) 751 | SetBitField (vStart, 9: 9, 7:7); 752 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5) 753 | SetBit (6); 754 newmode.crtc[0x10] = Set8Bits (vStart); 755 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0) 756 | SetBit (5); 757 newmode.crtc[0x12] = Set8Bits (vDisplay); 758 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8); 759 newmode.crtc[0x15] = Set8Bits (vBlankStart); 760 newmode.crtc[0x16] = Set8Bits (vBlankEnd); 761 762 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4) 763 | SetBitField(vBlankStart,10:10,3:3) 764 | SetBitField(vStart,10:10,2:2) 765 | SetBitField(vDisplay,10:10,1:1) 766 | SetBitField(vTotal,10:10,0:0); 767 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0) 768 | SetBitField(hDisplay,8:8,1:1) 769 | SetBitField(hBlankStart,8:8,2:2) 770 | SetBitField(hStart,8:8,3:3); 771 newmode.ext.extra = SetBitField(vTotal,11:11,0:0) 772 | SetBitField(vDisplay,11:11,2:2) 773 | SetBitField(vStart,11:11,4:4) 774 | SetBitField(vBlankStart,11:11,6:6); 775 776 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { 777 int tmp = (hTotal >> 1) & ~1; 778 newmode.ext.interlace = Set8Bits(tmp); 779 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4); 780 } else 781 newmode.ext.interlace = 0xff; /* interlace off */ 782 783 if (par->riva.Architecture >= NV_ARCH_10) 784 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart); 785 786 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 787 newmode.misc_output &= ~0x40; 788 else 789 newmode.misc_output |= 0x40; 790 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 791 newmode.misc_output &= ~0x80; 792 else 793 newmode.misc_output |= 0x80; 794 795 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width, 796 hDisplaySize, height, dotClock); 797 if (rc) 798 goto out; 799 800 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) & 801 0xfff000ff; 802 if (par->FlatPanel == 1) { 803 newmode.ext.pixel |= (1 << 7); 804 newmode.ext.scale |= (1 << 8); 805 } 806 if (par->SecondCRTC) { 807 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) & 808 ~0x00001000; 809 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) | 810 0x00001000; 811 newmode.ext.crtcOwner = 3; 812 newmode.ext.pllsel |= 0x20000800; 813 newmode.ext.vpll2 = newmode.ext.vpll; 814 } else if (par->riva.twoHeads) { 815 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) | 816 0x00001000; 817 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) & 818 ~0x00001000; 819 newmode.ext.crtcOwner = 0; 820 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520); 821 } 822 if (par->FlatPanel == 1) { 823 newmode.ext.pixel |= (1 << 7); 824 newmode.ext.scale |= (1 << 8); 825 } 826 newmode.ext.cursorConfig = 0x02000100; 827 par->current_state = newmode; 828 riva_load_state(par, &par->current_state); 829 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */ 830 831out: 832 rivafb_blank(FB_BLANK_UNBLANK, info); 833 NVTRACE_LEAVE(); 834 835 return rc; 836} 837 838static void riva_update_var(struct fb_var_screeninfo *var, 839 const struct fb_videomode *modedb) 840{ 841 NVTRACE_ENTER(); 842 var->xres = var->xres_virtual = modedb->xres; 843 var->yres = modedb->yres; 844 if (var->yres_virtual < var->yres) 845 var->yres_virtual = var->yres; 846 var->xoffset = var->yoffset = 0; 847 var->pixclock = modedb->pixclock; 848 var->left_margin = modedb->left_margin; 849 var->right_margin = modedb->right_margin; 850 var->upper_margin = modedb->upper_margin; 851 var->lower_margin = modedb->lower_margin; 852 var->hsync_len = modedb->hsync_len; 853 var->vsync_len = modedb->vsync_len; 854 var->sync = modedb->sync; 855 var->vmode = modedb->vmode; 856 NVTRACE_LEAVE(); 857} 858 859/** 860 * rivafb_do_maximize - 861 * @info: pointer to fb_info object containing info for current riva board 862 * @var: 863 * @nom: 864 * @den: 865 * 866 * DESCRIPTION: 867 * . 868 * 869 * RETURNS: 870 * -EINVAL on failure, 0 on success 871 * 872 * 873 * CALLED FROM: 874 * rivafb_check_var() 875 */ 876static int rivafb_do_maximize(struct fb_info *info, 877 struct fb_var_screeninfo *var, 878 int nom, int den) 879{ 880 static struct { 881 int xres, yres; 882 } modes[] = { 883 {1600, 1280}, 884 {1280, 1024}, 885 {1024, 768}, 886 {800, 600}, 887 {640, 480}, 888 {-1, -1} 889 }; 890 int i; 891 892 NVTRACE_ENTER(); 893 /* use highest possible virtual resolution */ 894 if (var->xres_virtual == -1 && var->yres_virtual == -1) { 895 printk(KERN_WARNING PFX 896 "using maximum available virtual resolution\n"); 897 for (i = 0; modes[i].xres != -1; i++) { 898 if (modes[i].xres * nom / den * modes[i].yres < 899 info->fix.smem_len) 900 break; 901 } 902 if (modes[i].xres == -1) { 903 printk(KERN_ERR PFX 904 "could not find a virtual resolution that fits into video memory!!\n"); 905 NVTRACE("EXIT - EINVAL error\n"); 906 return -EINVAL; 907 } 908 var->xres_virtual = modes[i].xres; 909 var->yres_virtual = modes[i].yres; 910 911 printk(KERN_INFO PFX 912 "virtual resolution set to maximum of %dx%d\n", 913 var->xres_virtual, var->yres_virtual); 914 } else if (var->xres_virtual == -1) { 915 var->xres_virtual = (info->fix.smem_len * den / 916 (nom * var->yres_virtual)) & ~15; 917 printk(KERN_WARNING PFX 918 "setting virtual X resolution to %d\n", var->xres_virtual); 919 } else if (var->yres_virtual == -1) { 920 var->xres_virtual = (var->xres_virtual + 15) & ~15; 921 var->yres_virtual = info->fix.smem_len * den / 922 (nom * var->xres_virtual); 923 printk(KERN_WARNING PFX 924 "setting virtual Y resolution to %d\n", var->yres_virtual); 925 } else { 926 var->xres_virtual = (var->xres_virtual + 15) & ~15; 927 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) { 928 printk(KERN_ERR PFX 929 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n", 930 var->xres, var->yres, var->bits_per_pixel); 931 NVTRACE("EXIT - EINVAL error\n"); 932 return -EINVAL; 933 } 934 } 935 936 if (var->xres_virtual * nom / den >= 8192) { 937 printk(KERN_WARNING PFX 938 "virtual X resolution (%d) is too high, lowering to %d\n", 939 var->xres_virtual, 8192 * den / nom - 16); 940 var->xres_virtual = 8192 * den / nom - 16; 941 } 942 943 if (var->xres_virtual < var->xres) { 944 printk(KERN_ERR PFX 945 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual); 946 return -EINVAL; 947 } 948 949 if (var->yres_virtual < var->yres) { 950 printk(KERN_ERR PFX 951 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual); 952 return -EINVAL; 953 } 954 if (var->yres_virtual > 0x7fff/nom) 955 var->yres_virtual = 0x7fff/nom; 956 if (var->xres_virtual > 0x7fff/nom) 957 var->xres_virtual = 0x7fff/nom; 958 NVTRACE_LEAVE(); 959 return 0; 960} 961 962static void 963riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1) 964{ 965 RIVA_FIFO_FREE(par->riva, Patt, 4); 966 NV_WR32(&par->riva.Patt->Color0, 0, clr0); 967 NV_WR32(&par->riva.Patt->Color1, 0, clr1); 968 NV_WR32(par->riva.Patt->Monochrome, 0, pat0); 969 NV_WR32(par->riva.Patt->Monochrome, 4, pat1); 970} 971 972/* acceleration routines */ 973static inline void wait_for_idle(struct riva_par *par) 974{ 975 while (par->riva.Busy(&par->riva)); 976} 977 978/* 979 * Set ROP. Translate X rop into ROP3. Internal routine. 980 */ 981static void 982riva_set_rop_solid(struct riva_par *par, int rop) 983{ 984 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 985 RIVA_FIFO_FREE(par->riva, Rop, 1); 986 NV_WR32(&par->riva.Rop->Rop3, 0, rop); 987 988} 989 990static void riva_setup_accel(struct fb_info *info) 991{ 992 struct riva_par *par = info->par; 993 994 RIVA_FIFO_FREE(par->riva, Clip, 2); 995 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0); 996 NV_WR32(&par->riva.Clip->WidthHeight, 0, 997 (info->var.xres_virtual & 0xffff) | 998 (info->var.yres_virtual << 16)); 999 riva_set_rop_solid(par, 0xcc); 1000 wait_for_idle(par); 1001} 1002 1003/** 1004 * riva_get_cmap_len - query current color map length 1005 * @var: standard kernel fb changeable data 1006 * 1007 * DESCRIPTION: 1008 * Get current color map length. 1009 * 1010 * RETURNS: 1011 * Length of color map 1012 * 1013 * CALLED FROM: 1014 * rivafb_setcolreg() 1015 */ 1016static int riva_get_cmap_len(const struct fb_var_screeninfo *var) 1017{ 1018 int rc = 256; /* reasonable default */ 1019 1020 switch (var->green.length) { 1021 case 8: 1022 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */ 1023 break; 1024 case 5: 1025 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */ 1026 break; 1027 case 6: 1028 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */ 1029 break; 1030 default: 1031 /* should not occur */ 1032 break; 1033 } 1034 return rc; 1035} 1036 1037/* ------------------------------------------------------------------------- * 1038 * 1039 * framebuffer operations 1040 * 1041 * ------------------------------------------------------------------------- */ 1042 1043static int rivafb_open(struct fb_info *info, int user) 1044{ 1045 struct riva_par *par = info->par; 1046 1047 NVTRACE_ENTER(); 1048 mutex_lock(&par->open_lock); 1049 if (!par->ref_count) { 1050#ifdef CONFIG_X86 1051 memset(&par->state, 0, sizeof(struct vgastate)); 1052 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS; 1053 /* save the DAC for Riva128 */ 1054 if (par->riva.Architecture == NV_ARCH_03) 1055 par->state.flags |= VGA_SAVE_CMAP; 1056 save_vga(&par->state); 1057#endif 1058 /* vgaHWunlock() + riva unlock (0x7F) */ 1059 CRTCout(par, 0x11, 0xFF); 1060 par->riva.LockUnlock(&par->riva, 0); 1061 1062 riva_save_state(par, &par->initial_state); 1063 } 1064 par->ref_count++; 1065 mutex_unlock(&par->open_lock); 1066 NVTRACE_LEAVE(); 1067 return 0; 1068} 1069 1070static int rivafb_release(struct fb_info *info, int user) 1071{ 1072 struct riva_par *par = info->par; 1073 1074 NVTRACE_ENTER(); 1075 mutex_lock(&par->open_lock); 1076 if (!par->ref_count) { 1077 mutex_unlock(&par->open_lock); 1078 return -EINVAL; 1079 } 1080 if (par->ref_count == 1) { 1081 par->riva.LockUnlock(&par->riva, 0); 1082 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); 1083 riva_load_state(par, &par->initial_state); 1084#ifdef CONFIG_X86 1085 restore_vga(&par->state); 1086#endif 1087 par->riva.LockUnlock(&par->riva, 1); 1088 } 1089 par->ref_count--; 1090 mutex_unlock(&par->open_lock); 1091 NVTRACE_LEAVE(); 1092 return 0; 1093} 1094 1095static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 1096{ 1097 const struct fb_videomode *mode; 1098 struct riva_par *par = info->par; 1099 int nom, den; /* translating from pixels->bytes */ 1100 int mode_valid = 0; 1101 1102 NVTRACE_ENTER(); 1103 switch (var->bits_per_pixel) { 1104 case 1 ... 8: 1105 var->red.offset = var->green.offset = var->blue.offset = 0; 1106 var->red.length = var->green.length = var->blue.length = 8; 1107 var->bits_per_pixel = 8; 1108 nom = den = 1; 1109 break; 1110 case 9 ... 15: 1111 var->green.length = 5; 1112 /* fall through */ 1113 case 16: 1114 var->bits_per_pixel = 16; 1115 /* The Riva128 supports RGB555 only */ 1116 if (par->riva.Architecture == NV_ARCH_03) 1117 var->green.length = 5; 1118 if (var->green.length == 5) { 1119 /* 0rrrrrgg gggbbbbb */ 1120 var->red.offset = 10; 1121 var->green.offset = 5; 1122 var->blue.offset = 0; 1123 var->red.length = 5; 1124 var->green.length = 5; 1125 var->blue.length = 5; 1126 } else { 1127 /* rrrrrggg gggbbbbb */ 1128 var->red.offset = 11; 1129 var->green.offset = 5; 1130 var->blue.offset = 0; 1131 var->red.length = 5; 1132 var->green.length = 6; 1133 var->blue.length = 5; 1134 } 1135 nom = 2; 1136 den = 1; 1137 break; 1138 case 17 ... 32: 1139 var->red.length = var->green.length = var->blue.length = 8; 1140 var->bits_per_pixel = 32; 1141 var->red.offset = 16; 1142 var->green.offset = 8; 1143 var->blue.offset = 0; 1144 nom = 4; 1145 den = 1; 1146 break; 1147 default: 1148 printk(KERN_ERR PFX 1149 "mode %dx%dx%d rejected...color depth not supported.\n", 1150 var->xres, var->yres, var->bits_per_pixel); 1151 NVTRACE("EXIT, returning -EINVAL\n"); 1152 return -EINVAL; 1153 } 1154 1155 if (!strictmode) { 1156 if (!info->monspecs.vfmax || !info->monspecs.hfmax || 1157 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 1158 mode_valid = 1; 1159 } 1160 1161 /* calculate modeline if supported by monitor */ 1162 if (!mode_valid && info->monspecs.gtf) { 1163 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 1164 mode_valid = 1; 1165 } 1166 1167 if (!mode_valid) { 1168 mode = fb_find_best_mode(var, &info->modelist); 1169 if (mode) { 1170 riva_update_var(var, mode); 1171 mode_valid = 1; 1172 } 1173 } 1174 1175 if (!mode_valid && info->monspecs.modedb_len) 1176 return -EINVAL; 1177 1178 if (var->xres_virtual < var->xres) 1179 var->xres_virtual = var->xres; 1180 if (var->yres_virtual <= var->yres) 1181 var->yres_virtual = -1; 1182 if (rivafb_do_maximize(info, var, nom, den) < 0) 1183 return -EINVAL; 1184 1185 if (var->xoffset < 0) 1186 var->xoffset = 0; 1187 if (var->yoffset < 0) 1188 var->yoffset = 0; 1189 1190 /* truncate xoffset and yoffset to maximum if too high */ 1191 if (var->xoffset > var->xres_virtual - var->xres) 1192 var->xoffset = var->xres_virtual - var->xres - 1; 1193 1194 if (var->yoffset > var->yres_virtual - var->yres) 1195 var->yoffset = var->yres_virtual - var->yres - 1; 1196 1197 var->red.msb_right = 1198 var->green.msb_right = 1199 var->blue.msb_right = 1200 var->transp.offset = var->transp.length = var->transp.msb_right = 0; 1201 NVTRACE_LEAVE(); 1202 return 0; 1203} 1204 1205static int rivafb_set_par(struct fb_info *info) 1206{ 1207 struct riva_par *par = info->par; 1208 int rc = 0; 1209 1210 NVTRACE_ENTER(); 1211 /* vgaHWunlock() + riva unlock (0x7F) */ 1212 CRTCout(par, 0x11, 0xFF); 1213 par->riva.LockUnlock(&par->riva, 0); 1214 rc = riva_load_video_mode(info); 1215 if (rc) 1216 goto out; 1217 if(!(info->flags & FBINFO_HWACCEL_DISABLED)) 1218 riva_setup_accel(info); 1219 1220 par->cursor_reset = 1; 1221 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3)); 1222 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1223 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1224 1225 if (info->flags & FBINFO_HWACCEL_DISABLED) 1226 info->pixmap.scan_align = 1; 1227 else 1228 info->pixmap.scan_align = 4; 1229 1230out: 1231 NVTRACE_LEAVE(); 1232 return rc; 1233} 1234 1235/** 1236 * rivafb_pan_display 1237 * @var: standard kernel fb changeable data 1238 * @con: TODO 1239 * @info: pointer to fb_info object containing info for current riva board 1240 * 1241 * DESCRIPTION: 1242 * Pan (or wrap, depending on the `vmode' field) the display using the 1243 * `xoffset' and `yoffset' fields of the `var' structure. 1244 * If the values don't fit, return -EINVAL. 1245 * 1246 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag 1247 */ 1248static int rivafb_pan_display(struct fb_var_screeninfo *var, 1249 struct fb_info *info) 1250{ 1251 struct riva_par *par = info->par; 1252 unsigned int base; 1253 1254 NVTRACE_ENTER(); 1255 base = var->yoffset * info->fix.line_length + var->xoffset; 1256 par->riva.SetStartAddress(&par->riva, base); 1257 NVTRACE_LEAVE(); 1258 return 0; 1259} 1260 1261static int rivafb_blank(int blank, struct fb_info *info) 1262{ 1263 struct riva_par *par= info->par; 1264 unsigned char tmp, vesa; 1265 1266 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */ 1267 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */ 1268 1269 NVTRACE_ENTER(); 1270 1271 if (blank) 1272 tmp |= 0x20; 1273 1274 switch (blank) { 1275 case FB_BLANK_UNBLANK: 1276 case FB_BLANK_NORMAL: 1277 break; 1278 case FB_BLANK_VSYNC_SUSPEND: 1279 vesa |= 0x80; 1280 break; 1281 case FB_BLANK_HSYNC_SUSPEND: 1282 vesa |= 0x40; 1283 break; 1284 case FB_BLANK_POWERDOWN: 1285 vesa |= 0xc0; 1286 break; 1287 } 1288 1289 SEQout(par, 0x01, tmp); 1290 CRTCout(par, 0x1a, vesa); 1291 1292 NVTRACE_LEAVE(); 1293 1294 return 0; 1295} 1296 1297/** 1298 * rivafb_setcolreg 1299 * @regno: register index 1300 * @red: red component 1301 * @green: green component 1302 * @blue: blue component 1303 * @transp: transparency 1304 * @info: pointer to fb_info object containing info for current riva board 1305 * 1306 * DESCRIPTION: 1307 * Set a single color register. The values supplied have a 16 bit 1308 * magnitude. 1309 * 1310 * RETURNS: 1311 * Return != 0 for invalid regno. 1312 * 1313 * CALLED FROM: 1314 * fbcmap.c:fb_set_cmap() 1315 */ 1316static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green, 1317 unsigned blue, unsigned transp, 1318 struct fb_info *info) 1319{ 1320 struct riva_par *par = info->par; 1321 RIVA_HW_INST *chip = &par->riva; 1322 int i; 1323 1324 if (regno >= riva_get_cmap_len(&info->var)) 1325 return -EINVAL; 1326 1327 if (info->var.grayscale) { 1328 /* gray = 0.30*R + 0.59*G + 0.11*B */ 1329 red = green = blue = 1330 (red * 77 + green * 151 + blue * 28) >> 8; 1331 } 1332 1333 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 1334 ((u32 *) info->pseudo_palette)[regno] = 1335 (regno << info->var.red.offset) | 1336 (regno << info->var.green.offset) | 1337 (regno << info->var.blue.offset); 1338 /* 1339 * The Riva128 2D engine requires color information in 1340 * TrueColor format even if framebuffer is in DirectColor 1341 */ 1342 if (par->riva.Architecture == NV_ARCH_03) { 1343 switch (info->var.bits_per_pixel) { 1344 case 16: 1345 par->palette[regno] = ((red & 0xf800) >> 1) | 1346 ((green & 0xf800) >> 6) | 1347 ((blue & 0xf800) >> 11); 1348 break; 1349 case 32: 1350 par->palette[regno] = ((red & 0xff00) << 8) | 1351 ((green & 0xff00)) | 1352 ((blue & 0xff00) >> 8); 1353 break; 1354 } 1355 } 1356 } 1357 1358 switch (info->var.bits_per_pixel) { 1359 case 8: 1360 /* "transparent" stuff is completely ignored. */ 1361 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1362 break; 1363 case 16: 1364 if (info->var.green.length == 5) { 1365 for (i = 0; i < 8; i++) { 1366 riva_wclut(chip, regno*8+i, red >> 8, 1367 green >> 8, blue >> 8); 1368 } 1369 } else { 1370 u8 r, g, b; 1371 1372 if (regno < 32) { 1373 for (i = 0; i < 8; i++) { 1374 riva_wclut(chip, regno*8+i, 1375 red >> 8, green >> 8, 1376 blue >> 8); 1377 } 1378 } 1379 riva_rclut(chip, regno*4, &r, &g, &b); 1380 for (i = 0; i < 4; i++) 1381 riva_wclut(chip, regno*4+i, r, 1382 green >> 8, b); 1383 } 1384 break; 1385 case 32: 1386 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8); 1387 break; 1388 default: 1389 /* do nothing */ 1390 break; 1391 } 1392 return 0; 1393} 1394 1395/** 1396 * rivafb_fillrect - hardware accelerated color fill function 1397 * @info: pointer to fb_info structure 1398 * @rect: pointer to fb_fillrect structure 1399 * 1400 * DESCRIPTION: 1401 * This function fills up a region of framebuffer memory with a solid 1402 * color with a choice of two different ROP's, copy or invert. 1403 * 1404 * CALLED FROM: 1405 * framebuffer hook 1406 */ 1407static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 1408{ 1409 struct riva_par *par = info->par; 1410 u_int color, rop = 0; 1411 1412 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1413 cfb_fillrect(info, rect); 1414 return; 1415 } 1416 1417 if (info->var.bits_per_pixel == 8) 1418 color = rect->color; 1419 else { 1420 if (par->riva.Architecture != NV_ARCH_03) 1421 color = ((u32 *)info->pseudo_palette)[rect->color]; 1422 else 1423 color = par->palette[rect->color]; 1424 } 1425 1426 switch (rect->rop) { 1427 case ROP_XOR: 1428 rop = 0x66; 1429 break; 1430 case ROP_COPY: 1431 default: 1432 rop = 0xCC; 1433 break; 1434 } 1435 1436 riva_set_rop_solid(par, rop); 1437 1438 RIVA_FIFO_FREE(par->riva, Bitmap, 1); 1439 NV_WR32(&par->riva.Bitmap->Color1A, 0, color); 1440 1441 RIVA_FIFO_FREE(par->riva, Bitmap, 2); 1442 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0, 1443 (rect->dx << 16) | rect->dy); 1444 mb(); 1445 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0, 1446 (rect->width << 16) | rect->height); 1447 mb(); 1448 riva_set_rop_solid(par, 0xcc); 1449 1450} 1451 1452/** 1453 * rivafb_copyarea - hardware accelerated blit function 1454 * @info: pointer to fb_info structure 1455 * @region: pointer to fb_copyarea structure 1456 * 1457 * DESCRIPTION: 1458 * This copies an area of pixels from one location to another 1459 * 1460 * CALLED FROM: 1461 * framebuffer hook 1462 */ 1463static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region) 1464{ 1465 struct riva_par *par = info->par; 1466 1467 if ((info->flags & FBINFO_HWACCEL_DISABLED)) { 1468 cfb_copyarea(info, region); 1469 return; 1470 } 1471 1472 RIVA_FIFO_FREE(par->riva, Blt, 3); 1473 NV_WR32(&par->riva.Blt->TopLeftSrc, 0, 1474 (region->sy << 16) | region->sx); 1475 NV_WR32(&par->riva.Blt->TopLeftDst, 0, 1476 (region->dy << 16) | region->dx); 1477 mb(); 1478 NV_WR32(&par->riva.Blt->WidthHeight, 0, 1479 (region->height << 16) | region->width); 1480 mb(); 1481} 1482 1483static inline void convert_bgcolor_16(u32 *col) 1484{ 1485 *col = ((*col & 0x0000F800) << 8) 1486 | ((*col & 0x00007E0) << 5) 1487 | ((*col & 0x0000001F) << 3) 1488 | 0xFF000000; 1489 mb(); 1490} 1491 1492/** 1493 * rivafb_imageblit: hardware accelerated color expand function 1494 * @info: pointer to fb_info structure 1495 * @image: pointer to fb_image structure 1496 * 1497 * DESCRIPTION: 1498 * If the source is a monochrome bitmap, the function fills up a a region 1499 * of framebuffer memory with pixels whose color is determined by the bit 1500 * setting of the bitmap, 1 - foreground, 0 - background. 1501 * 1502 * If the source is not a monochrome bitmap, color expansion is not done. 1503 * In this case, it is channeled to a software function. 1504 * 1505 * CALLED FROM: 1506 * framebuffer hook 1507 */ 1508static void rivafb_imageblit(struct fb_info *info, 1509 const struct fb_image *image) 1510{ 1511 struct riva_par *par = info->par; 1512 u32 fgx = 0, bgx = 0, width, tmp; 1513 u8 *cdat = (u8 *) image->data; 1514 volatile u32 __iomem *d; 1515 int i, size; 1516 1517 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) { 1518 cfb_imageblit(info, image); 1519 return; 1520 } 1521 1522 switch (info->var.bits_per_pixel) { 1523 case 8: 1524 fgx = image->fg_color; 1525 bgx = image->bg_color; 1526 break; 1527 case 16: 1528 case 32: 1529 if (par->riva.Architecture != NV_ARCH_03) { 1530 fgx = ((u32 *)info->pseudo_palette)[image->fg_color]; 1531 bgx = ((u32 *)info->pseudo_palette)[image->bg_color]; 1532 } else { 1533 fgx = par->palette[image->fg_color]; 1534 bgx = par->palette[image->bg_color]; 1535 } 1536 if (info->var.green.length == 6) 1537 convert_bgcolor_16(&bgx); 1538 break; 1539 } 1540 1541 RIVA_FIFO_FREE(par->riva, Bitmap, 7); 1542 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0, 1543 (image->dy << 16) | (image->dx & 0xFFFF)); 1544 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0, 1545 (((image->dy + image->height) << 16) | 1546 ((image->dx + image->width) & 0xffff))); 1547 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx); 1548 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx); 1549 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0, 1550 (image->height << 16) | ((image->width + 31) & ~31)); 1551 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0, 1552 (image->height << 16) | ((image->width + 31) & ~31)); 1553 NV_WR32(&par->riva.Bitmap->PointE, 0, 1554 (image->dy << 16) | (image->dx & 0xFFFF)); 1555 1556 d = &par->riva.Bitmap->MonochromeData01E; 1557 1558 width = (image->width + 31)/32; 1559 size = width * image->height; 1560 while (size >= 16) { 1561 RIVA_FIFO_FREE(par->riva, Bitmap, 16); 1562 for (i = 0; i < 16; i++) { 1563 tmp = *((u32 *)cdat); 1564 cdat = (u8 *)((u32 *)cdat + 1); 1565 reverse_order(&tmp); 1566 NV_WR32(d, i*4, tmp); 1567 } 1568 size -= 16; 1569 } 1570 if (size) { 1571 RIVA_FIFO_FREE(par->riva, Bitmap, size); 1572 for (i = 0; i < size; i++) { 1573 tmp = *((u32 *) cdat); 1574 cdat = (u8 *)((u32 *)cdat + 1); 1575 reverse_order(&tmp); 1576 NV_WR32(d, i*4, tmp); 1577 } 1578 } 1579} 1580 1581/** 1582 * rivafb_cursor - hardware cursor function 1583 * @info: pointer to info structure 1584 * @cursor: pointer to fbcursor structure 1585 * 1586 * DESCRIPTION: 1587 * A cursor function that supports displaying a cursor image via hardware. 1588 * Within the kernel, copy and invert rops are supported. If exported 1589 * to user space, only the copy rop will be supported. 1590 * 1591 * CALLED FROM 1592 * framebuffer hook 1593 */ 1594static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 1595{ 1596 struct riva_par *par = info->par; 1597 u8 data[MAX_CURS * MAX_CURS/8]; 1598 int i, set = cursor->set; 1599 u16 fg, bg; 1600 1601 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 1602 return -ENXIO; 1603 1604 par->riva.ShowHideCursor(&par->riva, 0); 1605 1606 if (par->cursor_reset) { 1607 set = FB_CUR_SETALL; 1608 par->cursor_reset = 0; 1609 } 1610 1611 if (set & FB_CUR_SETSIZE) 1612 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2); 1613 1614 if (set & FB_CUR_SETPOS) { 1615 u32 xx, yy, temp; 1616 1617 yy = cursor->image.dy - info->var.yoffset; 1618 xx = cursor->image.dx - info->var.xoffset; 1619 temp = xx & 0xFFFF; 1620 temp |= yy << 16; 1621 1622 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp); 1623 } 1624 1625 1626 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 1627 u32 bg_idx = cursor->image.bg_color; 1628 u32 fg_idx = cursor->image.fg_color; 1629 u32 s_pitch = (cursor->image.width+7) >> 3; 1630 u32 d_pitch = MAX_CURS/8; 1631 u8 *dat = (u8 *) cursor->image.data; 1632 u8 *msk = (u8 *) cursor->mask; 1633 u8 *src; 1634 1635 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); 1636 1637 if (src) { 1638 switch (cursor->rop) { 1639 case ROP_XOR: 1640 for (i = 0; i < s_pitch * cursor->image.height; i++) 1641 src[i] = dat[i] ^ msk[i]; 1642 break; 1643 case ROP_COPY: 1644 default: 1645 for (i = 0; i < s_pitch * cursor->image.height; i++) 1646 src[i] = dat[i] & msk[i]; 1647 break; 1648 } 1649 1650 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 1651 cursor->image.height); 1652 1653 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 1654 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 1655 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1656 1 << 15; 1657 1658 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 1659 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 1660 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1661 1 << 15; 1662 1663 par->riva.LockUnlock(&par->riva, 0); 1664 1665 rivafb_load_cursor_image(par, data, bg, fg, 1666 cursor->image.width, 1667 cursor->image.height); 1668 kfree(src); 1669 } 1670 } 1671 1672 if (cursor->enable) 1673 par->riva.ShowHideCursor(&par->riva, 1); 1674 1675 return 0; 1676} 1677 1678static int rivafb_sync(struct fb_info *info) 1679{ 1680 struct riva_par *par = info->par; 1681 1682 wait_for_idle(par); 1683 return 0; 1684} 1685 1686/* ------------------------------------------------------------------------- * 1687 * 1688 * initialization helper functions 1689 * 1690 * ------------------------------------------------------------------------- */ 1691 1692/* kernel interface */ 1693static struct fb_ops riva_fb_ops = { 1694 .owner = THIS_MODULE, 1695 .fb_open = rivafb_open, 1696 .fb_release = rivafb_release, 1697 .fb_check_var = rivafb_check_var, 1698 .fb_set_par = rivafb_set_par, 1699 .fb_setcolreg = rivafb_setcolreg, 1700 .fb_pan_display = rivafb_pan_display, 1701 .fb_blank = rivafb_blank, 1702 .fb_fillrect = rivafb_fillrect, 1703 .fb_copyarea = rivafb_copyarea, 1704 .fb_imageblit = rivafb_imageblit, 1705 .fb_cursor = rivafb_cursor, 1706 .fb_sync = rivafb_sync, 1707}; 1708 1709static int __devinit riva_set_fbinfo(struct fb_info *info) 1710{ 1711 unsigned int cmap_len; 1712 struct riva_par *par = info->par; 1713 1714 NVTRACE_ENTER(); 1715 info->flags = FBINFO_DEFAULT 1716 | FBINFO_HWACCEL_XPAN 1717 | FBINFO_HWACCEL_YPAN 1718 | FBINFO_HWACCEL_COPYAREA 1719 | FBINFO_HWACCEL_FILLRECT 1720 | FBINFO_HWACCEL_IMAGEBLIT; 1721 1722 /* Accel seems to not work properly on NV30 yet...*/ 1723 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) { 1724 printk(KERN_DEBUG PFX "disabling acceleration\n"); 1725 info->flags |= FBINFO_HWACCEL_DISABLED; 1726 } 1727 1728 info->var = rivafb_default_var; 1729 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1730 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1731 1732 info->pseudo_palette = par->pseudo_palette; 1733 1734 cmap_len = riva_get_cmap_len(&info->var); 1735 fb_alloc_cmap(&info->cmap, cmap_len, 0); 1736 1737 info->pixmap.size = 8 * 1024; 1738 info->pixmap.buf_align = 4; 1739 info->pixmap.access_align = 32; 1740 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1741 info->var.yres_virtual = -1; 1742 NVTRACE_LEAVE(); 1743 return (rivafb_check_var(&info->var, info)); 1744} 1745 1746#ifdef CONFIG_PPC_OF 1747static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd) 1748{ 1749 struct riva_par *par = info->par; 1750 struct device_node *dp; 1751 const unsigned char *pedid = NULL; 1752 const unsigned char *disptype = NULL; 1753 static char *propnames[] = { 1754 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL }; 1755 int i; 1756 1757 NVTRACE_ENTER(); 1758 dp = pci_device_to_OF_node(pd); 1759 for (; dp != NULL; dp = dp->child) { 1760 disptype = get_property(dp, "display-type", NULL); 1761 if (disptype == NULL) 1762 continue; 1763 if (strncmp(disptype, "LCD", 3) != 0) 1764 continue; 1765 for (i = 0; propnames[i] != NULL; ++i) { 1766 pedid = get_property(dp, propnames[i], NULL); 1767 if (pedid != NULL) { 1768 par->EDID = (unsigned char *)pedid; 1769 NVTRACE("LCD found.\n"); 1770 return 1; 1771 } 1772 } 1773 } 1774 NVTRACE_LEAVE(); 1775 return 0; 1776} 1777#endif /* CONFIG_PPC_OF */ 1778 1779#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF) 1780static int __devinit riva_get_EDID_i2c(struct fb_info *info) 1781{ 1782 struct riva_par *par = info->par; 1783 struct fb_var_screeninfo var; 1784 int i; 1785 1786 NVTRACE_ENTER(); 1787 riva_create_i2c_busses(par); 1788 for (i = 0; i < par->bus; i++) { 1789 riva_probe_i2c_connector(par, i+1, &par->EDID); 1790 if (par->EDID && !fb_parse_edid(par->EDID, &var)) { 1791 printk(PFX "Found EDID Block from BUS %i\n", i); 1792 break; 1793 } 1794 } 1795 1796 NVTRACE_LEAVE(); 1797 return (par->EDID) ? 1 : 0; 1798} 1799#endif /* CONFIG_FB_RIVA_I2C */ 1800 1801static void __devinit riva_update_default_var(struct fb_var_screeninfo *var, 1802 struct fb_info *info) 1803{ 1804 struct fb_monspecs *specs = &info->monspecs; 1805 struct fb_videomode modedb; 1806 1807 NVTRACE_ENTER(); 1808 /* respect mode options */ 1809 if (mode_option) { 1810 fb_find_mode(var, info, mode_option, 1811 specs->modedb, specs->modedb_len, 1812 NULL, 8); 1813 } else if (specs->modedb != NULL) { 1814 /* get preferred timing */ 1815 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) { 1816 int i; 1817 1818 for (i = 0; i < specs->modedb_len; i++) { 1819 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) { 1820 modedb = specs->modedb[i]; 1821 break; 1822 } 1823 } 1824 } else { 1825 /* otherwise, get first mode in database */ 1826 modedb = specs->modedb[0]; 1827 } 1828 var->bits_per_pixel = 8; 1829 riva_update_var(var, &modedb); 1830 } 1831 NVTRACE_LEAVE(); 1832} 1833 1834 1835static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev) 1836{ 1837 NVTRACE_ENTER(); 1838#ifdef CONFIG_PPC_OF 1839 if (!riva_get_EDID_OF(info, pdev)) 1840 printk(PFX "could not retrieve EDID from OF\n"); 1841#elif defined(CONFIG_FB_RIVA_I2C) 1842 if (!riva_get_EDID_i2c(info)) 1843 printk(PFX "could not retrieve EDID from DDC/I2C\n"); 1844#endif 1845 NVTRACE_LEAVE(); 1846} 1847 1848 1849static void __devinit riva_get_edidinfo(struct fb_info *info) 1850{ 1851 struct fb_var_screeninfo *var = &rivafb_default_var; 1852 struct riva_par *par = info->par; 1853 1854 fb_edid_to_monspecs(par->EDID, &info->monspecs); 1855 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, 1856 &info->modelist); 1857 riva_update_default_var(var, info); 1858 1859 /* if user specified flatpanel, we respect that */ 1860 if (info->monspecs.input & FB_DISP_DDI) 1861 par->FlatPanel = 1; 1862} 1863 1864/* ------------------------------------------------------------------------- * 1865 * 1866 * PCI bus 1867 * 1868 * ------------------------------------------------------------------------- */ 1869 1870static u32 __devinit riva_get_arch(struct pci_dev *pd) 1871{ 1872 u32 arch = 0; 1873 1874 switch (pd->device & 0x0ff0) { 1875 case 0x0100: /* GeForce 256 */ 1876 case 0x0110: /* GeForce2 MX */ 1877 case 0x0150: /* GeForce2 */ 1878 case 0x0170: /* GeForce4 MX */ 1879 case 0x0180: /* GeForce4 MX (8x AGP) */ 1880 case 0x01A0: /* nForce */ 1881 case 0x01F0: /* nForce2 */ 1882 arch = NV_ARCH_10; 1883 break; 1884 case 0x0200: /* GeForce3 */ 1885 case 0x0250: /* GeForce4 Ti */ 1886 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1887 arch = NV_ARCH_20; 1888 break; 1889 case 0x0300: /* GeForceFX 5800 */ 1890 case 0x0310: /* GeForceFX 5600 */ 1891 case 0x0320: /* GeForceFX 5200 */ 1892 case 0x0330: /* GeForceFX 5900 */ 1893 case 0x0340: /* GeForceFX 5700 */ 1894 arch = NV_ARCH_30; 1895 break; 1896 case 0x0020: /* TNT, TNT2 */ 1897 arch = NV_ARCH_04; 1898 break; 1899 case 0x0010: /* Riva128 */ 1900 arch = NV_ARCH_03; 1901 break; 1902 default: /* unknown architecture */ 1903 break; 1904 } 1905 return arch; 1906} 1907 1908static int __devinit rivafb_probe(struct pci_dev *pd, 1909 const struct pci_device_id *ent) 1910{ 1911 struct riva_par *default_par; 1912 struct fb_info *info; 1913 int ret; 1914 1915 NVTRACE_ENTER(); 1916 assert(pd != NULL); 1917 1918 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev); 1919 if (!info) { 1920 printk (KERN_ERR PFX "could not allocate memory\n"); 1921 ret = -ENOMEM; 1922 goto err_ret; 1923 } 1924 default_par = info->par; 1925 default_par->pdev = pd; 1926 1927 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1928 if (info->pixmap.addr == NULL) { 1929 ret = -ENOMEM; 1930 goto err_framebuffer_release; 1931 } 1932 1933 ret = pci_enable_device(pd); 1934 if (ret < 0) { 1935 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1936 goto err_free_pixmap; 1937 } 1938 1939 ret = pci_request_regions(pd, "rivafb"); 1940 if (ret < 0) { 1941 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1942 goto err_disable_device; 1943 } 1944 1945 mutex_init(&default_par->open_lock); 1946 default_par->riva.Architecture = riva_get_arch(pd); 1947 1948 default_par->Chipset = (pd->vendor << 16) | pd->device; 1949 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset); 1950 1951 if(default_par->riva.Architecture == 0) { 1952 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1953 ret=-ENODEV; 1954 goto err_release_region; 1955 } 1956 if(default_par->riva.Architecture == NV_ARCH_10 || 1957 default_par->riva.Architecture == NV_ARCH_20 || 1958 default_par->riva.Architecture == NV_ARCH_30) { 1959 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1960 } else { 1961 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture); 1962 } 1963 1964 default_par->FlatPanel = flatpanel; 1965 if (flatpanel == 1) 1966 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1967 default_par->forceCRTC = forceCRTC; 1968 1969 rivafb_fix.mmio_len = pci_resource_len(pd, 0); 1970 rivafb_fix.smem_len = pci_resource_len(pd, 1); 1971 1972 { 1973 /* enable IO and mem if not already done */ 1974 unsigned short cmd; 1975 1976 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1977 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1978 pci_write_config_word(pd, PCI_COMMAND, cmd); 1979 } 1980 1981 rivafb_fix.mmio_start = pci_resource_start(pd, 0); 1982 rivafb_fix.smem_start = pci_resource_start(pd, 1); 1983 1984 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start, 1985 rivafb_fix.mmio_len); 1986 if (!default_par->ctrl_base) { 1987 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1988 ret = -EIO; 1989 goto err_release_region; 1990 } 1991 1992 switch (default_par->riva.Architecture) { 1993 case NV_ARCH_03: 1994 /* Riva128's PRAMIN is in the "framebuffer" space 1995 * Since these cards were never made with more than 8 megabytes 1996 * we can safely allocate this separately. 1997 */ 1998 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000); 1999 if (!default_par->riva.PRAMIN) { 2000 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n"); 2001 ret = -EIO; 2002 goto err_iounmap_ctrl_base; 2003 } 2004 break; 2005 case NV_ARCH_04: 2006 case NV_ARCH_10: 2007 case NV_ARCH_20: 2008 case NV_ARCH_30: 2009 default_par->riva.PCRTC0 = 2010 (u32 __iomem *)(default_par->ctrl_base + 0x00600000); 2011 default_par->riva.PRAMIN = 2012 (u32 __iomem *)(default_par->ctrl_base + 0x00710000); 2013 break; 2014 } 2015 riva_common_setup(default_par); 2016 2017 if (default_par->riva.Architecture == NV_ARCH_03) { 2018 default_par->riva.PCRTC = default_par->riva.PCRTC0 2019 = default_par->riva.PGRAPH; 2020 } 2021 2022 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024; 2023 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000; 2024 info->screen_base = ioremap(rivafb_fix.smem_start, 2025 rivafb_fix.smem_len); 2026 if (!info->screen_base) { 2027 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 2028 ret = -EIO; 2029 goto err_iounmap_pramin; 2030 } 2031 2032#ifdef CONFIG_MTRR 2033 if (!nomtrr) { 2034 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start, 2035 rivafb_fix.smem_len, 2036 MTRR_TYPE_WRCOMB, 1); 2037 if (default_par->mtrr.vram < 0) { 2038 printk(KERN_ERR PFX "unable to setup MTRR\n"); 2039 } else { 2040 default_par->mtrr.vram_valid = 1; 2041 /* let there be speed */ 2042 printk(KERN_INFO PFX "RIVA MTRR set to ON\n"); 2043 } 2044 } 2045#endif /* CONFIG_MTRR */ 2046 2047 info->fbops = &riva_fb_ops; 2048 info->fix = rivafb_fix; 2049 riva_get_EDID(info, pd); 2050 riva_get_edidinfo(info); 2051 2052 ret=riva_set_fbinfo(info); 2053 if (ret < 0) { 2054 printk(KERN_ERR PFX "error setting initial video mode\n"); 2055 goto err_iounmap_screen_base; 2056 } 2057 2058 fb_destroy_modedb(info->monspecs.modedb); 2059 info->monspecs.modedb = NULL; 2060 2061 pci_set_drvdata(pd, info); 2062 riva_bl_init(info->par); 2063 ret = register_framebuffer(info); 2064 if (ret < 0) { 2065 printk(KERN_ERR PFX 2066 "error registering riva framebuffer\n"); 2067 goto err_iounmap_screen_base; 2068 } 2069 2070 printk(KERN_INFO PFX 2071 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n", 2072 info->fix.id, 2073 RIVAFB_VERSION, 2074 info->fix.smem_len / (1024 * 1024), 2075 info->fix.smem_start); 2076 2077 NVTRACE_LEAVE(); 2078 return 0; 2079 2080err_iounmap_screen_base: 2081#ifdef CONFIG_FB_RIVA_I2C 2082 riva_delete_i2c_busses(info->par); 2083#endif 2084 iounmap(info->screen_base); 2085err_iounmap_pramin: 2086 if (default_par->riva.Architecture == NV_ARCH_03) 2087 iounmap(default_par->riva.PRAMIN); 2088err_iounmap_ctrl_base: 2089 iounmap(default_par->ctrl_base); 2090err_release_region: 2091 pci_release_regions(pd); 2092err_disable_device: 2093err_free_pixmap: 2094 kfree(info->pixmap.addr); 2095err_framebuffer_release: 2096 framebuffer_release(info); 2097err_ret: 2098 return ret; 2099} 2100 2101static void __exit rivafb_remove(struct pci_dev *pd) 2102{ 2103 struct fb_info *info = pci_get_drvdata(pd); 2104 struct riva_par *par = info->par; 2105 2106 NVTRACE_ENTER(); 2107 2108#ifdef CONFIG_FB_RIVA_I2C 2109 riva_delete_i2c_busses(par); 2110 kfree(par->EDID); 2111#endif 2112 2113 unregister_framebuffer(info); 2114 2115 riva_bl_exit(info); 2116 2117#ifdef CONFIG_MTRR 2118 if (par->mtrr.vram_valid) 2119 mtrr_del(par->mtrr.vram, info->fix.smem_start, 2120 info->fix.smem_len); 2121#endif /* CONFIG_MTRR */ 2122 2123 iounmap(par->ctrl_base); 2124 iounmap(info->screen_base); 2125 if (par->riva.Architecture == NV_ARCH_03) 2126 iounmap(par->riva.PRAMIN); 2127 pci_release_regions(pd); 2128 kfree(info->pixmap.addr); 2129 framebuffer_release(info); 2130 pci_set_drvdata(pd, NULL); 2131 NVTRACE_LEAVE(); 2132} 2133 2134/* ------------------------------------------------------------------------- * 2135 * 2136 * initialization 2137 * 2138 * ------------------------------------------------------------------------- */ 2139 2140#ifndef MODULE 2141static int __init rivafb_setup(char *options) 2142{ 2143 char *this_opt; 2144 2145 NVTRACE_ENTER(); 2146 if (!options || !*options) 2147 return 0; 2148 2149 while ((this_opt = strsep(&options, ",")) != NULL) { 2150 if (!strncmp(this_opt, "forceCRTC", 9)) { 2151 char *p; 2152 2153 p = this_opt + 9; 2154 if (!*p || !*(++p)) continue; 2155 forceCRTC = *p - '0'; 2156 if (forceCRTC < 0 || forceCRTC > 1) 2157 forceCRTC = -1; 2158 } else if (!strncmp(this_opt, "flatpanel", 9)) { 2159 flatpanel = 1; 2160#ifdef CONFIG_MTRR 2161 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2162 nomtrr = 1; 2163#endif 2164 } else if (!strncmp(this_opt, "strictmode", 10)) { 2165 strictmode = 1; 2166 } else if (!strncmp(this_opt, "noaccel", 7)) { 2167 noaccel = 1; 2168 } else 2169 mode_option = this_opt; 2170 } 2171 NVTRACE_LEAVE(); 2172 return 0; 2173} 2174#endif /* !MODULE */ 2175 2176static struct pci_driver rivafb_driver = { 2177 .name = "rivafb", 2178 .id_table = rivafb_pci_tbl, 2179 .probe = rivafb_probe, 2180 .remove = __exit_p(rivafb_remove), 2181}; 2182 2183 2184 2185/* ------------------------------------------------------------------------- * 2186 * 2187 * modularization 2188 * 2189 * ------------------------------------------------------------------------- */ 2190 2191static int __devinit rivafb_init(void) 2192{ 2193#ifndef MODULE 2194 char *option = NULL; 2195 2196 if (fb_get_options("rivafb", &option)) 2197 return -ENODEV; 2198 rivafb_setup(option); 2199#endif 2200 return pci_register_driver(&rivafb_driver); 2201} 2202 2203 2204module_init(rivafb_init); 2205 2206#ifdef MODULE 2207static void __exit rivafb_exit(void) 2208{ 2209 pci_unregister_driver(&rivafb_driver); 2210} 2211 2212module_exit(rivafb_exit); 2213#endif /* MODULE */ 2214 2215module_param(noaccel, bool, 0); 2216MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2217module_param(flatpanel, int, 0); 2218MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)"); 2219module_param(forceCRTC, int, 0); 2220MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)"); 2221#ifdef CONFIG_MTRR 2222module_param(nomtrr, bool, 0); 2223MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)"); 2224#endif 2225module_param(strictmode, bool, 0); 2226MODULE_PARM_DESC(strictmode, "Only use video modes from EDID"); 2227 2228MODULE_AUTHOR("Ani Joshi, maintainer"); 2229MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series"); 2230MODULE_LICENSE("GPL"); 2231