1773c3e75d1fc7ea5058bfeab5d82bac5b85f8cd8Sriramakrishnan#ifndef __CAN_PLATFORM_TI_HECC_H__ 2773c3e75d1fc7ea5058bfeab5d82bac5b85f8cd8Sriramakrishnan#define __CAN_PLATFORM_TI_HECC_H__ 3773c3e75d1fc7ea5058bfeab5d82bac5b85f8cd8Sriramakrishnan 43758bf25db8caeec667e4e56e030da0ec3060529Anant Gole/* 53758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * TI HECC (High End CAN Controller) driver platform header 63758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * 73758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ 83758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * 93758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * This program is free software; you can redistribute it and/or 103758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * modify it under the terms of the GNU General Public License as 113758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * published by the Free Software Foundation version 2. 123758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * 133758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * This program is distributed as is WITHOUT ANY WARRANTY of any 143758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * kind, whether express or implied; without even the implied warranty 153758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 163758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * GNU General Public License for more details. 173758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * 183758bf25db8caeec667e4e56e030da0ec3060529Anant Gole */ 193758bf25db8caeec667e4e56e030da0ec3060529Anant Gole 203758bf25db8caeec667e4e56e030da0ec3060529Anant Gole/** 213758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * struct hecc_platform_data - HECC Platform Data 223758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * 233758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * @scc_hecc_offset: mostly 0 - should really never change 243758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * @scc_ram_offset: SCC RAM offset 253758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * @hecc_ram_offset: HECC RAM offset 263758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * @mbx_offset: Mailbox RAM offset 273758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * @int_line: Interrupt line to use - 0 or 1 283758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * @version: version for future use 29773c3e75d1fc7ea5058bfeab5d82bac5b85f8cd8Sriramakrishnan * @transceiver_switch: platform specific callback fn for transceiver control 303758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * 313758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * Platform data structure to get all platform specific settings. 323758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * this structure also accounts the fact that the IP may have different 333758bf25db8caeec667e4e56e030da0ec3060529Anant Gole * RAM and mailbox offsets for different SOC's 343758bf25db8caeec667e4e56e030da0ec3060529Anant Gole */ 353758bf25db8caeec667e4e56e030da0ec3060529Anant Golestruct ti_hecc_platform_data { 363758bf25db8caeec667e4e56e030da0ec3060529Anant Gole u32 scc_hecc_offset; 373758bf25db8caeec667e4e56e030da0ec3060529Anant Gole u32 scc_ram_offset; 383758bf25db8caeec667e4e56e030da0ec3060529Anant Gole u32 hecc_ram_offset; 393758bf25db8caeec667e4e56e030da0ec3060529Anant Gole u32 mbx_offset; 403758bf25db8caeec667e4e56e030da0ec3060529Anant Gole u32 int_line; 413758bf25db8caeec667e4e56e030da0ec3060529Anant Gole u32 version; 42773c3e75d1fc7ea5058bfeab5d82bac5b85f8cd8Sriramakrishnan void (*transceiver_switch) (int); 433758bf25db8caeec667e4e56e030da0ec3060529Anant Gole}; 44773c3e75d1fc7ea5058bfeab5d82bac5b85f8cd8Sriramakrishnan#endif 45