twl.h revision 1fbe99529d9490fd29982af07731650f112ffdfa
1/* 2 * twl4030.h - header for TWL4030 PM and audio CODEC device 3 * 4 * Copyright (C) 2005-2006 Texas Instruments, Inc. 5 * 6 * Based on tlv320aic23.c: 7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 25#ifndef __TWL_H_ 26#define __TWL_H_ 27 28#include <linux/types.h> 29#include <linux/input/matrix_keypad.h> 30 31/* 32 * Using the twl4030 core we address registers using a pair 33 * { module id, relative register offset } 34 * which that core then maps to the relevant 35 * { i2c slave, absolute register address } 36 * 37 * The module IDs are meaningful only to the twl4030 core code, 38 * which uses them as array indices to look up the first register 39 * address each module uses within a given i2c slave. 40 */ 41 42/* Slave 0 (i2c address 0x48) */ 43#define TWL4030_MODULE_USB 0x00 44 45/* Slave 1 (i2c address 0x49) */ 46#define TWL4030_MODULE_AUDIO_VOICE 0x01 47#define TWL4030_MODULE_GPIO 0x02 48#define TWL4030_MODULE_INTBR 0x03 49#define TWL4030_MODULE_PIH 0x04 50#define TWL4030_MODULE_TEST 0x05 51 52/* Slave 2 (i2c address 0x4a) */ 53#define TWL4030_MODULE_KEYPAD 0x06 54#define TWL4030_MODULE_MADC 0x07 55#define TWL4030_MODULE_INTERRUPTS 0x08 56#define TWL4030_MODULE_LED 0x09 57#define TWL4030_MODULE_MAIN_CHARGE 0x0A 58#define TWL4030_MODULE_PRECHARGE 0x0B 59#define TWL4030_MODULE_PWM0 0x0C 60#define TWL4030_MODULE_PWM1 0x0D 61#define TWL4030_MODULE_PWMA 0x0E 62#define TWL4030_MODULE_PWMB 0x0F 63 64#define TWL5031_MODULE_ACCESSORY 0x10 65#define TWL5031_MODULE_INTERRUPTS 0x11 66 67/* Slave 3 (i2c address 0x4b) */ 68#define TWL4030_MODULE_BACKUP 0x12 69#define TWL4030_MODULE_INT 0x13 70#define TWL4030_MODULE_PM_MASTER 0x14 71#define TWL4030_MODULE_PM_RECEIVER 0x15 72#define TWL4030_MODULE_RTC 0x16 73#define TWL4030_MODULE_SECURED_REG 0x17 74 75#define TWL_MODULE_USB TWL4030_MODULE_USB 76#define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE 77#define TWL_MODULE_PIH TWL4030_MODULE_PIH 78#define TWL_MODULE_MADC TWL4030_MODULE_MADC 79#define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE 80#define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER 81#define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER 82#define TWL_MODULE_RTC TWL4030_MODULE_RTC 83#define TWL_MODULE_PWM TWL4030_MODULE_PWM0 84 85#define TWL6030_MODULE_ID0 0x0D 86#define TWL6030_MODULE_ID1 0x0E 87#define TWL6030_MODULE_ID2 0x0F 88 89#define GPIO_INTR_OFFSET 0 90#define KEYPAD_INTR_OFFSET 1 91#define BCI_INTR_OFFSET 2 92#define MADC_INTR_OFFSET 3 93#define USB_INTR_OFFSET 4 94#define CHARGERFAULT_INTR_OFFSET 5 95#define BCI_PRES_INTR_OFFSET 9 96#define USB_PRES_INTR_OFFSET 10 97#define RTC_INTR_OFFSET 11 98 99/* 100 * Offset from TWL6030_IRQ_BASE / pdata->irq_base 101 */ 102#define PWR_INTR_OFFSET 0 103#define HOTDIE_INTR_OFFSET 12 104#define SMPSLDO_INTR_OFFSET 13 105#define BATDETECT_INTR_OFFSET 14 106#define SIMDETECT_INTR_OFFSET 15 107#define MMCDETECT_INTR_OFFSET 16 108#define GASGAUGE_INTR_OFFSET 17 109#define USBOTG_INTR_OFFSET 4 110#define CHARGER_INTR_OFFSET 2 111#define RSV_INTR_OFFSET 0 112 113/* INT register offsets */ 114#define REG_INT_STS_A 0x00 115#define REG_INT_STS_B 0x01 116#define REG_INT_STS_C 0x02 117 118#define REG_INT_MSK_LINE_A 0x03 119#define REG_INT_MSK_LINE_B 0x04 120#define REG_INT_MSK_LINE_C 0x05 121 122#define REG_INT_MSK_STS_A 0x06 123#define REG_INT_MSK_STS_B 0x07 124#define REG_INT_MSK_STS_C 0x08 125 126/* MASK INT REG GROUP A */ 127#define TWL6030_PWR_INT_MASK 0x07 128#define TWL6030_RTC_INT_MASK 0x18 129#define TWL6030_HOTDIE_INT_MASK 0x20 130#define TWL6030_SMPSLDOA_INT_MASK 0xC0 131 132/* MASK INT REG GROUP B */ 133#define TWL6030_SMPSLDOB_INT_MASK 0x01 134#define TWL6030_BATDETECT_INT_MASK 0x02 135#define TWL6030_SIMDETECT_INT_MASK 0x04 136#define TWL6030_MMCDETECT_INT_MASK 0x08 137#define TWL6030_GPADC_INT_MASK 0x60 138#define TWL6030_GASGAUGE_INT_MASK 0x80 139 140/* MASK INT REG GROUP C */ 141#define TWL6030_USBOTG_INT_MASK 0x0F 142#define TWL6030_CHARGER_CTRL_INT_MASK 0x10 143#define TWL6030_CHARGER_FAULT_INT_MASK 0x60 144 145#define TWL6030_MMCCTRL 0xEE 146#define VMMC_AUTO_OFF (0x1 << 3) 147#define SW_FC (0x1 << 2) 148#define STS_MMC 0x1 149 150#define TWL6030_CFG_INPUT_PUPD3 0xF2 151#define MMC_PU (0x1 << 3) 152#define MMC_PD (0x1 << 2) 153 154#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF) 155#define TWL_SIL_REV(rev) ((rev) >> 24) 156#define TWL_SIL_5030 0x09002F 157#define TWL5030_REV_1_0 0x00 158#define TWL5030_REV_1_1 0x10 159#define TWL5030_REV_1_2 0x30 160 161#define TWL4030_CLASS_ID 0x4030 162#define TWL6030_CLASS_ID 0x6030 163unsigned int twl_rev(void); 164#define GET_TWL_REV (twl_rev()) 165#define TWL_CLASS_IS(class, id) \ 166static inline int twl_class_is_ ##class(void) \ 167{ \ 168 return ((id) == (GET_TWL_REV)) ? 1 : 0; \ 169} 170 171TWL_CLASS_IS(4030, TWL4030_CLASS_ID) 172TWL_CLASS_IS(6030, TWL6030_CLASS_ID) 173 174#define TWL6025_SUBCLASS BIT(4) /* TWL6025 has changed registers */ 175 176/* 177 * Read and write single 8-bit registers 178 */ 179int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg); 180int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg); 181 182/* 183 * Read and write several 8-bit registers at once. 184 * 185 * IMPORTANT: For twl_i2c_write(), allocate num_bytes + 1 186 * for the value, and populate your data starting at offset 1. 187 */ 188int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 189int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 190 191int twl_get_type(void); 192int twl_get_version(void); 193 194int twl6030_interrupt_unmask(u8 bit_mask, u8 offset); 195int twl6030_interrupt_mask(u8 bit_mask, u8 offset); 196 197/* Card detect Configuration for MMC1 Controller on OMAP4 */ 198#ifdef CONFIG_TWL4030_CORE 199int twl6030_mmc_card_detect_config(void); 200#else 201static inline int twl6030_mmc_card_detect_config(void) 202{ 203 pr_debug("twl6030_mmc_card_detect_config not supported\n"); 204 return 0; 205} 206#endif 207 208/* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */ 209#ifdef CONFIG_TWL4030_CORE 210int twl6030_mmc_card_detect(struct device *dev, int slot); 211#else 212static inline int twl6030_mmc_card_detect(struct device *dev, int slot) 213{ 214 pr_debug("Call back twl6030_mmc_card_detect not supported\n"); 215 return -EIO; 216} 217#endif 218/*----------------------------------------------------------------------*/ 219 220/* 221 * NOTE: at up to 1024 registers, this is a big chip. 222 * 223 * Avoid putting register declarations in this file, instead of into 224 * a driver-private file, unless some of the registers in a block 225 * need to be shared with other drivers. One example is blocks that 226 * have Secondary IRQ Handler (SIH) registers. 227 */ 228 229#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0) 230#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1) 231#define TWL4030_SIH_CTRL_COR_MASK BIT(2) 232 233/*----------------------------------------------------------------------*/ 234 235/* 236 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO) 237 */ 238 239#define REG_GPIODATAIN1 0x0 240#define REG_GPIODATAIN2 0x1 241#define REG_GPIODATAIN3 0x2 242#define REG_GPIODATADIR1 0x3 243#define REG_GPIODATADIR2 0x4 244#define REG_GPIODATADIR3 0x5 245#define REG_GPIODATAOUT1 0x6 246#define REG_GPIODATAOUT2 0x7 247#define REG_GPIODATAOUT3 0x8 248#define REG_CLEARGPIODATAOUT1 0x9 249#define REG_CLEARGPIODATAOUT2 0xA 250#define REG_CLEARGPIODATAOUT3 0xB 251#define REG_SETGPIODATAOUT1 0xC 252#define REG_SETGPIODATAOUT2 0xD 253#define REG_SETGPIODATAOUT3 0xE 254#define REG_GPIO_DEBEN1 0xF 255#define REG_GPIO_DEBEN2 0x10 256#define REG_GPIO_DEBEN3 0x11 257#define REG_GPIO_CTRL 0x12 258#define REG_GPIOPUPDCTR1 0x13 259#define REG_GPIOPUPDCTR2 0x14 260#define REG_GPIOPUPDCTR3 0x15 261#define REG_GPIOPUPDCTR4 0x16 262#define REG_GPIOPUPDCTR5 0x17 263#define REG_GPIO_ISR1A 0x19 264#define REG_GPIO_ISR2A 0x1A 265#define REG_GPIO_ISR3A 0x1B 266#define REG_GPIO_IMR1A 0x1C 267#define REG_GPIO_IMR2A 0x1D 268#define REG_GPIO_IMR3A 0x1E 269#define REG_GPIO_ISR1B 0x1F 270#define REG_GPIO_ISR2B 0x20 271#define REG_GPIO_ISR3B 0x21 272#define REG_GPIO_IMR1B 0x22 273#define REG_GPIO_IMR2B 0x23 274#define REG_GPIO_IMR3B 0x24 275#define REG_GPIO_EDR1 0x28 276#define REG_GPIO_EDR2 0x29 277#define REG_GPIO_EDR3 0x2A 278#define REG_GPIO_EDR4 0x2B 279#define REG_GPIO_EDR5 0x2C 280#define REG_GPIO_SIH_CTRL 0x2D 281 282/* Up to 18 signals are available as GPIOs, when their 283 * pins are not assigned to another use (such as ULPI/USB). 284 */ 285#define TWL4030_GPIO_MAX 18 286 287/*----------------------------------------------------------------------*/ 288 289/*Interface Bit Register (INTBR) offsets 290 *(Use TWL_4030_MODULE_INTBR) 291 */ 292 293#define REG_IDCODE_7_0 0x00 294#define REG_IDCODE_15_8 0x01 295#define REG_IDCODE_16_23 0x02 296#define REG_IDCODE_31_24 0x03 297#define REG_GPPUPDCTR1 0x0F 298#define REG_UNLOCK_TEST_REG 0x12 299 300/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */ 301 302#define I2C_SCL_CTRL_PU BIT(0) 303#define I2C_SDA_CTRL_PU BIT(2) 304#define SR_I2C_SCL_CTRL_PU BIT(4) 305#define SR_I2C_SDA_CTRL_PU BIT(6) 306 307#define TWL_EEPROM_R_UNLOCK 0x49 308 309/*----------------------------------------------------------------------*/ 310 311/* 312 * Keypad register offsets (use TWL4030_MODULE_KEYPAD) 313 * ... SIH/interrupt only 314 */ 315 316#define TWL4030_KEYPAD_KEYP_ISR1 0x11 317#define TWL4030_KEYPAD_KEYP_IMR1 0x12 318#define TWL4030_KEYPAD_KEYP_ISR2 0x13 319#define TWL4030_KEYPAD_KEYP_IMR2 0x14 320#define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */ 321#define TWL4030_KEYPAD_KEYP_EDR 0x16 322#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17 323 324/*----------------------------------------------------------------------*/ 325 326/* 327 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC) 328 * ... SIH/interrupt only 329 */ 330 331#define TWL4030_MADC_ISR1 0x61 332#define TWL4030_MADC_IMR1 0x62 333#define TWL4030_MADC_ISR2 0x63 334#define TWL4030_MADC_IMR2 0x64 335#define TWL4030_MADC_SIR 0x65 /* test register */ 336#define TWL4030_MADC_EDR 0x66 337#define TWL4030_MADC_SIH_CTRL 0x67 338 339/*----------------------------------------------------------------------*/ 340 341/* 342 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS) 343 */ 344 345#define TWL4030_INTERRUPTS_BCIISR1A 0x0 346#define TWL4030_INTERRUPTS_BCIISR2A 0x1 347#define TWL4030_INTERRUPTS_BCIIMR1A 0x2 348#define TWL4030_INTERRUPTS_BCIIMR2A 0x3 349#define TWL4030_INTERRUPTS_BCIISR1B 0x4 350#define TWL4030_INTERRUPTS_BCIISR2B 0x5 351#define TWL4030_INTERRUPTS_BCIIMR1B 0x6 352#define TWL4030_INTERRUPTS_BCIIMR2B 0x7 353#define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */ 354#define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */ 355#define TWL4030_INTERRUPTS_BCIEDR1 0xa 356#define TWL4030_INTERRUPTS_BCIEDR2 0xb 357#define TWL4030_INTERRUPTS_BCIEDR3 0xc 358#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd 359 360/*----------------------------------------------------------------------*/ 361 362/* 363 * Power Interrupt block register offsets (use TWL4030_MODULE_INT) 364 */ 365 366#define TWL4030_INT_PWR_ISR1 0x0 367#define TWL4030_INT_PWR_IMR1 0x1 368#define TWL4030_INT_PWR_ISR2 0x2 369#define TWL4030_INT_PWR_IMR2 0x3 370#define TWL4030_INT_PWR_SIR 0x4 /* test register */ 371#define TWL4030_INT_PWR_EDR1 0x5 372#define TWL4030_INT_PWR_EDR2 0x6 373#define TWL4030_INT_PWR_SIH_CTRL 0x7 374 375/*----------------------------------------------------------------------*/ 376 377/* 378 * Accessory Interrupts 379 */ 380#define TWL5031_ACIIMR_LSB 0x05 381#define TWL5031_ACIIMR_MSB 0x06 382#define TWL5031_ACIIDR_LSB 0x07 383#define TWL5031_ACIIDR_MSB 0x08 384#define TWL5031_ACCISR1 0x0F 385#define TWL5031_ACCIMR1 0x10 386#define TWL5031_ACCISR2 0x11 387#define TWL5031_ACCIMR2 0x12 388#define TWL5031_ACCSIR 0x13 389#define TWL5031_ACCEDR1 0x14 390#define TWL5031_ACCSIHCTRL 0x15 391 392/*----------------------------------------------------------------------*/ 393 394/* 395 * Battery Charger Controller 396 */ 397 398#define TWL5031_INTERRUPTS_BCIISR1 0x0 399#define TWL5031_INTERRUPTS_BCIIMR1 0x1 400#define TWL5031_INTERRUPTS_BCIISR2 0x2 401#define TWL5031_INTERRUPTS_BCIIMR2 0x3 402#define TWL5031_INTERRUPTS_BCISIR 0x4 403#define TWL5031_INTERRUPTS_BCIEDR1 0x5 404#define TWL5031_INTERRUPTS_BCIEDR2 0x6 405#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7 406 407/*----------------------------------------------------------------------*/ 408 409/* 410 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER) 411 */ 412 413#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00 414#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01 415#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02 416#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03 417#define TWL4030_PM_MASTER_STS_BOOT 0x04 418#define TWL4030_PM_MASTER_CFG_BOOT 0x05 419#define TWL4030_PM_MASTER_SHUNDAN 0x06 420#define TWL4030_PM_MASTER_BOOT_BCI 0x07 421#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08 422#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09 423#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b 424#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c 425#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d 426#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e 427#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f 428#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10 429#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11 430#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12 431#define TWL4030_PM_MASTER_STS_P123_STATE 0x13 432#define TWL4030_PM_MASTER_PB_CFG 0x14 433#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15 434#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16 435#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c 436#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d 437#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e 438#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f 439#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20 440#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21 441#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22 442#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23 443#define TWL4030_PM_MASTER_MEMORY_DATA 0x24 444 445#define TWL4030_PM_MASTER_KEY_CFG1 0xc0 446#define TWL4030_PM_MASTER_KEY_CFG2 0x0c 447 448#define TWL4030_PM_MASTER_KEY_TST1 0xe0 449#define TWL4030_PM_MASTER_KEY_TST2 0x0e 450 451#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6 452 453/*----------------------------------------------------------------------*/ 454 455/* Power bus message definitions */ 456 457/* The TWL4030/5030 splits its power-management resources (the various 458 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and 459 * P3. These groups can then be configured to transition between sleep, wait-on 460 * and active states by sending messages to the power bus. See Section 5.4.2 461 * Power Resources of TWL4030 TRM 462 */ 463 464/* Processor groups */ 465#define DEV_GRP_NULL 0x0 466#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ 467#define DEV_GRP_P2 0x2 /* P2: all Modem devices */ 468#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ 469 470/* Resource groups */ 471#define RES_GRP_RES 0x0 /* Reserved */ 472#define RES_GRP_PP 0x1 /* Power providers */ 473#define RES_GRP_RC 0x2 /* Reset and control */ 474#define RES_GRP_PP_RC 0x3 475#define RES_GRP_PR 0x4 /* Power references */ 476#define RES_GRP_PP_PR 0x5 477#define RES_GRP_RC_PR 0x6 478#define RES_GRP_ALL 0x7 /* All resource groups */ 479 480#define RES_TYPE2_R0 0x0 481 482#define RES_TYPE_ALL 0x7 483 484/* Resource states */ 485#define RES_STATE_WRST 0xF 486#define RES_STATE_ACTIVE 0xE 487#define RES_STATE_SLEEP 0x8 488#define RES_STATE_OFF 0x0 489 490/* Power resources */ 491 492/* Power providers */ 493#define RES_VAUX1 1 494#define RES_VAUX2 2 495#define RES_VAUX3 3 496#define RES_VAUX4 4 497#define RES_VMMC1 5 498#define RES_VMMC2 6 499#define RES_VPLL1 7 500#define RES_VPLL2 8 501#define RES_VSIM 9 502#define RES_VDAC 10 503#define RES_VINTANA1 11 504#define RES_VINTANA2 12 505#define RES_VINTDIG 13 506#define RES_VIO 14 507#define RES_VDD1 15 508#define RES_VDD2 16 509#define RES_VUSB_1V5 17 510#define RES_VUSB_1V8 18 511#define RES_VUSB_3V1 19 512#define RES_VUSBCP 20 513#define RES_REGEN 21 514/* Reset and control */ 515#define RES_NRES_PWRON 22 516#define RES_CLKEN 23 517#define RES_SYSEN 24 518#define RES_HFCLKOUT 25 519#define RES_32KCLKOUT 26 520#define RES_RESET 27 521/* Power Reference */ 522#define RES_MAIN_REF 28 523 524#define TOTAL_RESOURCES 28 525/* 526 * Power Bus Message Format ... these can be sent individually by Linux, 527 * but are usually part of downloaded scripts that are run when various 528 * power events are triggered. 529 * 530 * Broadcast Message (16 Bits): 531 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] 532 * RES_STATE[3:0] 533 * 534 * Singular Message (16 Bits): 535 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] 536 */ 537 538#define MSG_BROADCAST(devgrp, grp, type, type2, state) \ 539 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ 540 | (type) << 4 | (state)) 541 542#define MSG_SINGULAR(devgrp, id, state) \ 543 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) 544 545#define MSG_BROADCAST_ALL(devgrp, state) \ 546 ((devgrp) << 5 | (state)) 547 548#define MSG_BROADCAST_REF MSG_BROADCAST_ALL 549#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL 550#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL 551/*----------------------------------------------------------------------*/ 552 553struct twl4030_clock_init_data { 554 bool ck32k_lowpwr_enable; 555}; 556 557struct twl4030_bci_platform_data { 558 int *battery_tmp_tbl; 559 unsigned int tblsize; 560}; 561 562/* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */ 563struct twl4030_gpio_platform_data { 564 int gpio_base; 565 unsigned irq_base, irq_end; 566 567 /* package the two LED signals as output-only GPIOs? */ 568 bool use_leds; 569 570 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */ 571 u8 mmc_cd; 572 573 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */ 574 u32 debounce; 575 576 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup 577 * should be enabled. Else, if that bit is set in "pulldowns", 578 * that pulldown is enabled. Don't waste power by letting any 579 * digital inputs float... 580 */ 581 u32 pullups; 582 u32 pulldowns; 583 584 int (*setup)(struct device *dev, 585 unsigned gpio, unsigned ngpio); 586 int (*teardown)(struct device *dev, 587 unsigned gpio, unsigned ngpio); 588}; 589 590struct twl4030_madc_platform_data { 591 int irq_line; 592}; 593 594/* Boards have unique mappings of {row, col} --> keycode. 595 * Column and row are 8 bits each, but range only from 0..7. 596 * a PERSISTENT_KEY is "always on" and never reported. 597 */ 598#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED) 599 600struct twl4030_keypad_data { 601 const struct matrix_keymap_data *keymap_data; 602 unsigned rows; 603 unsigned cols; 604 bool rep; 605}; 606 607enum twl4030_usb_mode { 608 T2_USB_MODE_ULPI = 1, 609 T2_USB_MODE_CEA2011_3PIN = 2, 610}; 611 612struct twl4030_usb_data { 613 enum twl4030_usb_mode usb_mode; 614 unsigned long features; 615 616 int (*phy_init)(struct device *dev); 617 int (*phy_exit)(struct device *dev); 618 /* Power on/off the PHY */ 619 int (*phy_power)(struct device *dev, int iD, int on); 620 /* enable/disable phy clocks */ 621 int (*phy_set_clock)(struct device *dev, int on); 622 /* suspend/resume of phy */ 623 int (*phy_suspend)(struct device *dev, int suspend); 624}; 625 626struct twl4030_ins { 627 u16 pmb_message; 628 u8 delay; 629}; 630 631struct twl4030_script { 632 struct twl4030_ins *script; 633 unsigned size; 634 u8 flags; 635#define TWL4030_WRST_SCRIPT (1<<0) 636#define TWL4030_WAKEUP12_SCRIPT (1<<1) 637#define TWL4030_WAKEUP3_SCRIPT (1<<2) 638#define TWL4030_SLEEP_SCRIPT (1<<3) 639}; 640 641struct twl4030_resconfig { 642 u8 resource; 643 u8 devgroup; /* Processor group that Power resource belongs to */ 644 u8 type; /* Power resource addressed, 6 / broadcast message */ 645 u8 type2; /* Power resource addressed, 3 / broadcast message */ 646 u8 remap_off; /* off state remapping */ 647 u8 remap_sleep; /* sleep state remapping */ 648}; 649 650struct twl4030_power_data { 651 struct twl4030_script **scripts; 652 unsigned num; 653 struct twl4030_resconfig *resource_config; 654#define TWL4030_RESCONFIG_UNDEF ((u8)-1) 655}; 656 657extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts); 658extern int twl4030_remove_script(u8 flags); 659 660struct twl4030_codec_data { 661 unsigned int digimic_delay; /* in ms */ 662 unsigned int ramp_delay_value; 663 unsigned int offset_cncl_path; 664 unsigned int check_defaults:1; 665 unsigned int reset_registers:1; 666 unsigned int hs_extmute:1; 667 u16 hs_left_step; 668 u16 hs_right_step; 669 u16 hf_left_step; 670 u16 hf_right_step; 671 void (*set_hs_extmute)(int mute); 672}; 673 674struct twl4030_vibra_data { 675 unsigned int coexist; 676 677 /* twl6040 */ 678 unsigned int vibldrv_res; /* left driver resistance */ 679 unsigned int vibrdrv_res; /* right driver resistance */ 680 unsigned int viblmotor_res; /* left motor resistance */ 681 unsigned int vibrmotor_res; /* right motor resistance */ 682 int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */ 683 int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */ 684}; 685 686struct twl4030_audio_data { 687 unsigned int audio_mclk; 688 struct twl4030_codec_data *codec; 689 struct twl4030_vibra_data *vibra; 690 691 /* twl6040 */ 692 int audpwron_gpio; /* audio power-on gpio */ 693 int naudint_irq; /* audio interrupt */ 694 unsigned int irq_base; 695}; 696 697struct twl4030_platform_data { 698 unsigned irq_base, irq_end; 699 struct twl4030_clock_init_data *clock; 700 struct twl4030_bci_platform_data *bci; 701 struct twl4030_gpio_platform_data *gpio; 702 struct twl4030_madc_platform_data *madc; 703 struct twl4030_keypad_data *keypad; 704 struct twl4030_usb_data *usb; 705 struct twl4030_power_data *power; 706 struct twl4030_audio_data *audio; 707 708 /* Common LDO regulators for TWL4030/TWL6030 */ 709 struct regulator_init_data *vdac; 710 struct regulator_init_data *vaux1; 711 struct regulator_init_data *vaux2; 712 struct regulator_init_data *vaux3; 713 /* TWL4030 LDO regulators */ 714 struct regulator_init_data *vpll1; 715 struct regulator_init_data *vpll2; 716 struct regulator_init_data *vmmc1; 717 struct regulator_init_data *vmmc2; 718 struct regulator_init_data *vsim; 719 struct regulator_init_data *vaux4; 720 struct regulator_init_data *vio; 721 struct regulator_init_data *vdd1; 722 struct regulator_init_data *vdd2; 723 struct regulator_init_data *vintana1; 724 struct regulator_init_data *vintana2; 725 struct regulator_init_data *vintdig; 726 /* TWL6030 LDO regulators */ 727 struct regulator_init_data *vmmc; 728 struct regulator_init_data *vpp; 729 struct regulator_init_data *vusim; 730 struct regulator_init_data *vana; 731 struct regulator_init_data *vcxio; 732 struct regulator_init_data *vusb; 733 struct regulator_init_data *clk32kg; 734 /* TWL6025 LDO regulators */ 735 struct regulator_init_data *ldo1; 736 struct regulator_init_data *ldo2; 737 struct regulator_init_data *ldo3; 738 struct regulator_init_data *ldo4; 739 struct regulator_init_data *ldo5; 740 struct regulator_init_data *ldo6; 741 struct regulator_init_data *ldo7; 742 struct regulator_init_data *ldoln; 743 struct regulator_init_data *ldousb; 744 /* TWL6025 DCDC regulators */ 745 struct regulator_init_data *smps3; 746 struct regulator_init_data *smps4; 747 struct regulator_init_data *vio6025; 748}; 749 750/*----------------------------------------------------------------------*/ 751 752int twl4030_sih_setup(int module); 753 754/* Offsets to Power Registers */ 755#define TWL4030_VDAC_DEV_GRP 0x3B 756#define TWL4030_VDAC_DEDICATED 0x3E 757#define TWL4030_VAUX1_DEV_GRP 0x17 758#define TWL4030_VAUX1_DEDICATED 0x1A 759#define TWL4030_VAUX2_DEV_GRP 0x1B 760#define TWL4030_VAUX2_DEDICATED 0x1E 761#define TWL4030_VAUX3_DEV_GRP 0x1F 762#define TWL4030_VAUX3_DEDICATED 0x22 763 764static inline int twl4030charger_usb_en(int enable) { return 0; } 765 766/*----------------------------------------------------------------------*/ 767 768/* Linux-specific regulator identifiers ... for now, we only support 769 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2 770 * need to tie into hardware based voltage scaling (cpufreq etc), while 771 * VIO is generally fixed. 772 */ 773 774/* TWL4030 SMPS/LDO's */ 775/* EXTERNAL dc-to-dc buck converters */ 776#define TWL4030_REG_VDD1 0 777#define TWL4030_REG_VDD2 1 778#define TWL4030_REG_VIO 2 779 780/* EXTERNAL LDOs */ 781#define TWL4030_REG_VDAC 3 782#define TWL4030_REG_VPLL1 4 783#define TWL4030_REG_VPLL2 5 /* not on all chips */ 784#define TWL4030_REG_VMMC1 6 785#define TWL4030_REG_VMMC2 7 /* not on all chips */ 786#define TWL4030_REG_VSIM 8 /* not on all chips */ 787#define TWL4030_REG_VAUX1 9 /* not on all chips */ 788#define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */ 789#define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */ 790#define TWL4030_REG_VAUX3 12 /* not on all chips */ 791#define TWL4030_REG_VAUX4 13 /* not on all chips */ 792 793/* INTERNAL LDOs */ 794#define TWL4030_REG_VINTANA1 14 795#define TWL4030_REG_VINTANA2 15 796#define TWL4030_REG_VINTDIG 16 797#define TWL4030_REG_VUSB1V5 17 798#define TWL4030_REG_VUSB1V8 18 799#define TWL4030_REG_VUSB3V1 19 800 801/* TWL6030 SMPS/LDO's */ 802/* EXTERNAL dc-to-dc buck convertor controllable via SR */ 803#define TWL6030_REG_VDD1 30 804#define TWL6030_REG_VDD2 31 805#define TWL6030_REG_VDD3 32 806 807/* Non SR compliant dc-to-dc buck convertors */ 808#define TWL6030_REG_VMEM 33 809#define TWL6030_REG_V2V1 34 810#define TWL6030_REG_V1V29 35 811#define TWL6030_REG_V1V8 36 812 813/* EXTERNAL LDOs */ 814#define TWL6030_REG_VAUX1_6030 37 815#define TWL6030_REG_VAUX2_6030 38 816#define TWL6030_REG_VAUX3_6030 39 817#define TWL6030_REG_VMMC 40 818#define TWL6030_REG_VPP 41 819#define TWL6030_REG_VUSIM 42 820#define TWL6030_REG_VANA 43 821#define TWL6030_REG_VCXIO 44 822#define TWL6030_REG_VDAC 45 823#define TWL6030_REG_VUSB 46 824 825/* INTERNAL LDOs */ 826#define TWL6030_REG_VRTC 47 827#define TWL6030_REG_CLK32KG 48 828 829/* LDOs on 6025 have different names */ 830#define TWL6025_REG_LDO2 49 831#define TWL6025_REG_LDO4 50 832#define TWL6025_REG_LDO3 51 833#define TWL6025_REG_LDO5 52 834#define TWL6025_REG_LDO1 53 835#define TWL6025_REG_LDO7 54 836#define TWL6025_REG_LDO6 55 837#define TWL6025_REG_LDOLN 56 838#define TWL6025_REG_LDOUSB 57 839 840/* 6025 DCDC supplies */ 841#define TWL6025_REG_SMPS3 58 842#define TWL6025_REG_SMPS4 59 843#define TWL6025_REG_VIO 60 844 845 846#endif /* End of __TWL4030_H */ 847