vx_core.h revision 0ed1cad172176a4595f82e8cd9055938ad54bd4b
1/* 2 * Driver for Digigram VX soundcards 3 * 4 * Hardware core part 5 * 6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#ifndef __SOUND_VX_COMMON_H 24#define __SOUND_VX_COMMON_H 25 26#include <sound/pcm.h> 27#include <sound/hwdep.h> 28#include <linux/interrupt.h> 29 30#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) 31#if !defined(CONFIG_USE_VXLOADER) && !defined(CONFIG_SND_VX_LIB) /* built-in kernel */ 32#define SND_VX_FW_LOADER /* use the standard firmware loader */ 33#endif 34#endif 35 36struct firmware; 37struct device; 38 39#define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */ 40 41/* 42 */ 43#define SIZE_MAX_CMD 0x10 44#define SIZE_MAX_STATUS 0x10 45 46struct vx_rmh { 47 u16 LgCmd; /* length of the command to send (WORDs) */ 48 u16 LgStat; /* length of the status received (WORDs) */ 49 u32 Cmd[SIZE_MAX_CMD]; 50 u32 Stat[SIZE_MAX_STATUS]; 51 u16 DspStat; /* status type, RMP_SSIZE_XXX */ 52}; 53 54typedef u64 pcx_time_t; 55 56#define VX_MAX_PIPES 16 57#define VX_MAX_PERIODS 32 58#define VX_MAX_CODECS 2 59 60struct vx_ibl_info { 61 int size; /* the current IBL size (0 = query) in bytes */ 62 int max_size; /* max. IBL size in bytes */ 63 int min_size; /* min. IBL size in bytes */ 64 int granularity; /* granularity */ 65}; 66 67struct vx_pipe { 68 int number; 69 unsigned int is_capture: 1; 70 unsigned int data_mode: 1; 71 unsigned int running: 1; 72 unsigned int prepared: 1; 73 int channels; 74 unsigned int differed_type; 75 pcx_time_t pcx_time; 76 struct snd_pcm_substream *substream; 77 78 int hbuf_size; /* H-buffer size in bytes */ 79 int buffer_bytes; /* the ALSA pcm buffer size in bytes */ 80 int period_bytes; /* the ALSA pcm period size in bytes */ 81 int hw_ptr; /* the current hardware pointer in bytes */ 82 int position; /* the current position in frames (playback only) */ 83 int transferred; /* the transferred size (per period) in frames */ 84 int align; /* size of alignment */ 85 u64 cur_count; /* current sample position (for playback) */ 86 87 unsigned int references; /* an output pipe may be used for monitoring and/or playback */ 88 struct vx_pipe *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/ 89 90 struct tasklet_struct start_tq; 91}; 92 93struct vx_core; 94 95struct snd_vx_ops { 96 /* low-level i/o */ 97 unsigned char (*in8)(struct vx_core *chip, int reg); 98 unsigned int (*in32)(struct vx_core *chip, int reg); 99 void (*out8)(struct vx_core *chip, int reg, unsigned char val); 100 void (*out32)(struct vx_core *chip, int reg, unsigned int val); 101 /* irq */ 102 int (*test_and_ack)(struct vx_core *chip); 103 void (*validate_irq)(struct vx_core *chip, int enable); 104 /* codec */ 105 void (*write_codec)(struct vx_core *chip, int codec, unsigned int data); 106 void (*akm_write)(struct vx_core *chip, int reg, unsigned int data); 107 void (*reset_codec)(struct vx_core *chip); 108 void (*change_audio_source)(struct vx_core *chip, int src); 109 void (*set_clock_source)(struct vx_core *chp, int src); 110 /* chip init */ 111 int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw); 112 void (*reset_dsp)(struct vx_core *chip); 113 void (*reset_board)(struct vx_core *chip, int cold_reset); 114 int (*add_controls)(struct vx_core *chip); 115 /* pcm */ 116 void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime, 117 struct vx_pipe *pipe, int count); 118 void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime, 119 struct vx_pipe *pipe, int count); 120}; 121 122struct snd_vx_hardware { 123 const char *name; 124 int type; /* VX_TYPE_XXX */ 125 126 /* hardware specs */ 127 unsigned int num_codecs; 128 unsigned int num_ins; 129 unsigned int num_outs; 130 unsigned int output_level_max; 131}; 132 133/* hwdep id string */ 134#define SND_VX_HWDEP_ID "VX Loader" 135 136/* hardware type */ 137enum { 138 /* VX222 PCI */ 139 VX_TYPE_BOARD, /* old VX222 PCI */ 140 VX_TYPE_V2, /* VX222 V2 PCI */ 141 VX_TYPE_MIC, /* VX222 Mic PCI */ 142 /* VX-pocket */ 143 VX_TYPE_VXPOCKET, /* VXpocket V2 */ 144 VX_TYPE_VXP440, /* VXpocket 440 */ 145 VX_TYPE_NUMS 146}; 147 148/* chip status */ 149enum { 150 VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */ 151 VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */ 152 VX_STAT_CHIP_INIT = (1 << 2), /* all operational */ 153 VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */ 154 VX_STAT_IS_STALE = (1 << 15) /* device is stale */ 155}; 156 157/* min/max values for analog output for old codecs */ 158#define VX_ANALOG_OUT_LEVEL_MAX 0xe3 159 160struct vx_core { 161 /* ALSA stuff */ 162 struct snd_card *card; 163 struct snd_pcm *pcm[VX_MAX_CODECS]; 164 int type; /* VX_TYPE_XXX */ 165 166 int irq; 167 /* ports are defined externally */ 168 169 /* low-level functions */ 170 struct snd_vx_hardware *hw; 171 struct snd_vx_ops *ops; 172 173 spinlock_t lock; 174 spinlock_t irq_lock; 175 struct tasklet_struct tq; 176 177 unsigned int chip_status; 178 unsigned int pcm_running; 179 180 struct device *dev; 181 struct snd_hwdep *hwdep; 182 183 struct vx_rmh irq_rmh; /* RMH used in interrupts */ 184 185 unsigned int audio_info; /* see VX_AUDIO_INFO */ 186 unsigned int audio_ins; 187 unsigned int audio_outs; 188 struct vx_pipe **playback_pipes; 189 struct vx_pipe **capture_pipes; 190 191 /* clock and audio sources */ 192 unsigned int audio_source; /* current audio input source */ 193 unsigned int audio_source_target; 194 unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */ 195 unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */ 196 unsigned int freq; /* current frequency */ 197 unsigned int freq_detected; /* detected frequency from digital in */ 198 unsigned int uer_detected; /* VX_UER_MODE_XXX */ 199 unsigned int uer_bits; /* IEC958 status bits */ 200 struct vx_ibl_info ibl; /* IBL information */ 201 202 /* mixer setting */ 203 int output_level[VX_MAX_CODECS][2]; /* analog output level */ 204 int audio_gain[2][4]; /* digital audio level (playback/capture) */ 205 unsigned char audio_active[4]; /* mute/unmute on digital playback */ 206 int audio_monitor[4]; /* playback hw-monitor level */ 207 unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */ 208 209 struct semaphore mixer_mutex; 210 211 const struct firmware *firmware[4]; /* loaded firmware data */ 212}; 213 214 215/* 216 * constructor 217 */ 218struct vx_core *snd_vx_create(struct snd_card *card, struct snd_vx_hardware *hw, 219 struct snd_vx_ops *ops, int extra_size); 220int snd_vx_setup_firmware(struct vx_core *chip); 221int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp); 222int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp); 223int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp); 224 225void snd_vx_free_firmware(struct vx_core *chip); 226 227/* 228 * interrupt handler; exported for pcmcia 229 */ 230irqreturn_t snd_vx_irq_handler(int irq, void *dev, struct pt_regs *regs); 231 232/* 233 * lowlevel functions 234 */ 235static inline int vx_test_and_ack(struct vx_core *chip) 236{ 237 snd_assert(chip->ops->test_and_ack, return -ENXIO); 238 return chip->ops->test_and_ack(chip); 239} 240 241static inline void vx_validate_irq(struct vx_core *chip, int enable) 242{ 243 snd_assert(chip->ops->validate_irq, return); 244 chip->ops->validate_irq(chip, enable); 245} 246 247static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg) 248{ 249 snd_assert(chip->ops->in8, return 0); 250 return chip->ops->in8(chip, reg); 251} 252 253static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg) 254{ 255 snd_assert(chip->ops->in32, return 0); 256 return chip->ops->in32(chip, reg); 257} 258 259static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val) 260{ 261 snd_assert(chip->ops->out8, return); 262 chip->ops->out8(chip, reg, val); 263} 264 265static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val) 266{ 267 snd_assert(chip->ops->out32, return); 268 chip->ops->out32(chip, reg, val); 269} 270 271#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg) 272#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val) 273#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg) 274#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val) 275 276static inline void vx_reset_dsp(struct vx_core *chip) 277{ 278 snd_assert(chip->ops->reset_dsp, return); 279 chip->ops->reset_dsp(chip); 280} 281 282int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh); 283int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh); 284int vx_send_rih(struct vx_core *chip, int cmd); 285int vx_send_rih_nolock(struct vx_core *chip, int cmd); 286 287void vx_reset_codec(struct vx_core *chip, int cold_reset); 288 289/* 290 * check the bit on the specified register 291 * returns zero if a bit matches, or a negative error code. 292 * exported for vxpocket driver 293 */ 294int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time); 295#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time) 296#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200) 297#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL) 298 299 300/* 301 * pseudo-DMA transfer 302 */ 303static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, 304 struct vx_pipe *pipe, int count) 305{ 306 snd_assert(chip->ops->dma_write, return); 307 chip->ops->dma_write(chip, runtime, pipe, count); 308} 309 310static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, 311 struct vx_pipe *pipe, int count) 312{ 313 snd_assert(chip->ops->dma_read, return); 314 chip->ops->dma_read(chip, runtime, pipe, count); 315} 316 317 318 319/* error with hardware code, 320 * the return value is -(VX_ERR_MASK | actual-hw-error-code) 321 */ 322#define VX_ERR_MASK 0x1000000 323#define vx_get_error(err) (-(err) & ~VX_ERR_MASK) 324 325 326/* 327 * pcm stuff 328 */ 329int snd_vx_pcm_new(struct vx_core *chip); 330void vx_pcm_update_intr(struct vx_core *chip, unsigned int events); 331 332/* 333 * mixer stuff 334 */ 335int snd_vx_mixer_new(struct vx_core *chip); 336void vx_toggle_dac_mute(struct vx_core *chip, int mute); 337int vx_sync_audio_source(struct vx_core *chip); 338int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active); 339 340/* 341 * IEC958 & clock stuff 342 */ 343void vx_set_iec958_status(struct vx_core *chip, unsigned int bits); 344int vx_set_clock(struct vx_core *chip, unsigned int freq); 345void vx_set_internal_clock(struct vx_core *chip, unsigned int freq); 346int vx_change_frequency(struct vx_core *chip); 347 348 349/* 350 * PM 351 */ 352int snd_vx_suspend(struct vx_core *card, pm_message_t state); 353int snd_vx_resume(struct vx_core *card); 354 355/* 356 * hardware constants 357 */ 358 359#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD) 360#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET) 361 362/* audio input source */ 363enum { 364 VX_AUDIO_SRC_DIGITAL, 365 VX_AUDIO_SRC_LINE, 366 VX_AUDIO_SRC_MIC 367}; 368 369/* clock source */ 370enum { 371 INTERNAL_QUARTZ, 372 UER_SYNC 373}; 374 375/* clock mode */ 376enum { 377 VX_CLOCK_MODE_AUTO, /* depending on the current audio source */ 378 VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */ 379 VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */ 380}; 381 382/* SPDIF/UER type */ 383enum { 384 VX_UER_MODE_CONSUMER, 385 VX_UER_MODE_PROFESSIONAL, 386 VX_UER_MODE_NOT_PRESENT, 387}; 388 389/* register indices */ 390enum { 391 VX_ICR, 392 VX_CVR, 393 VX_ISR, 394 VX_IVR, 395 VX_RXH, 396 VX_TXH = VX_RXH, 397 VX_RXM, 398 VX_TXM = VX_RXM, 399 VX_RXL, 400 VX_TXL = VX_RXL, 401 VX_DMA, 402 VX_CDSP, 403 VX_RFREQ, 404 VX_RUER_V2, 405 VX_GAIN, 406 VX_DATA = VX_GAIN, 407 VX_MEMIRQ, 408 VX_ACQ, 409 VX_BIT0, 410 VX_BIT1, 411 VX_MIC0, 412 VX_MIC1, 413 VX_MIC2, 414 VX_MIC3, 415 VX_PLX0, 416 VX_PLX1, 417 VX_PLX2, 418 419 VX_LOFREQ, // V2: ACQ, VP: RFREQ 420 VX_HIFREQ, // V2: BIT0, VP: RUER_V2 421 VX_CSUER, // V2: BIT1, VP: BIT0 422 VX_RUER, // V2: RUER_V2, VP: BIT1 423 424 VX_REG_MAX, 425 426 /* aliases for VX board */ 427 VX_RESET_DMA = VX_ISR, 428 VX_CFG = VX_RFREQ, 429 VX_STATUS = VX_MEMIRQ, 430 VX_SELMIC = VX_MIC0, 431 VX_COMPOT = VX_MIC1, 432 VX_SCOMPR = VX_MIC2, 433 VX_GLIMIT = VX_MIC3, 434 VX_INTCSR = VX_PLX0, 435 VX_CNTRL = VX_PLX1, 436 VX_GPIOC = VX_PLX2, 437 438 /* aliases for VXPOCKET board */ 439 VX_MICRO = VX_MEMIRQ, 440 VX_CODEC2 = VX_MEMIRQ, 441 VX_DIALOG = VX_ACQ, 442 443}; 444 445/* RMH status type */ 446enum { 447 RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */ 448 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */ 449 RMH_SSIZE_MASK = 2, /* status size given in bitmask */ 450}; 451 452 453/* bits for ICR register */ 454#define ICR_HF1 0x10 455#define ICR_HF0 0x08 456#define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */ 457#define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */ 458 459/* bits for CVR register */ 460#define CVR_HC 0x80 461 462/* bits for ISR register */ 463#define ISR_HF3 0x10 464#define ISR_HF2 0x08 465#define ISR_CHK 0x10 466#define ISR_ERR 0x08 467#define ISR_TX_READY 0x04 468#define ISR_TX_EMPTY 0x02 469#define ISR_RX_FULL 0x01 470 471/* Constants used to access the DATA register */ 472#define VX_DATA_CODEC_MASK 0x80 473#define VX_DATA_XICOR_MASK 0x80 474 475/* Constants used to access the CSUER register (both for VX2 and VXP) */ 476#define VX_SUER_FREQ_MASK 0x0c 477#define VX_SUER_FREQ_32KHz_MASK 0x0c 478#define VX_SUER_FREQ_44KHz_MASK 0x00 479#define VX_SUER_FREQ_48KHz_MASK 0x04 480#define VX_SUER_DATA_PRESENT_MASK 0x02 481#define VX_SUER_CLOCK_PRESENT_MASK 0x01 482 483#define VX_CUER_HH_BITC_SEL_MASK 0x08 484#define VX_CUER_MH_BITC_SEL_MASK 0x04 485#define VX_CUER_ML_BITC_SEL_MASK 0x02 486#define VX_CUER_LL_BITC_SEL_MASK 0x01 487 488#define XX_UER_CBITS_OFFSET_MASK 0x1f 489 490 491/* bits for audio_info */ 492#define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */ 493#define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */ 494#define VX_AUDIO_INFO_MPEG1 (1<<5) 495#define VX_AUDIO_INFO_MPEG2 (1<<6) 496#define VX_AUDIO_INFO_LINEAR_8 (1<<7) 497#define VX_AUDIO_INFO_LINEAR_16 (1<<8) 498#define VX_AUDIO_INFO_LINEAR_24 (1<<9) 499 500/* DSP Interrupt Request values */ 501#define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */ 502/* call with vx_send_irq_dsp() */ 503#define IRQ_MESS_WRITE_END 0x30 504#define IRQ_MESS_WRITE_NEXT 0x32 505#define IRQ_MESS_READ_NEXT 0x34 506#define IRQ_MESS_READ_END 0x36 507#define IRQ_MESSAGE 0x38 508#define IRQ_RESET_CHK 0x3A 509#define IRQ_CONNECT_STREAM_NEXT 0x26 510#define IRQ_CONNECT_STREAM_END 0x28 511#define IRQ_PAUSE_START_CONNECT 0x2A 512#define IRQ_END_CONNECTION 0x2C 513 514/* Is there async. events pending ( IT Source Test ) */ 515#define ASYNC_EVENTS_PENDING 0x008000 516#define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate 517#define NOTIF_EVENTS_PENDING 0x002000 518#define TIME_CODE_EVENT_PENDING 0x001000 519#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800 520#define END_OF_BUFFER_EVENTS_PENDING 0x000400 521#define FATAL_DSP_ERROR 0xff0000 522 523/* Stream Format Header Defines */ 524#define HEADER_FMT_BASE 0xFED00000 525#define HEADER_FMT_MONO 0x000000C0 526#define HEADER_FMT_INTEL 0x00008000 527#define HEADER_FMT_16BITS 0x00002000 528#define HEADER_FMT_24BITS 0x00004000 529#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/ 530#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/ 531 532/* Constants used to access the Codec */ 533#define XX_CODEC_SELECTOR 0x20 534/* codec commands */ 535#define XX_CODEC_ADC_CONTROL_REGISTER 0x01 536#define XX_CODEC_DAC_CONTROL_REGISTER 0x02 537#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03 538#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04 539#define XX_CODEC_PORT_MODE_REGISTER 0x05 540#define XX_CODEC_STATUS_REPORT_REGISTER 0x06 541#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07 542 543/* 544 * Audio-level control values 545 */ 546#define CVAL_M110DB 0x000 /* -110dB */ 547#define CVAL_M99DB 0x02C 548#define CVAL_M21DB 0x163 549#define CVAL_M18DB 0x16F 550#define CVAL_M10DB 0x18F 551#define CVAL_0DB 0x1B7 552#define CVAL_18DB 0x1FF /* +18dB */ 553#define CVAL_MAX 0x1FF 554 555#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000 556#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000 557#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000 558#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01 559#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02 560#define VALID_AUDIO_IO_MUTE_LEVEL 0x04 561#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08 562#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10 563 564 565#endif /* __SOUND_VX_COMMON_H */ 566