vx_core.h revision 77933d7276ee8fa0e2947641941a6f7a100a327b
1/* 2 * Driver for Digigram VX soundcards 3 * 4 * Hardware core part 5 * 6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23#ifndef __SOUND_VX_COMMON_H 24#define __SOUND_VX_COMMON_H 25 26#include <sound/pcm.h> 27#include <sound/hwdep.h> 28#include <linux/interrupt.h> 29 30#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) 31#if !defined(CONFIG_USE_VXLOADER) && !defined(CONFIG_SND_VX_LIB) /* built-in kernel */ 32#define SND_VX_FW_LOADER /* use the standard firmware loader */ 33#endif 34#endif 35 36struct firmware; 37struct device; 38 39typedef struct snd_vx_core vx_core_t; 40typedef struct vx_pipe vx_pipe_t; 41 42#define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */ 43 44/* 45 */ 46#define SIZE_MAX_CMD 0x10 47#define SIZE_MAX_STATUS 0x10 48 49struct vx_rmh { 50 u16 LgCmd; /* length of the command to send (WORDs) */ 51 u16 LgStat; /* length of the status received (WORDs) */ 52 u32 Cmd[SIZE_MAX_CMD]; 53 u32 Stat[SIZE_MAX_STATUS]; 54 u16 DspStat; /* status type, RMP_SSIZE_XXX */ 55}; 56 57typedef u64 pcx_time_t; 58 59#define VX_MAX_PIPES 16 60#define VX_MAX_PERIODS 32 61#define VX_MAX_CODECS 2 62 63struct vx_ibl_info { 64 int size; /* the current IBL size (0 = query) in bytes */ 65 int max_size; /* max. IBL size in bytes */ 66 int min_size; /* min. IBL size in bytes */ 67 int granularity; /* granularity */ 68}; 69 70struct vx_pipe { 71 int number; 72 unsigned int is_capture: 1; 73 unsigned int data_mode: 1; 74 unsigned int running: 1; 75 unsigned int prepared: 1; 76 int channels; 77 unsigned int differed_type; 78 pcx_time_t pcx_time; 79 snd_pcm_substream_t *substream; 80 81 int hbuf_size; /* H-buffer size in bytes */ 82 int buffer_bytes; /* the ALSA pcm buffer size in bytes */ 83 int period_bytes; /* the ALSA pcm period size in bytes */ 84 int hw_ptr; /* the current hardware pointer in bytes */ 85 int position; /* the current position in frames (playback only) */ 86 int transferred; /* the transferred size (per period) in frames */ 87 int align; /* size of alignment */ 88 u64 cur_count; /* current sample position (for playback) */ 89 90 unsigned int references; /* an output pipe may be used for monitoring and/or playback */ 91 vx_pipe_t *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/ 92 93 struct tasklet_struct start_tq; 94}; 95 96struct snd_vx_ops { 97 /* low-level i/o */ 98 unsigned char (*in8)(vx_core_t *chip, int reg); 99 unsigned int (*in32)(vx_core_t *chip, int reg); 100 void (*out8)(vx_core_t *chip, int reg, unsigned char val); 101 void (*out32)(vx_core_t *chip, int reg, unsigned int val); 102 /* irq */ 103 int (*test_and_ack)(vx_core_t *chip); 104 void (*validate_irq)(vx_core_t *chip, int enable); 105 /* codec */ 106 void (*write_codec)(vx_core_t *chip, int codec, unsigned int data); 107 void (*akm_write)(vx_core_t *chip, int reg, unsigned int data); 108 void (*reset_codec)(vx_core_t *chip); 109 void (*change_audio_source)(vx_core_t *chip, int src); 110 void (*set_clock_source)(vx_core_t *chp, int src); 111 /* chip init */ 112 int (*load_dsp)(vx_core_t *chip, int idx, const struct firmware *fw); 113 void (*reset_dsp)(vx_core_t *chip); 114 void (*reset_board)(vx_core_t *chip, int cold_reset); 115 int (*add_controls)(vx_core_t *chip); 116 /* pcm */ 117 void (*dma_write)(vx_core_t *chip, snd_pcm_runtime_t *runtime, 118 vx_pipe_t *pipe, int count); 119 void (*dma_read)(vx_core_t *chip, snd_pcm_runtime_t *runtime, 120 vx_pipe_t *pipe, int count); 121}; 122 123struct snd_vx_hardware { 124 const char *name; 125 int type; /* VX_TYPE_XXX */ 126 127 /* hardware specs */ 128 unsigned int num_codecs; 129 unsigned int num_ins; 130 unsigned int num_outs; 131 unsigned int output_level_max; 132}; 133 134/* hwdep id string */ 135#define SND_VX_HWDEP_ID "VX Loader" 136 137/* hardware type */ 138enum { 139 /* VX222 PCI */ 140 VX_TYPE_BOARD, /* old VX222 PCI */ 141 VX_TYPE_V2, /* VX222 V2 PCI */ 142 VX_TYPE_MIC, /* VX222 Mic PCI */ 143 /* VX-pocket */ 144 VX_TYPE_VXPOCKET, /* VXpocket V2 */ 145 VX_TYPE_VXP440, /* VXpocket 440 */ 146 VX_TYPE_NUMS 147}; 148 149/* chip status */ 150enum { 151 VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */ 152 VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */ 153 VX_STAT_CHIP_INIT = (1 << 2), /* all operational */ 154 VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */ 155 VX_STAT_IS_STALE = (1 << 15) /* device is stale */ 156}; 157 158/* min/max values for analog output for old codecs */ 159#define VX_ANALOG_OUT_LEVEL_MAX 0xe3 160 161struct snd_vx_core { 162 /* ALSA stuff */ 163 snd_card_t *card; 164 snd_pcm_t *pcm[VX_MAX_CODECS]; 165 int type; /* VX_TYPE_XXX */ 166 167 int irq; 168 /* ports are defined externally */ 169 170 /* low-level functions */ 171 struct snd_vx_hardware *hw; 172 struct snd_vx_ops *ops; 173 174 spinlock_t lock; 175 spinlock_t irq_lock; 176 struct tasklet_struct tq; 177 178 unsigned int chip_status; 179 unsigned int pcm_running; 180 181 struct device *dev; 182 snd_hwdep_t *hwdep; 183 184 struct vx_rmh irq_rmh; /* RMH used in interrupts */ 185 186 unsigned int audio_info; /* see VX_AUDIO_INFO */ 187 unsigned int audio_ins; 188 unsigned int audio_outs; 189 struct vx_pipe **playback_pipes; 190 struct vx_pipe **capture_pipes; 191 192 /* clock and audio sources */ 193 unsigned int audio_source; /* current audio input source */ 194 unsigned int audio_source_target; 195 unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */ 196 unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */ 197 unsigned int freq; /* current frequency */ 198 unsigned int freq_detected; /* detected frequency from digital in */ 199 unsigned int uer_detected; /* VX_UER_MODE_XXX */ 200 unsigned int uer_bits; /* IEC958 status bits */ 201 struct vx_ibl_info ibl; /* IBL information */ 202 203 /* mixer setting */ 204 int output_level[VX_MAX_CODECS][2]; /* analog output level */ 205 int audio_gain[2][4]; /* digital audio level (playback/capture) */ 206 unsigned char audio_active[4]; /* mute/unmute on digital playback */ 207 int audio_monitor[4]; /* playback hw-monitor level */ 208 unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */ 209 210 struct semaphore mixer_mutex; 211 212 const struct firmware *firmware[4]; /* loaded firmware data */ 213}; 214 215 216/* 217 * constructor 218 */ 219vx_core_t *snd_vx_create(snd_card_t *card, struct snd_vx_hardware *hw, 220 struct snd_vx_ops *ops, int extra_size); 221int snd_vx_setup_firmware(vx_core_t *chip); 222int snd_vx_load_boot_image(vx_core_t *chip, const struct firmware *dsp); 223int snd_vx_dsp_boot(vx_core_t *chip, const struct firmware *dsp); 224int snd_vx_dsp_load(vx_core_t *chip, const struct firmware *dsp); 225 226void snd_vx_free_firmware(vx_core_t *chip); 227 228/* 229 * interrupt handler; exported for pcmcia 230 */ 231irqreturn_t snd_vx_irq_handler(int irq, void *dev, struct pt_regs *regs); 232 233/* 234 * lowlevel functions 235 */ 236static inline int vx_test_and_ack(vx_core_t *chip) 237{ 238 snd_assert(chip->ops->test_and_ack, return -ENXIO); 239 return chip->ops->test_and_ack(chip); 240} 241 242static inline void vx_validate_irq(vx_core_t *chip, int enable) 243{ 244 snd_assert(chip->ops->validate_irq, return); 245 chip->ops->validate_irq(chip, enable); 246} 247 248static inline unsigned char snd_vx_inb(vx_core_t *chip, int reg) 249{ 250 snd_assert(chip->ops->in8, return 0); 251 return chip->ops->in8(chip, reg); 252} 253 254static inline unsigned int snd_vx_inl(vx_core_t *chip, int reg) 255{ 256 snd_assert(chip->ops->in32, return 0); 257 return chip->ops->in32(chip, reg); 258} 259 260static inline void snd_vx_outb(vx_core_t *chip, int reg, unsigned char val) 261{ 262 snd_assert(chip->ops->out8, return); 263 chip->ops->out8(chip, reg, val); 264} 265 266static inline void snd_vx_outl(vx_core_t *chip, int reg, unsigned int val) 267{ 268 snd_assert(chip->ops->out32, return); 269 chip->ops->out32(chip, reg, val); 270} 271 272#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg) 273#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val) 274#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg) 275#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val) 276 277void snd_vx_delay(vx_core_t *chip, int msec); 278 279static inline void vx_reset_dsp(vx_core_t *chip) 280{ 281 snd_assert(chip->ops->reset_dsp, return); 282 chip->ops->reset_dsp(chip); 283} 284 285int vx_send_msg(vx_core_t *chip, struct vx_rmh *rmh); 286int vx_send_msg_nolock(vx_core_t *chip, struct vx_rmh *rmh); 287int vx_send_rih(vx_core_t *chip, int cmd); 288int vx_send_rih_nolock(vx_core_t *chip, int cmd); 289 290void vx_reset_codec(vx_core_t *chip, int cold_reset); 291 292/* 293 * check the bit on the specified register 294 * returns zero if a bit matches, or a negative error code. 295 * exported for vxpocket driver 296 */ 297int snd_vx_check_reg_bit(vx_core_t *chip, int reg, int mask, int bit, int time); 298#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time) 299#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200) 300#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL) 301 302 303/* 304 * pseudo-DMA transfer 305 */ 306static inline void vx_pseudo_dma_write(vx_core_t *chip, snd_pcm_runtime_t *runtime, 307 vx_pipe_t *pipe, int count) 308{ 309 snd_assert(chip->ops->dma_write, return); 310 chip->ops->dma_write(chip, runtime, pipe, count); 311} 312 313static inline void vx_pseudo_dma_read(vx_core_t *chip, snd_pcm_runtime_t *runtime, 314 vx_pipe_t *pipe, int count) 315{ 316 snd_assert(chip->ops->dma_read, return); 317 chip->ops->dma_read(chip, runtime, pipe, count); 318} 319 320 321 322/* error with hardware code, 323 * the return value is -(VX_ERR_MASK | actual-hw-error-code) 324 */ 325#define VX_ERR_MASK 0x1000000 326#define vx_get_error(err) (-(err) & ~VX_ERR_MASK) 327 328 329/* 330 * pcm stuff 331 */ 332int snd_vx_pcm_new(vx_core_t *chip); 333void vx_pcm_update_intr(vx_core_t *chip, unsigned int events); 334 335/* 336 * mixer stuff 337 */ 338int snd_vx_mixer_new(vx_core_t *chip); 339void vx_toggle_dac_mute(vx_core_t *chip, int mute); 340int vx_sync_audio_source(vx_core_t *chip); 341int vx_set_monitor_level(vx_core_t *chip, int audio, int level, int active); 342 343/* 344 * IEC958 & clock stuff 345 */ 346void vx_set_iec958_status(vx_core_t *chip, unsigned int bits); 347int vx_set_clock(vx_core_t *chip, unsigned int freq); 348void vx_set_internal_clock(vx_core_t *chip, unsigned int freq); 349int vx_change_frequency(vx_core_t *chip); 350 351 352/* 353 * hardware constants 354 */ 355 356#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD) 357#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET) 358 359/* audio input source */ 360enum { 361 VX_AUDIO_SRC_DIGITAL, 362 VX_AUDIO_SRC_LINE, 363 VX_AUDIO_SRC_MIC 364}; 365 366/* clock source */ 367enum { 368 INTERNAL_QUARTZ, 369 UER_SYNC 370}; 371 372/* clock mode */ 373enum { 374 VX_CLOCK_MODE_AUTO, /* depending on the current audio source */ 375 VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */ 376 VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */ 377}; 378 379/* SPDIF/UER type */ 380enum { 381 VX_UER_MODE_CONSUMER, 382 VX_UER_MODE_PROFESSIONAL, 383 VX_UER_MODE_NOT_PRESENT, 384}; 385 386/* register indices */ 387enum { 388 VX_ICR, 389 VX_CVR, 390 VX_ISR, 391 VX_IVR, 392 VX_RXH, 393 VX_TXH = VX_RXH, 394 VX_RXM, 395 VX_TXM = VX_RXM, 396 VX_RXL, 397 VX_TXL = VX_RXL, 398 VX_DMA, 399 VX_CDSP, 400 VX_RFREQ, 401 VX_RUER_V2, 402 VX_GAIN, 403 VX_DATA = VX_GAIN, 404 VX_MEMIRQ, 405 VX_ACQ, 406 VX_BIT0, 407 VX_BIT1, 408 VX_MIC0, 409 VX_MIC1, 410 VX_MIC2, 411 VX_MIC3, 412 VX_PLX0, 413 VX_PLX1, 414 VX_PLX2, 415 416 VX_LOFREQ, // V2: ACQ, VP: RFREQ 417 VX_HIFREQ, // V2: BIT0, VP: RUER_V2 418 VX_CSUER, // V2: BIT1, VP: BIT0 419 VX_RUER, // V2: RUER_V2, VP: BIT1 420 421 VX_REG_MAX, 422 423 /* aliases for VX board */ 424 VX_RESET_DMA = VX_ISR, 425 VX_CFG = VX_RFREQ, 426 VX_STATUS = VX_MEMIRQ, 427 VX_SELMIC = VX_MIC0, 428 VX_COMPOT = VX_MIC1, 429 VX_SCOMPR = VX_MIC2, 430 VX_GLIMIT = VX_MIC3, 431 VX_INTCSR = VX_PLX0, 432 VX_CNTRL = VX_PLX1, 433 VX_GPIOC = VX_PLX2, 434 435 /* aliases for VXPOCKET board */ 436 VX_MICRO = VX_MEMIRQ, 437 VX_CODEC2 = VX_MEMIRQ, 438 VX_DIALOG = VX_ACQ, 439 440}; 441 442/* RMH status type */ 443enum { 444 RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */ 445 RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */ 446 RMH_SSIZE_MASK = 2, /* status size given in bitmask */ 447}; 448 449 450/* bits for ICR register */ 451#define ICR_HF1 0x10 452#define ICR_HF0 0x08 453#define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */ 454#define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */ 455 456/* bits for CVR register */ 457#define CVR_HC 0x80 458 459/* bits for ISR register */ 460#define ISR_HF3 0x10 461#define ISR_HF2 0x08 462#define ISR_CHK 0x10 463#define ISR_ERR 0x08 464#define ISR_TX_READY 0x04 465#define ISR_TX_EMPTY 0x02 466#define ISR_RX_FULL 0x01 467 468/* Constants used to access the DATA register */ 469#define VX_DATA_CODEC_MASK 0x80 470#define VX_DATA_XICOR_MASK 0x80 471 472/* Constants used to access the CSUER register (both for VX2 and VXP) */ 473#define VX_SUER_FREQ_MASK 0x0c 474#define VX_SUER_FREQ_32KHz_MASK 0x0c 475#define VX_SUER_FREQ_44KHz_MASK 0x00 476#define VX_SUER_FREQ_48KHz_MASK 0x04 477#define VX_SUER_DATA_PRESENT_MASK 0x02 478#define VX_SUER_CLOCK_PRESENT_MASK 0x01 479 480#define VX_CUER_HH_BITC_SEL_MASK 0x08 481#define VX_CUER_MH_BITC_SEL_MASK 0x04 482#define VX_CUER_ML_BITC_SEL_MASK 0x02 483#define VX_CUER_LL_BITC_SEL_MASK 0x01 484 485#define XX_UER_CBITS_OFFSET_MASK 0x1f 486 487 488/* bits for audio_info */ 489#define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */ 490#define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */ 491#define VX_AUDIO_INFO_MPEG1 (1<<5) 492#define VX_AUDIO_INFO_MPEG2 (1<<6) 493#define VX_AUDIO_INFO_LINEAR_8 (1<<7) 494#define VX_AUDIO_INFO_LINEAR_16 (1<<8) 495#define VX_AUDIO_INFO_LINEAR_24 (1<<9) 496 497/* DSP Interrupt Request values */ 498#define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */ 499/* call with vx_send_irq_dsp() */ 500#define IRQ_MESS_WRITE_END 0x30 501#define IRQ_MESS_WRITE_NEXT 0x32 502#define IRQ_MESS_READ_NEXT 0x34 503#define IRQ_MESS_READ_END 0x36 504#define IRQ_MESSAGE 0x38 505#define IRQ_RESET_CHK 0x3A 506#define IRQ_CONNECT_STREAM_NEXT 0x26 507#define IRQ_CONNECT_STREAM_END 0x28 508#define IRQ_PAUSE_START_CONNECT 0x2A 509#define IRQ_END_CONNECTION 0x2C 510 511/* Is there async. events pending ( IT Source Test ) */ 512#define ASYNC_EVENTS_PENDING 0x008000 513#define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate 514#define NOTIF_EVENTS_PENDING 0x002000 515#define TIME_CODE_EVENT_PENDING 0x001000 516#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800 517#define END_OF_BUFFER_EVENTS_PENDING 0x000400 518#define FATAL_DSP_ERROR 0xff0000 519 520/* Stream Format Header Defines */ 521#define HEADER_FMT_BASE 0xFED00000 522#define HEADER_FMT_MONO 0x000000C0 523#define HEADER_FMT_INTEL 0x00008000 524#define HEADER_FMT_16BITS 0x00002000 525#define HEADER_FMT_24BITS 0x00004000 526#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/ 527#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/ 528 529/* Constants used to access the Codec */ 530#define XX_CODEC_SELECTOR 0x20 531/* codec commands */ 532#define XX_CODEC_ADC_CONTROL_REGISTER 0x01 533#define XX_CODEC_DAC_CONTROL_REGISTER 0x02 534#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03 535#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04 536#define XX_CODEC_PORT_MODE_REGISTER 0x05 537#define XX_CODEC_STATUS_REPORT_REGISTER 0x06 538#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07 539 540/* 541 * Audio-level control values 542 */ 543#define CVAL_M110DB 0x000 /* -110dB */ 544#define CVAL_M99DB 0x02C 545#define CVAL_M21DB 0x163 546#define CVAL_M18DB 0x16F 547#define CVAL_M10DB 0x18F 548#define CVAL_0DB 0x1B7 549#define CVAL_18DB 0x1FF /* +18dB */ 550#define CVAL_MAX 0x1FF 551 552#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000 553#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000 554#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000 555#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01 556#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02 557#define VALID_AUDIO_IO_MUTE_LEVEL 0x04 558#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08 559#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10 560 561 562#endif /* __SOUND_VX_COMMON_H */ 563