Lines Matching refs:i64
108 addRegisterClass(MVT::i64, &SPU::R64CRegClass);
121 setTruncStoreAction(MVT::i128, MVT::i64, Expand);
171 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
196 setOperationAction(ISD::SREM, MVT::i64, Expand);
197 setOperationAction(ISD::UREM, MVT::i64, Expand);
198 setOperationAction(ISD::SDIV, MVT::i64, Expand);
199 setOperationAction(ISD::UDIV, MVT::i64, Expand);
200 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
201 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
247 setOperationAction(ISD::SHL, MVT::i64, Legal);
248 setOperationAction(ISD::SRL, MVT::i64, Legal);
249 setOperationAction(ISD::SRA, MVT::i64, Legal);
251 // Custom lower i8, i32 and i64 multiplications
254 setOperationAction(ISD::MUL, MVT::i64, Legal);
270 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
271 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
272 setOperationAction(ISD::MULHU, MVT::i64, Expand);
273 setOperationAction(ISD::MULHS, MVT::i64, Expand);
275 // Need to custom handle (some) common i8, i64 math ops
277 setOperationAction(ISD::ADD, MVT::i64, Legal);
279 setOperationAction(ISD::SUB, MVT::i64, Legal);
284 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
289 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
295 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
300 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
306 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
311 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
319 setOperationAction(ISD::SELECT, MVT::i64, Legal);
324 setOperationAction(ISD::SETCC, MVT::i64, Legal);
327 // Custom lower i128 -> i64 truncates
328 setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
330 // Custom lower i32/i64 -> i128 sign extend
341 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
342 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
349 // SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
361 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
388 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
390 // Cell SPU has instructions for converting between i64 and fp.
391 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
392 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
394 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
398 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
716 // if there is no highpart (i.e. value is i64 and offset is 4), this
1107 SDValue T = DAG.getConstant(dbits, MVT::i64);
1165 case MVT::i64:
1329 case MVT::i64:
1539 if (ValueType == MVT::i64) {
1561 if (ValueType == MVT::i64) {
1584 if (ValueType == MVT::i64) {
1631 || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
1650 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
1699 SDValue T = DAG.getConstant(f64val, MVT::i64);
1871 } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
1978 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
1995 case MVT::i64:
2021 else if (VT == MVT::i64 && EltNo >= 2)
2022 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
2024 if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
2025 // i32 and i64: Element 0 is the preferred slot
2048 case MVT::i64:
2148 case MVT::i64:
2452 case MVT::i64:
2462 All conversions to i64 are expanded to a libcall.
2471 || OpVT == MVT::i64) {
2472 // Convert f32 / f64 to i32 / i64 via libcall.
2488 All conversions from i64 are expanded to a libcall.
2497 || Op0VT == MVT::i64) {
2498 // Convert i32, i64 to f64 via libcall:
2528 EVT IntVT(MVT::i64);
2688 if (Op0VT == MVT::i128 && simpleVT == MVT::i64) {
2709 * Emit the instruction sequence for i64/i32 -> i128 sign extend. The basic
2712 * the leftmost words and the i64/i32 into the rightmost words using shufb.
2736 // the type to extend from needs to be i64 or i32.
2737 assert((OpVT == MVT::i128 && (Op0VT == MVT::i64 || Op0VT == MVT::i32)) &&
2743 unsigned mask2 = Op0VT == MVT::i64 ? 0x00010203 : 0x10101010; // byte 8 - 11
2744 unsigned mask3 = Op0VT == MVT::i64 ? 0x04050607 : 0x00010203; // byte 12 - 15
2753 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32;
2810 // i8, i64 math ops:
3148 if (VT == MVT::i64)