Searched defs:BaseReg (Results 1 - 19 of 19) sorted by relevance

/external/llvm/include/llvm/Transforms/Utils/
H A DAddrModeMatcher.h37 Value *BaseReg; member in struct:llvm::ExtAddrMode
39 ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
44 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.cpp138 const MCOperand &BaseReg = MI->getOperand(Op); local
151 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
158 if (IndexReg.getReg() || BaseReg.getReg()) {
160 if (BaseReg.getReg())
H A DX86IntelInstPrinter.cpp129 const MCOperand &BaseReg = MI->getOperand(Op); local
144 if (BaseReg.getReg()) {
164 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
/external/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp179 unsigned DestReg, unsigned BaseReg, int NumBytes,
187 if (DestReg != ARM::SP && DestReg != BaseReg &&
209 .addReg(BaseReg, RegState::Kill)
216 .addReg(BaseReg, RegState::Kill)
227 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
230 .addReg(BaseReg).setMIFlags(MIFlags));
231 BaseReg = ARM::SP;
236 if (BaseReg == ARM::SP) {
242 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
260 assert(DestReg != ARM::SP && BaseReg !
177 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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H A DThumb1RegisterInfo.cpp93 unsigned DestReg, unsigned BaseReg,
100 (BaseReg != 0 && !isARMLowRegister(BaseReg));
112 assert(BaseReg == ARM::SP && "Unexpected!");
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
170 unsigned DestReg, unsigned BaseReg,
186 if (DestReg == BaseReg && BaseReg == ARM::SP) {
192 } else if (!isSub && BaseReg
90 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument
167 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument
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H A DThumb2SizeReduction.cpp380 unsigned BaseReg = MI->getOperand(0).getReg(); local
381 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
388 if (MI->getOperand(i).getReg() == BaseReg) {
402 unsigned BaseReg = MI->getOperand(1).getReg(); local
403 if (BaseReg != ARM::SP)
416 unsigned BaseReg = MI->getOperand(1).getReg(); local
417 if (BaseReg == ARM::SP &&
422 } else if (!isARMLowRegister(BaseReg) ||
H A DARMBaseRegisterInfo.cpp938 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
942 unsigned BaseReg, int FrameIdx,
956 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
958 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
967 unsigned BaseReg, int64_t Offset) const {
984 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
987 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
941 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
966 resolveFrameIndex(MachineBasicBlock::iterator I, unsigned BaseReg, int64_t Offset) const argument
H A DARMConstantIslandPass.cpp1879 unsigned BaseReg = MI->getOperand(0).getReg(); local
1891 while (PrevI != B && !PrevI->definesRegister(BaseReg))
1896 if (!PrevI->definesRegister(BaseReg))
1908 if (MO.isDef() && MO.getReg() != BaseReg) {
1922 for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI)
1930 LeaMI->getOperand(0).getReg() != BaseReg)
H A DARMISelDAGToDAG.cpp169 SDValue &BaseReg, SDValue &Opc);
386 SDValue &BaseReg,
398 BaseReg = N.getOperand(0);
409 SDValue &BaseReg,
422 BaseReg = N.getOperand(0);
1147 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, argument
1158 BaseReg = N.getOperand(0);
385 SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) argument
408 SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) argument
H A DARMLoadStoreOptimizer.cpp1077 unsigned BaseReg, bool BaseKill, bool BaseUndef,
1085 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1091 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1103 unsigned BaseReg = BaseOp.getReg(); local
1110 bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3();
1140 .addReg(BaseReg, getKillRegState(BaseKill))
1147 .addReg(BaseReg, getKillRegState(BaseKill))
1171 (TRI->regsOverlap(EvenReg, BaseReg))) {
1172 assert(!TRI->regsOverlap(OddReg, BaseReg));
1175 BaseReg, fals
1072 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1560 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument
1725 unsigned BaseReg = 0, PredReg = 0; local
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H A DARMBaseInstrInfo.cpp154 unsigned BaseReg = Base.getReg(); local
170 .addReg(BaseReg).addImm(Amt)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
182 .addReg(BaseReg).addReg(OffReg)
193 .addReg(BaseReg).addImm(Amt)
198 .addReg(BaseReg).addReg(OffReg)
220 .addReg(BaseReg).addImm(0).addImm(Pred);
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
1737 unsigned DestReg, unsigned BaseReg, int NumBytes,
1756 .addReg(BaseReg, RegStat
1735 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
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/external/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp290 unsigned BaseReg = 0; local
310 BaseReg = RegOffset.first;
319 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
321 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
328 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
339 std::pair<unsigned, int64_t>(BaseReg, BaseOffset));
343 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
347 TRI->resolveFrameIndex(I, BaseReg, Offset);
/external/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp312 const MachineOperand &BaseReg = MI->getOperand(Op); local
317 bool HasBaseReg = BaseReg.getReg() != 0;
319 BaseReg.getReg() == X86::RIP)
H A DX86InstrInfo.cpp1500 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { argument
1502 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1505 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1553 unsigned BaseReg = MI->getOperand(1).getReg(); local
1554 if (BaseReg == 0 || BaseReg == X86::RIP)
1561 return regIsPICBase(BaseReg, MRI);
1574 unsigned BaseReg = MI->getOperand(1).getReg(); local
1575 if (BaseReg == 0)
1580 return regIsPICBase(BaseReg, MR
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/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp192 unsigned BaseReg = MI->getOperand(0).getReg(); local
194 if (MI->getOperand(i).getReg() == BaseReg)
201 O << '\t' << getRegisterName(BaseReg);
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp166 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
169 if ((BaseReg.getReg() != 0 &&
170 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
181 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
184 if ((BaseReg.getReg() != 0 &&
185 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
196 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
199 if ((BaseReg.getReg() != 0 &&
200 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
306 unsigned BaseReg local
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/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h695 /// BaseReg to be a pointer to FrameIdx before insertion point I.
697 unsigned BaseReg, int FrameIdx,
706 unsigned BaseReg, int64_t Offset) const {
696 materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const argument
705 resolveFrameIndex(MachineBasicBlock::iterator I, unsigned BaseReg, int64_t Offset) const argument
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp191 unsigned BaseReg; member in struct:__anon8982::X86Operand::__anon8983::__anon8987
240 return Mem.BaseReg;
469 Res->Mem.BaseReg = 0;
478 unsigned BaseReg, unsigned IndexReg,
483 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
491 Res->Mem.BaseReg = BaseReg;
508 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
518 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
649 unsigned BaseReg local
477 CreateMem(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size = 0) argument
885 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; local
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/external/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp911 const SCEV *BaseReg = *I; local
912 if (VisitedRegs.count(BaseReg)) {
916 RatePrimaryRegister(BaseReg, Regs, L, SE, DT, LoserRegs);
1305 // ICmpZero BaseReg + Offset => ICmp BaseReg, -Offset
1314 // ICmpZero BaseReg + -1*ScaleReg => ICmp BaseReg, ScaleReg
3089 const SCEV *BaseReg = Base.BaseRegs[i]; local
3092 const SCEV *Remainder = CollectSubexprs(BaseReg, 0, AddOps, L, SE);
3174 const SCEV *BaseReg local
3582 const SCEV *BaseReg = F.BaseRegs[N]; local
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