/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 135 ISD::LoadExtType ExtType = LD->getExtensionType(); local 136 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { 358 ISD::LoadExtType ExtType = LD->getExtensionType(); local 366 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
|
H A D | LegalizeIntegerTypes.cpp | 416 ISD::LoadExtType ExtType = local 419 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 1788 ISD::LoadExtType ExtType = N->getExtensionType(); local 1800 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1806 if (ExtType == ISD::SEXTLOAD) { 1812 } else if (ExtType == ISD::ZEXTLOAD) { 1816 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1833 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, 1851 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1878 Hi = DAG.getNode(ExtType [all...] |
H A D | LegalizeVectorTypes.cpp | 786 ISD::LoadExtType ExtType = LD->getExtensionType(); local 799 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, 806 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, 1949 ISD::LoadExtType ExtType = LD->getExtensionType(); local 1953 if (ExtType != ISD::NON_EXTLOAD) 1954 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); 2513 ISD::LoadExtType ExtType) { 2536 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, 2544 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, 2511 GenWidenVectorExtLoads(SmallVector<SDValue, 16>& LdChain, LoadSDNode * LD, ISD::LoadExtType ExtType) argument
|
H A D | DAGCombiner.cpp | 158 ISD::NodeType ExtType); 722 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) local 727 return DAG.getExtLoad(ExtType, dl, PVT, 946 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) local 950 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 4227 ISD::NodeType ExtType) { 4238 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4984 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; local 4996 ExtType = ISD::SEXTLOAD; 5000 ExtType 4225 ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, SDValue Trunc, SDValue ExtLoad, DebugLoc DL, ISD::NodeType ExtType) argument 7879 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) local [all...] |
H A D | SelectionDAG.cpp | 2305 unsigned ExtType = LD->getExtensionType(); local 2306 switch (ExtType) { 4242 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument 4271 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO); 4275 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument 4280 ExtType = ISD::NON_EXTLOAD; 4281 } else if (ExtType == ISD::NON_EXTLOAD) { 4306 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile(), 4315 SDNode *N = new (NodeAllocator) LoadSDNode(Ops, dl, VTs, AM, ExtType, 4335 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLo argument [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 417 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { argument 418 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 421 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 426 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 427 return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal; 1107 void setLoadExtAction(unsigned ExtType, MVT VT, 1109 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 1111 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
|
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 566 ISD::LoadExtType ExtType = LN->getExtensionType(); local 738 if (ExtType == ISD::SEXTLOAD) { 740 } else if (ExtType == ISD::ZEXTLOAD) { 742 } else if (ExtType == ISD::EXTLOAD) {
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2124 ISD::LoadExtType ExtType = LD->getExtensionType(); local 2134 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 2153 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2154 (ExtType == ISD::EXTLOAD)) 2157 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
|