/external/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 100 MemOpQueue &MemOps, 116 unsigned Scratch, MemOpQueue &MemOps, 119 void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps); 363 // MergeOpsUpdate - call MergeOps and update MemOps and merges accordingly on 449 unsigned Scratch, MemOpQueue &MemOps, 452 int Offset = MemOps[SIndex].Offset; 455 MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI; 481 for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) { 482 int NewOffset = MemOps[i].Offset; 483 const MachineOperand &MO = MemOps[ 446 MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base, int Opcode, unsigned Size, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, MemOpQueue &MemOps, SmallVector<MachineBasicBlock::iterator, 4> &Merges) argument 1034 AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) argument 1222 MemOpQueue MemOps; local 1496 IsSafeAndProfitableToMove(bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSet<MachineInstr*, 4> &MemOps, SmallSet<unsigned, 4> &MemRegs, const TargetRegisterInfo *TRI) argument 1697 SmallPtrSet<MachineInstr*, 4> MemOps; local [all...] |
H A D | ARMISelLowering.cpp | 2563 SmallVector<SDValue, 4> MemOps; local 2577 MemOps.push_back(Store); 2581 if (!MemOps.empty()) 2583 &MemOps[0], MemOps.size());
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 831 SmallVector<SDValue, 4> MemOps; local 895 if (!MemOps.empty()) 896 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], 897 MemOps.size());
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1167 SmallVector<SDValue, 4> MemOps; local 1186 MemOps.push_back(Store); 1188 if (!MemOps.empty()) 1190 &MemOps[0], MemOps.size());
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 1228 SmallVector<SDValue, 79-3+1> MemOps; local 1240 MemOps.push_back(Store); 1245 if (!MemOps.empty()) 1247 &MemOps[0], MemOps.size());
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 3430 static bool FindOptimalMemOpLowering(std::vector<EVT> &MemOps, argument 3492 MemOps.push_back(VT); 3515 std::vector<EVT> MemOps; local 3531 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, 3538 Type *Ty = MemOps[0].getTypeForEVT(*DAG.getContext()); 3549 unsigned NumMemOps = MemOps.size(); 3552 EVT VT = MemOps[i]; 3608 std::vector<EVT> MemOps; local 3621 if (!FindOptimalMemOpLowering(MemOps, Limit, Size, 3627 Type *Ty = MemOps[ 3686 std::vector<EVT> MemOps; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1867 SmallVector<SDValue, 8> MemOps; local 1912 MemOps.push_back(Store); 1931 MemOps.push_back(Store); 1939 if (!MemOps.empty()) 1941 MVT::Other, &MemOps[0], MemOps.size()); 2046 SmallVector<SDValue, 8> MemOps; local 2100 MemOps.push_back(Store); 2124 MemOps.push_back(Store); 2297 MemOps [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 2041 SmallVector<SDValue, 8> MemOps; local 2056 MemOps.push_back(Store); 2080 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 2085 if (!MemOps.empty()) 2087 &MemOps[0], MemOps.size()); 9484 SmallVector<SDValue, 8> MemOps; local 9491 MemOps.push_back(Store); 9500 MemOps.push_back(Store); 9510 MemOps [all...] |