| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon8933
|
| /external/libffi/src/mips/ |
| H A D | ffitarget.h | 128 # define SRL srl macro
135 # define SRL dsrl
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 91 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 316 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
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| /external/llvm/include/llvm/TableGen/ |
| H A D | Record.h | 874 enum BinaryOp { SHL, SRA, SRL, STRCONCAT, CONCAT, EQ }; enumerator in enum:llvm::BinOpInit::BinaryOp
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 653 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
1845 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1846 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1892 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1893 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1933 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1958 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2037 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2039 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2078 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, D
2169 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); local
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 873 else if (Opc == ISD::SRL)
1114 case ISD::SRL: return visitSRL(N);
1197 case ISD::SRL:
1881 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, local
1884 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1885 AddToWorkList(SRL.getNode());
1935 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1949 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
2093 N1 = DAG.getNode(ISD::SRL, D
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 755 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
986 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
987 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
996 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
997 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1004 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1005 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SRL, MV
10732 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, local
10776 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, local
[all...] |