Searched defs:SubRegs (Results 1 - 4 of 4) sorted by relevance
/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 102 /// alias EAX. The SubRegs field is a zero terminated array of registers that 111 uint32_t SubRegs; // Sub-register set, described above member in struct:llvm::MCRegisterDesc 115 // sub-register in SubRegs. 391 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 125 return SubRegs; 221 SubRegMap SubRegs; member in struct:llvm::CodeGenRegister
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H A D | CodeGenRegisters.cpp | 105 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs"); 109 "SubRegs and SubRegIndices must have the same size"); 199 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 212 return SubRegs; 219 if (!SubRegs.insert(std::make_pair(Idx, SR)).second) 238 if (!SubRegs.insert(*SI).second) 251 CodeGenRegister *SR = SubRegs[Idx]; 263 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) 266 SubRegs 586 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 685 unsigned SubRegs = 0; local 690 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2; 692 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4; 695 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2; 697 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3; 699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4; 702 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2; 704 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2; 706 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; 715 BeginIdx = BeginIdx + ((SubRegs [all...] |
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