Searched refs:ADD (Results 51 - 75 of 156) sorted by relevance

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/external/quake/quake/src/QW/server/
H A Dqwsv.mak84 # ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_CONSOLE" /YX /c
85 # ADD CPP /nologo /GX /O2 /I "." /I "../client" /D "NDEBUG" /D "SERVERONLY" /D "WIN32" /D "_CONSOLE" /YX /c
91 # ADD BASE RSC /l 0x409 /d "NDEBUG"
92 # ADD RSC /l 0x409 /d "NDEBUG"
94 # ADD BASE BSC32 /nologo
95 # ADD BSC32 /nologo
100 # ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /machine:I386
101 # ADD LINK32 wsock32.lib kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:console /profile /machine:I386
212 # ADD BASE CPP /nologo /W3 /Gm /GX /Zi /Od /D "WIN32" /D "_DEBUG" /D "_CONSOLE" /YX /c
213 # ADD CP
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/external/icu4c/test/intltest/
H A Dcalregts.cpp1134 TRUE,//ADD,
1290 const int32_t ADD = 1; local
1295 onset - ONE_HOUR, ADD, 1, ONE_HOUR,
1296 onset, ADD, -1, -ONE_HOUR,
1299 cease - ONE_HOUR, ADD, 1, ONE_HOUR,
1300 cease, ADD, -1, -ONE_HOUR,
1314 case ADD:
1984 enum Action { ADD=1, ROLL=2 }; enumerator in enum:Action
1992 int8_t actionMask; // ADD or ROLL or both
2123 #define ADD_ROLL ADD|ROL
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp321 setOperationAction(ISD::ADD , VT, Legal);
872 if (N.getOpcode() == ISD::ADD) {
921 if (N.getOpcode() == ISD::ADD) {
932 // Match LOAD (ADD (X, Lo(G))).
1010 if (N.getOpcode() == ISD::ADD) {
1035 if (N.getOpcode() == ISD::ADD) {
1046 // Match LOAD (ADD (X, Lo(G))).
1209 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1214 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1396 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, d
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp356 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
358 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
477 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
533 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
543 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
600 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
682 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
787 Ptr = DAG.getNode(ISD::ADD, d
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H A DLegalizeIntegerTypes.cpp105 case ISD::ADD:
459 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
622 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1143 case ISD::ADD:
1529 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1535 if (N->getOpcode() == ISD::ADD) {
1547 if (N->getOpcode() == ISD::ADD) {
1548 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1549 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1559 Hi = DAG.getNode(ISD::ADD, d
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H A DFastISel.cpp472 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
491 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
501 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
525 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
532 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
943 return SelectBinaryOp(I, ISD::ADD);
H A DDAGCombiner.cpp1090 case ISD::ADD: return visitADD(N);
1187 case ISD::ADD:
1351 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1354 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1359 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1385 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1388 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1407 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1425 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1430 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD
1884 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); local
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/external/llvm/lib/Target/CellSPU/
H A DSPUISelLowering.cpp276 setOperationAction(ISD::ADD, MVT::i8, Custom);
277 setOperationAction(ISD::ADD, MVT::i64, Legal);
417 setOperationAction(ISD::ADD, VT, Legal);
467 setTargetDAGCombine(ISD::ADD);
595 if (basePtr.getOpcode() == ISD::ADD
629 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
635 if (basePtr.getOpcode() == ISD::ADD) {
664 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
705 DAG.getNode(ISD::ADD, dl, PtrVT,
803 if (basePtr.getOpcode() == ISD::ADD
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/external/dexmaker/src/dx/java/com/android/dx/rop/code/
H A DRops.java210 new Rop(RegOps.ADD, Type.INT, StdTypeList.INT_INT, "add-int");
214 new Rop(RegOps.ADD, Type.LONG, StdTypeList.LONG_LONG, "add-long");
218 new Rop(RegOps.ADD, Type.FLOAT, StdTypeList.FLOAT_FLOAT, "add-float");
222 new Rop(RegOps.ADD, Type.DOUBLE, StdTypeList.DOUBLE_DOUBLE,
371 new Rop(RegOps.ADD, Type.INT, StdTypeList.INT, "add-const-int");
375 new Rop(RegOps.ADD, Type.LONG, StdTypeList.LONG, "add-const-long");
379 new Rop(RegOps.ADD, Type.FLOAT, StdTypeList.FLOAT, "add-const-float");
383 new Rop(RegOps.ADD, Type.DOUBLE, StdTypeList.DOUBLE,
1138 case RegOps.ADD: return opAdd(sources);
H A DRop.java375 case RegOps.ADD:
/external/chromium/net/base/
H A Dcookie_monster_unittest.cc839 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[0].type);
854 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[2].type);
869 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[4].type);
904 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[0].type);
1337 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[0].type);
1344 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[1].type);
1357 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[3].type);
1365 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[5].type);
1373 EXPECT_EQ(CookieStoreCommand::ADD, store->commands()[6].type);
1382 EXPECT_EQ(CookieStoreCommand::ADD, stor
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H A Dcookie_monster_store_test.cc39 CookieStoreCommand(CookieStoreCommand::ADD, cookie));
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp716 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
850 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
851 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
852 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
853 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
1083 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1084 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1085 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1086 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1108 setOperationAction(ISD::ADD, MV
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/external/openssl/crypto/sha/asm/
H A Dsha512-ia64.pl72 $ADD="add";
86 $ADD="padd4";
494 { .mib; $ADD X[15]=X[15],X[15-9] // X[i&0xF]+=X[(i+9)&0xF]
522 $ADD X[15]=X[15],s0 };; // X[i&0xF]+=sigma0(X[(i+1)&0xF])
532 $ADD X[15]=X[15],s0 };; // X[i&0xF]+=sigma0(X[(i+1)&0xF])
539 $ADD X[15]=X[15],s1 // X[i&0xF]+=sigma1(X[(i+14)&0xF])
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp209 case ISD::ADD: {
418 case ISD::ADD:
/external/qemu/tcg/ppc64/
H A Dtcg-target.c335 #define ADD XO31(266) macro
583 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
601 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
686 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
814 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
967 tcg_out32 (s, ADD | RT (rt) | RA (ra));
1303 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1456 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
/external/chromium/chrome/browser/password_manager/
H A Dpassword_store_default.cc130 changes.push_back(PasswordStoreChange(PasswordStoreChange::ADD, form));
H A Dpassword_store_x.cc34 changes.push_back(PasswordStoreChange(PasswordStoreChange::ADD, form));
/external/chromium/chrome/browser/sync/glue/
H A Dpassword_change_processor.cc73 case PasswordStoreChange::ADD: {
/external/llvm/test/MC/ARM/
H A Dbasic-thumb-instructions.s31 @ ADD (immediate)
45 @ ADD (register)
55 @ ADD (SP plus immediate)
75 @ ADD (SP plus register)
/external/proguard/src/proguard/evaluation/value/
H A DSpecificIntegerValue.java205 return new CompositeIntegerValue(this, CompositeIntegerValue.ADD, other);
/external/quake/quake/src/QW/client/
H A Dqwcl.mak145 # ADD BASE CPP /nologo /W3 /GX /O2 /D "WIN32" /D "NDEBUG" /D "_WINDOWS" /YX /c
146 # ADD CPP /nologo /GX /O2 /I "..\..\scitech\include" /I "..\..\dxsdk\sdk\inc" /D "WIN32" /D "NDEBUG" /D "_WINDOWS" /YX /c
153 # ADD BASE MTL /nologo /D "NDEBUG" /win32
154 # ADD MTL /nologo /D "NDEBUG" /win32
156 # ADD BASE RSC /l 0x409 /d "NDEBUG"
157 # ADD RSC /l 0x409 /d "NDEBUG"
160 # ADD BASE BSC32 /nologo
161 # ADD BSC32 /nologo
166 # ADD BASE LINK32 kernel32.lib user32.lib gdi32.lib winspool.lib comdlg32.lib advapi32.lib shell32.lib ole32.lib oleaut32.lib uuid.lib odbc32.lib odbccp32.lib /nologo /subsystem:windows /machine:I386
167 # ADD LINK3
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/external/qemu/tcg/ppc/
H A Dtcg-target.c345 #define ADD XO31(266) macro
564 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
650 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
760 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
849 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
1375 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DSCCP.java406 case RegOps.ADD:
509 case RegOps.ADD:
/external/llvm/lib/Target/MBlaze/
H A DMBlazeFrameLowering.cpp381 BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19)
405 BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADD), MBlaze::R1)

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