Searched refs:AllocatableRegs (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp321 if (AllocatableRegs.empty())
322 AllocatableRegs = TRI->getAllocatableSet(MF);
324 if (AllocatableRegs.test(*AI))
H A DMachineCSE.cpp66 AllocatableRegs.clear();
81 BitVector AllocatableRegs; member in class:__anon8676::MachineCSE
245 if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i]))
638 AllocatableRegs = TRI->getAllocatableSet(MF);
H A DLiveIntervalAnalysis.cpp113 AllocatableRegs = TRI->getAllocatableSet(fn);
/external/llvm/include/llvm/CodeGen/
H A DLiveIntervalAnalysis.h68 /// AllocatableRegs - A bit vector of allocatable registers.
69 BitVector AllocatableRegs; member in class:llvm::LiveIntervals
129 return AllocatableRegs.test(reg);
H A DMachineRegisterInfo.h98 /// AllocatableRegs - From TRI->getAllocatableSet.
99 mutable BitVector AllocatableRegs; member in class:llvm::MachineRegisterInfo
/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp859 std::set<Record*> AllocatableRegs; local
867 AllocatableRegs.insert(Order.begin(), Order.end());
1042 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
H A DCodeGenRegisters.cpp1216 std::set<unsigned> AllocatableRegs; local
1230 AllocatableRegs.insert((*Regs.begin())->EnumValue);
1233 AllocatableRegs.insert((*I)->EnumValue);
1240 if (AllocatableRegs.count(RegNum))

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