Searched refs:OpNum (Results 1 - 24 of 24) sorted by relevance

/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.h39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
48 void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
51 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
52 void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
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H A DARMInstPrinter.cpp247 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, argument
249 const MCOperand &MO1 = MI->getOperand(OpNum);
263 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, argument
265 const MCOperand &MO1 = MI->getOperand(OpNum);
266 const MCOperand &MO2 = MI->getOperand(OpNum+1);
267 const MCOperand &MO3 = MI->getOperand(OpNum+2);
281 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, argument
283 const MCOperand &MO1 = MI->getOperand(OpNum);
284 const MCOperand &MO2 = MI->getOperand(OpNum+1);
390 unsigned OpNum,
389 printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
479 printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
497 printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
505 printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
513 printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
522 printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
529 printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
551 printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
564 printAddrMode7Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
570 printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
580 printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
591 printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
597 printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
608 printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
617 printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
627 printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
637 printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
646 printCPSIMod(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
652 printCPSIFlag(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
664 printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
744 printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
754 printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
761 printSBitModifierOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
770 printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
775 printPImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
780 printCImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
785 printCoprocOptionImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
790 printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
795 printAdrLabelOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
814 printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
819 printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
825 printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
903 printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
919 printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
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/external/llvm/lib/Target/
H A DTargetInstrInfo.cpp34 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument
37 if (OpNum >= MCID.getNumOperands())
40 short RegClass = MCID.OpInfo[OpNum].RegClass;
41 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
/external/llvm/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp49 void printOperand(const MachineInstr *MI, int OpNum,
51 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
66 const MachineOperand &MO = MI->getOperand(OpNum);
111 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, argument
113 const MachineOperand &Base = MI->getOperand(OpNum);
114 const MachineOperand &Disp = MI->getOperand(OpNum+1);
121 printOperand(MI, OpNum+1, O, "nohash");
126 printOperand(MI, OpNum, O);
/external/llvm/lib/Target/ARM/
H A DARMAsmPrinter.h60 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
63 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
66 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
H A DARMAsmPrinter.cpp330 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
332 const MachineOperand &MO = MI->getOperand(OpNum);
417 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
427 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
429 if (MI->getOperand(OpNum).isReg()) {
431 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
437 if (!MI->getOperand(OpNum).isImm())
439 O << MI->getOperand(OpNum).getImm();
443 printOperand(MI, OpNum, O);
446 if (MI->getOperand(OpNum)
557 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
953 int OpNum = 1; local
1004 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1; local
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H A DThumb2SizeReduction.cpp338 unsigned OpNum = 3; // First 'rest' of operands. local
376 OpNum = 4;
397 OpNum = 0;
406 OpNum = 2;
414 OpNum = 0;
421 OpNum = 2;
471 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
472 MIB.addOperand(MI->getOperand(OpNum));
H A DARMLoadStoreOptimizer.cpp783 for (unsigned OpNum = 3, e = MI->getNumOperands(); OpNum != e; ++OpNum)
784 MIB.addOperand(MI->getOperand(OpNum));
H A DARMISelLowering.cpp4481 unsigned OpNum = (PFEntry >> 26) & 0x0F; local
4503 if (OpNum == OP_COPY) {
4514 switch (OpNum) {
4532 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4538 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4542 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4546 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4550 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
/external/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp312 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
319 const MachineOperand &MO = MI->getOperand(OpNum);
323 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
359 if (OpNum == 0)
361 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
377 unsigned RegOp = OpNum;
383 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
386 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum
408 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
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H A DMipsAsmPrinter.h65 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
/external/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp2000 unsigned OpNum = 0; local
2002 if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
2003 getValue(Record, OpNum, LHS->getType(), RHS) ||
2004 OpNum+1 > Record.size())
2007 int Opc = GetDecodedBinaryOpcode(Record[OpNum++], LHS->getType());
2011 if (OpNum < Record.size()) {
2016 if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP))
2018 if (Record[OpNum] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
2024 if (Record[OpNum] & (1 << bitc::PEO_EXACT))
2031 unsigned OpNum local
2047 unsigned OpNum = 0; local
2069 unsigned OpNum = 0; local
2090 unsigned OpNum = 0; local
2115 unsigned OpNum = 0; local
2130 unsigned OpNum = 0; local
2155 unsigned OpNum = 0; local
2166 unsigned OpNum = 0; local
2179 unsigned OpNum = 0; local
2199 unsigned OpNum = 0; local
2223 unsigned OpNum = 0; local
2368 unsigned OpNum = 4; local
2493 unsigned OpNum = 0; local
2505 unsigned OpNum = 0; local
2526 unsigned OpNum = 0; local
2540 unsigned OpNum = 0; local
2563 unsigned OpNum = 0; local
2583 unsigned OpNum = 0; local
2623 unsigned OpNum = 2; local
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/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h149 int getOperandConstraint(unsigned OpNum, argument
151 if (OpNum < NumOperands &&
152 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
154 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp106 unsigned short OpNum; member in struct:Operator
112 : ShuffleMask(shufflemask), OpNum(opnum), Name(name), Cost(cost) {
394 unsigned OpNum = ShufTab[i].Op ? ShufTab[i].Op->OpNum : 0;
395 assert(OpNum < 16 && "Too few bits to encode operation!");
402 unsigned Val = (CostSat << 30) | (OpNum << 26) | (LHS << 13) | RHS;
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h357 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
359 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
364 unsigned OpNum,
H A DX86CodeEmitter.cpp760 unsigned OpNum) {
761 unsigned SrcReg = MI.getOperand(OpNum).getReg();
762 unsigned SrcRegNum = X86_MC::getX86RegNum(MI.getOperand(OpNum).getReg());
H A DX86InstrInfo.cpp3745 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, argument
3747 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3768 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, argument
3770 unsigned Reg = MI->getOperand(OpNum).getReg();
3979 unsigned OpNum = Ops[0]; local
3989 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3991 } else if (OpNum == 0) { // If operand 0
4000 } else if (OpNum == 1) {
4002 } else if (OpNum == 2) {
4004 } else if (OpNum
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H A DX86ISelLowering.cpp4653 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4657 unsigned NumElems, unsigned &OpNum) {
4677 OpNum = SeenV1 ? 0 : 1;
4655 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, unsigned MaskI, unsigned MaskE, unsigned OpIdx, unsigned NumElems, unsigned &OpNum) argument
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp264 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
266 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
268 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
270 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1226 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1228 const MCOperand &MO1 = MI.getOperand(OpNum);
1229 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1230 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1244 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1246 const MCOperand &MO1 = MI.getOperand(OpNum);
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/external/llvm/lib/CodeGen/
H A DRegAllocFast.cpp74 unsigned short LastOpNum; // OpNum on LastUse.
172 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
174 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
177 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
572 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, argument
597 LRI->LastOpNum = OpNum;
605 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, argument
612 MachineOperand &MO = MI->getOperand(OpNum);
648 LRI->LastOpNum = OpNum;
653 // setPhysReg - Change operand OpNum i
656 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument
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/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h59 /// class constraint for OpNum, or NULL.
61 unsigned OpNum,
910 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
928 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, argument
935 /// before MI to eliminate an unwanted dependency on OpNum.
952 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, argument
/external/clang/lib/Sema/
H A DSemaStmtAsm.cpp663 unsigned OpNum = 0; local
664 for (unsigned i = 0, e = OutputExprNames.size(); i != e; ++i, ++OpNum) {
668 OS << '$' << OpNum; local
671 for (unsigned i = 0, e = InputExprNames.size(); i != e; ++i, ++OpNum) {
675 OS << '$' << OpNum; local
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp68 unsigned OpNum) {
69 unsigned SrcReg = MI.getOperand(OpNum).getReg();
70 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
67 getVEXRegisterEncoding(const MCInst &MI, unsigned OpNum) argument
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4255 unsigned OpNum = (PFEntry >> 26) & 0x0F; local
4272 if (OpNum == OP_COPY) {
4283 switch (OpNum) {

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