/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.h | 111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { argument 113 if (!isAllocated(Regs[i])) 138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { argument 139 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 144 unsigned Reg = Regs[FirstUnalloc]; 150 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, argument 152 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 157 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterScavenging.h | 146 void setUsed(BitVector &Regs) { argument 147 RegsAvailable.reset(Regs); 149 void setUnused(BitVector &Regs) { argument 150 RegsAvailable |= Regs;
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H A D | CallingConvLower.h | 232 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const { argument 234 if (!isAllocated(Regs[i])) 259 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { argument 260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 265 unsigned Reg = Regs[FirstUnalloc]; 271 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, argument 273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 278 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
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H A D | RegisterPressure.h | 176 void addLiveRegs(ArrayRef<unsigned> Regs); 271 void increasePhysRegPressure(ArrayRef<unsigned> Regs); 272 void decreasePhysRegPressure(ArrayRef<unsigned> Regs); 274 void increaseVirtRegPressure(ArrayRef<unsigned> Regs); 275 void decreaseVirtRegPressure(ArrayRef<unsigned> Regs);
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H A D | MachineRegisterInfo.h | 385 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } argument
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/external/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor); 59 const std::vector<CodeGenRegister*> &Regs, 171 const CodeGenRegister::Set &Regs = RC.getMembers(); local 172 if (Regs.empty()) 177 OS << " {" << (*Regs.begin())->getWeight(RegBank) 247 const std::vector<CodeGenRegister*> &Regs, 255 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 256 Record *Reg = Regs[i]->TheDef; 274 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace"); 322 for (unsigned i = 0, e = Regs 246 EmitRegMappingTables(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument 372 EmitRegMapping(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) argument 544 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local 1037 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); local 1147 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); local [all...] |
H A D | CodeGenRegisters.cpp | 145 RegUnitIterator(const CodeGenRegister::Set &Regs): argument 146 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { 968 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); local 969 std::sort(Regs.begin(), Regs.end(), LessRecord()); 970 Registers.reserve(Regs.size()); 972 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 973 getReg(Regs[i]); 1192 CodeGenRegister::Set Regs; member in struct:__anon9307::UberRegSet 1223 const CodeGenRegister::Set &Regs = RegClass->getMembers(); local 1795 computeCoveredRegisters(ArrayRef<Record*> Regs) argument [all...] |
H A D | CodeGenTarget.cpp | 202 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); local 203 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 204 if (Regs[i]->TheDef->getValueAsString("AsmName") == Name) 205 return Regs[i];
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H A D | CodeGenRegisters.h | 621 // Compute the set of registers completely covered by the registers in Regs. 622 // The returned BitVector will have a bit set for each register in Regs, 624 // registers in Regs. 628 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
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H A D | AsmMatcherEmitter.cpp | 2136 const std::vector<CodeGenRegister*> &Regs = 2138 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 2139 const CodeGenRegister *Reg = Regs[i];
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/external/llvm/lib/CodeGen/ |
H A D | RegisterPressure.cpp | 86 void RegPressureTracker::increasePhysRegPressure(ArrayRef<unsigned> Regs) { argument 87 for (unsigned I = 0, E = Regs.size(); I != E; ++I) 89 TRI->getMinimalPhysRegClass(Regs[I]), TRI); 94 void RegPressureTracker::decreasePhysRegPressure(ArrayRef<unsigned> Regs) { argument 95 for (unsigned I = 0, E = Regs.size(); I != E; ++I) 96 decreaseSetPressure(CurrSetPressure, TRI->getMinimalPhysRegClass(Regs[I]), 102 void RegPressureTracker::increaseVirtRegPressure(ArrayRef<unsigned> Regs) { argument 103 for (unsigned I = 0, E = Regs.size(); I != E; ++I) 105 MRI->getRegClass(Regs[I]), TRI); 109 void RegPressureTracker::decreaseVirtRegPressure(ArrayRef<unsigned> Regs) { argument 273 hasRegAlias(unsigned Reg, SparseSet<unsigned> &Regs, const TargetRegisterInfo *TRI) argument 285 findRegAlias(unsigned Reg, SmallVectorImpl<unsigned> &Regs, const TargetRegisterInfo *TRI) argument 299 findReg(unsigned Reg, bool isVReg, SmallVectorImpl<unsigned> &Regs, const TargetRegisterInfo *TRI) argument 360 addLiveRegs(ArrayRef<unsigned> Regs) argument [all...] |
H A D | ExecutionDepsFix.cpp | 575 SmallVector<LiveReg, 4> Regs; local 586 for (SmallVector<LiveReg, 4>::iterator i = Regs.begin(), e = Regs.end(); 590 Regs.insert(i, LR); 594 Regs.push_back(LR); 600 while (!Regs.empty()) { 602 dv = Regs.pop_back_val().Value; 609 DomainValue *Latest = Regs.pop_back_val().Value;
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H A D | AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
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H A D | AggressiveAntiDepBreaker.cpp | 71 std::vector<unsigned> &Regs, 76 Regs.push_back(Reg); 554 std::vector<unsigned> Regs; 555 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); 556 assert(Regs.size() > 0 && "Empty register group!"); 557 if (Regs.size() == 0) 567 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 568 unsigned Reg = Regs[i]; 587 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 588 unsigned Reg = Regs[ 69 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) argument [all...] |
H A D | LocalStackSlotAllocation.cpp | 197 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs, argument 203 unsigned e = Regs.size(); 205 RegOffset = Regs[i];
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 588 SmallVector<std::pair<unsigned,bool>, 4> Regs; local 620 Regs.push_back(std::make_pair(Reg, isKill)); 623 if (Regs.empty()) 625 if (Regs.size() > 1 || StrOpc== 0) { 629 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 630 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 631 } else if (Regs.size() == 1) { 634 .addReg(Regs[0].first, getKillRegState(Regs[ 658 SmallVector<unsigned, 4> Regs; local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 97 ArrayRef<std::pair<unsigned, bool> > Regs, 279 /// registers in Regs as the register operands that would be loaded / stored. 287 ArrayRef<std::pair<unsigned, bool> > Regs, 290 unsigned NumRegs = Regs.size(); 320 NewBase = Regs[NumRegs-1].first; 353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 354 | getKillRegState(Regs[i].second)); 393 SmallVector<std::pair<unsigned, bool>, 8> Regs; local 400 Regs.push_back(std::make_pair(Reg, isKill)); 416 Pred, PredReg, Scratch, dl, Regs, ImpDef 282 MergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int Offset, unsigned Base, bool BaseKill, int Opcode, ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, DebugLoc dl, ArrayRef<std::pair<unsigned, bool> > Regs, ArrayRef<unsigned> ImpDefs) argument [all...] |
H A D | Thumb2SizeReduction.cpp | 193 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) 194 if (*Regs == ARM::CPSR)
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/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 803 SmallPtrSet<const SCEV *, 16> &Regs, 815 SmallPtrSet<const SCEV *, 16> &Regs, 819 SmallPtrSet<const SCEV *, 16> &Regs, 829 SmallPtrSet<const SCEV *, 16> &Regs, 851 if (!Regs.count(AR->getOperand(1))) { 852 RateRegister(AR->getOperand(1), Regs, L, SE, DT); 877 SmallPtrSet<const SCEV *, 16> &Regs, 885 if (Regs.insert(Reg)) { 886 RateRegister(Reg, Regs, L, SE, DT); 893 SmallPtrSet<const SCEV *, 16> &Regs, 828 RateRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument 876 RatePrimaryRegister(const SCEV *Reg, SmallPtrSet<const SCEV *, 16> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument 892 RateFormula(const Formula &F, SmallPtrSet<const SCEV *, 16> &Regs, const DenseSet<const SCEV *> &VisitedRegs, const Loop *L, const SmallVectorImpl<int64_t> &Offsets, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSet<const SCEV *, 16> *LoserRegs) argument 1149 SmallPtrSet<const SCEV *, 4> Regs; member in class:__anon9107::LSRUse 3661 SmallPtrSet<const SCEV *, 16> Regs; local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 575 /// Regs - This list holds the registers assigned to the values. 579 SmallVector<unsigned, 4> Regs; member in struct:__anon8726::RegsForValue 585 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 596 Regs.push_back(Reg + i); 616 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 671 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 673 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 682 if (!TargetRegisterInfo::isVirtualRegister(Regs[Par 5818 SmallVector<unsigned, 4> Regs; local [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 2191 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, argument 2195 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 2198 contains(Regs.front().first)) 2203 I = Regs.begin(), E = Regs.end(); I != E; ++I)
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