Searched refs:v4i8 (Results 1 - 8 of 8) sorted by relevance
/external/clang/test/CodeGen/ |
H A D | builtins-mips.c | 10 typedef signed char v4i8 __attribute__ ((vector_size(4))); typedef 19 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c; 27 v4i8_a = (v4i8) {1, 2, 3, 0xFF}; 28 v4i8_b = (v4i8) {2, 4, 6, 8}; 91 v4i8_a = (v4i8) {1, 2, 3, 4}; 124 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78}; 142 v4i8_a = (v4i8) {1, 2, 3, 4}; 145 v4i8_a = (v4i8) {128, 64, 32, 16}; 168 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7}; 211 v4i8_b = (v4i8) { [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 60 v4i8 = 14, // 4 x i8 enumerator in enum:llvm::MVT::SimpleValueType 237 case v4i8 : 277 case v4i8: 311 case v4i8: 398 if (NumElements == 4) return MVT::v4i8;
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 223 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_avar; break; 253 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_asi; break; 283 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_ari; break; 312 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_areg; break; 409 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_avar; break; 440 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_asi; break; 471 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_ari; break; 500 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_areg; break;
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H A D | NVPTXISelLowering.cpp | 100 addRegisterClass(MVT::v4i8, &NVPTX::V4I8RegsRegClass); 105 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i8 , Custom); 116 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i8 , Custom); 199 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i8 , Custom);
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/external/llvm/lib/VMCore/ |
H A D | ValueTypes.cpp | 124 case MVT::v4i8: return "v4i8"; 175 case MVT::v4i8: return VectorType::get(Type::getInt8Ty(Context), 4);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 72 case MVT::v4i8: return "MVT::v4i8";
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 15908 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32)) 15909 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15911 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15926 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) 15927 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) { 15929 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32; 15955 // v4i8 = FP_TO_SINT() -> v4i8 [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 559 // It is legal to extload from v4i8 to v4i16 or v4i32. 560 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
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