apicdef_32.h revision 4e468ed2eb86a2406e14f1eca82072ee501d05fd 
1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ****************************************************************************
11 ****************************************************************************/
12#ifndef __ASM_APICDEF_H
13#define __ASM_APICDEF_H
14
15#define APIC_DEFAULT_PHYS_BASE 0xfee00000
16
17#define APIC_ID 0x20
18#define APIC_LVR 0x30
19#define APIC_LVR_MASK 0xFF00FF
20#define GET_APIC_VERSION(x) ((x)&0xFF)
21#define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
22#define APIC_INTEGRATED(x) ((x)&0xF0)
23#define APIC_XAPIC(x) ((x) >= 0x14)
24#define APIC_TASKPRI 0x80
25#define APIC_TPRI_MASK 0xFF
26#define APIC_ARBPRI 0x90
27#define APIC_ARBPRI_MASK 0xFF
28#define APIC_PROCPRI 0xA0
29#define APIC_EOI 0xB0
30#define APIC_EIO_ACK 0x0
31#define APIC_RRR 0xC0
32#define APIC_LDR 0xD0
33#define APIC_LDR_MASK (0xFF<<24)
34#define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
35#define SET_APIC_LOGICAL_ID(x) (((x)<<24))
36#define APIC_ALL_CPUS 0xFF
37#define APIC_DFR 0xE0
38#define APIC_DFR_CLUSTER 0x0FFFFFFFul
39#define APIC_DFR_FLAT 0xFFFFFFFFul
40#define APIC_SPIV 0xF0
41#define APIC_SPIV_FOCUS_DISABLED (1<<9)
42#define APIC_SPIV_APIC_ENABLED (1<<8)
43#define APIC_ISR 0x100
44#define APIC_ISR_NR 0x8
45#define APIC_TMR 0x180
46#define APIC_IRR 0x200
47#define APIC_ESR 0x280
48#define APIC_ESR_SEND_CS 0x00001
49#define APIC_ESR_RECV_CS 0x00002
50#define APIC_ESR_SEND_ACC 0x00004
51#define APIC_ESR_RECV_ACC 0x00008
52#define APIC_ESR_SENDILL 0x00020
53#define APIC_ESR_RECVILL 0x00040
54#define APIC_ESR_ILLREGA 0x00080
55#define APIC_ICR 0x300
56#define APIC_DEST_SELF 0x40000
57#define APIC_DEST_ALLINC 0x80000
58#define APIC_DEST_ALLBUT 0xC0000
59#define APIC_ICR_RR_MASK 0x30000
60#define APIC_ICR_RR_INVALID 0x00000
61#define APIC_ICR_RR_INPROG 0x10000
62#define APIC_ICR_RR_VALID 0x20000
63#define APIC_INT_LEVELTRIG 0x08000
64#define APIC_INT_ASSERT 0x04000
65#define APIC_ICR_BUSY 0x01000
66#define APIC_DEST_LOGICAL 0x00800
67#define APIC_DM_FIXED 0x00000
68#define APIC_DM_LOWEST 0x00100
69#define APIC_DM_SMI 0x00200
70#define APIC_DM_REMRD 0x00300
71#define APIC_DM_NMI 0x00400
72#define APIC_DM_INIT 0x00500
73#define APIC_DM_STARTUP 0x00600
74#define APIC_DM_EXTINT 0x00700
75#define APIC_VECTOR_MASK 0x000FF
76#define APIC_ICR2 0x310
77#define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
78#define SET_APIC_DEST_FIELD(x) ((x)<<24)
79#define APIC_LVTT 0x320
80#define APIC_LVTTHMR 0x330
81#define APIC_LVTPC 0x340
82#define APIC_LVT0 0x350
83#define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
84#define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
85#define SET_APIC_TIMER_BASE(x) (((x)<<18))
86#define APIC_TIMER_BASE_CLKIN 0x0
87#define APIC_TIMER_BASE_TMBASE 0x1
88#define APIC_TIMER_BASE_DIV 0x2
89#define APIC_LVT_TIMER_PERIODIC (1<<17)
90#define APIC_LVT_MASKED (1<<16)
91#define APIC_LVT_LEVEL_TRIGGER (1<<15)
92#define APIC_LVT_REMOTE_IRR (1<<14)
93#define APIC_INPUT_POLARITY (1<<13)
94#define APIC_SEND_PENDING (1<<12)
95#define APIC_MODE_MASK 0x700
96#define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
97#define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
98#define APIC_MODE_FIXED 0x0
99#define APIC_MODE_NMI 0x4
100#define APIC_MODE_EXTINT 0x7
101#define APIC_LVT1 0x360
102#define APIC_LVTERR 0x370
103#define APIC_TMICT 0x380
104#define APIC_TMCCT 0x390
105#define APIC_TDCR 0x3E0
106#define APIC_TDR_DIV_TMBASE (1<<2)
107#define APIC_TDR_DIV_1 0xB
108#define APIC_TDR_DIV_2 0x0
109#define APIC_TDR_DIV_4 0x1
110#define APIC_TDR_DIV_8 0x2
111#define APIC_TDR_DIV_16 0x3
112#define APIC_TDR_DIV_32 0x8
113#define APIC_TDR_DIV_64 0x9
114#define APIC_TDR_DIV_128 0xA
115
116#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
117
118#define MAX_IO_APICS 64
119
120#define u32 unsigned int
121
122struct local_apic {
123
124  struct { u32 __reserved[4]; } __reserved_01;
125
126  struct { u32 __reserved[4]; } __reserved_02;
127
128  struct {
129 u32 __reserved_1 : 24,
130 phys_apic_id : 4,
131 __reserved_2 : 4;
132 u32 __reserved[3];
133 } id;
134
135  const
136 struct {
137 u32 version : 8,
138 __reserved_1 : 8,
139 max_lvt : 8,
140 __reserved_2 : 8;
141 u32 __reserved[3];
142 } version;
143
144  struct { u32 __reserved[4]; } __reserved_03;
145
146  struct { u32 __reserved[4]; } __reserved_04;
147
148  struct { u32 __reserved[4]; } __reserved_05;
149
150  struct { u32 __reserved[4]; } __reserved_06;
151
152  struct {
153 u32 priority : 8,
154 __reserved_1 : 24;
155 u32 __reserved_2[3];
156 } tpr;
157
158  const
159 struct {
160 u32 priority : 8,
161 __reserved_1 : 24;
162 u32 __reserved_2[3];
163 } apr;
164
165  const
166 struct {
167 u32 priority : 8,
168 __reserved_1 : 24;
169 u32 __reserved_2[3];
170 } ppr;
171
172  struct {
173 u32 eoi;
174 u32 __reserved[3];
175 } eoi;
176
177  struct { u32 __reserved[4]; } __reserved_07;
178
179  struct {
180 u32 __reserved_1 : 24,
181 logical_dest : 8;
182 u32 __reserved_2[3];
183 } ldr;
184
185  struct {
186 u32 __reserved_1 : 28,
187 model : 4;
188 u32 __reserved_2[3];
189 } dfr;
190
191  struct {
192 u32 spurious_vector : 8,
193 apic_enabled : 1,
194 focus_cpu : 1,
195 __reserved_2 : 22;
196 u32 __reserved_3[3];
197 } svr;
198
199  struct {
200  u32 bitfield;
201 u32 __reserved[3];
202 } isr [8];
203
204  struct {
205  u32 bitfield;
206 u32 __reserved[3];
207 } tmr [8];
208
209  struct {
210  u32 bitfield;
211 u32 __reserved[3];
212 } irr [8];
213
214  union {
215 struct {
216 u32 send_cs_error : 1,
217 receive_cs_error : 1,
218 send_accept_error : 1,
219 receive_accept_error : 1,
220 __reserved_1 : 1,
221 send_illegal_vector : 1,
222 receive_illegal_vector : 1,
223 illegal_register_address : 1,
224 __reserved_2 : 24;
225 u32 __reserved_3[3];
226 } error_bits;
227 struct {
228 u32 errors;
229 u32 __reserved_3[3];
230 } all_errors;
231 } esr;
232
233  struct { u32 __reserved[4]; } __reserved_08;
234
235  struct { u32 __reserved[4]; } __reserved_09;
236
237  struct { u32 __reserved[4]; } __reserved_10;
238
239  struct { u32 __reserved[4]; } __reserved_11;
240
241  struct { u32 __reserved[4]; } __reserved_12;
242
243  struct { u32 __reserved[4]; } __reserved_13;
244
245  struct { u32 __reserved[4]; } __reserved_14;
246
247  struct {
248 u32 vector : 8,
249 delivery_mode : 3,
250 destination_mode : 1,
251 delivery_status : 1,
252 __reserved_1 : 1,
253 level : 1,
254 trigger : 1,
255 __reserved_2 : 2,
256 shorthand : 2,
257 __reserved_3 : 12;
258 u32 __reserved_4[3];
259 } icr1;
260
261  struct {
262 union {
263 u32 __reserved_1 : 24,
264 phys_dest : 4,
265 __reserved_2 : 4;
266 u32 __reserved_3 : 24,
267 logical_dest : 8;
268 } dest;
269 u32 __reserved_4[3];
270 } icr2;
271
272  struct {
273 u32 vector : 8,
274 __reserved_1 : 4,
275 delivery_status : 1,
276 __reserved_2 : 3,
277 mask : 1,
278 timer_mode : 1,
279 __reserved_3 : 14;
280 u32 __reserved_4[3];
281 } lvt_timer;
282
283  struct {
284 u32 vector : 8,
285 delivery_mode : 3,
286 __reserved_1 : 1,
287 delivery_status : 1,
288 __reserved_2 : 3,
289 mask : 1,
290 __reserved_3 : 15;
291 u32 __reserved_4[3];
292 } lvt_thermal;
293
294  struct {
295 u32 vector : 8,
296 delivery_mode : 3,
297 __reserved_1 : 1,
298 delivery_status : 1,
299 __reserved_2 : 3,
300 mask : 1,
301 __reserved_3 : 15;
302 u32 __reserved_4[3];
303 } lvt_pc;
304
305  struct {
306 u32 vector : 8,
307 delivery_mode : 3,
308 __reserved_1 : 1,
309 delivery_status : 1,
310 polarity : 1,
311 remote_irr : 1,
312 trigger : 1,
313 mask : 1,
314 __reserved_2 : 15;
315 u32 __reserved_3[3];
316 } lvt_lint0;
317
318  struct {
319 u32 vector : 8,
320 delivery_mode : 3,
321 __reserved_1 : 1,
322 delivery_status : 1,
323 polarity : 1,
324 remote_irr : 1,
325 trigger : 1,
326 mask : 1,
327 __reserved_2 : 15;
328 u32 __reserved_3[3];
329 } lvt_lint1;
330
331  struct {
332 u32 vector : 8,
333 __reserved_1 : 4,
334 delivery_status : 1,
335 __reserved_2 : 3,
336 mask : 1,
337 __reserved_3 : 15;
338 u32 __reserved_4[3];
339 } lvt_error;
340
341  struct {
342 u32 initial_count;
343 u32 __reserved_2[3];
344 } timer_icr;
345
346  const
347 struct {
348 u32 curr_count;
349 u32 __reserved_2[3];
350 } timer_ccr;
351
352  struct { u32 __reserved[4]; } __reserved_16;
353
354  struct { u32 __reserved[4]; } __reserved_17;
355
356  struct { u32 __reserved[4]; } __reserved_18;
357
358  struct { u32 __reserved[4]; } __reserved_19;
359
360  struct {
361 u32 divisor : 4,
362 __reserved_1 : 28;
363 u32 __reserved_2[3];
364 } timer_dcr;
365
366  struct { u32 __reserved[4]; } __reserved_20;
367
368} __attribute__ ((packed));
369
370#undef u32
371
372#endif
373