msr-index.h revision 4b29af0a1b8b25b43e4c0cb9bf066c52f3add9bd
1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 **************************************************************************** 11 ****************************************************************************/ 12#ifndef __ASM_MSR_INDEX_H 13#define __ASM_MSR_INDEX_H 14 15#define MSR_EFER 0xc0000080 16#define MSR_STAR 0xc0000081 17#define MSR_LSTAR 0xc0000082 18#define MSR_CSTAR 0xc0000083 19#define MSR_SYSCALL_MASK 0xc0000084 20#define MSR_FS_BASE 0xc0000100 21#define MSR_GS_BASE 0xc0000101 22#define MSR_KERNEL_GS_BASE 0xc0000102 23 24#define _EFER_SCE 0 25#define _EFER_LME 8 26#define _EFER_LMA 10 27#define _EFER_NX 11 28 29#define EFER_SCE (1<<_EFER_SCE) 30#define EFER_LME (1<<_EFER_LME) 31#define EFER_LMA (1<<_EFER_LMA) 32#define EFER_NX (1<<_EFER_NX) 33 34#define MSR_IA32_PERFCTR0 0x000000c1 35#define MSR_IA32_PERFCTR1 0x000000c2 36#define MSR_FSB_FREQ 0x000000cd 37 38#define MSR_MTRRcap 0x000000fe 39#define MSR_IA32_BBL_CR_CTL 0x00000119 40 41#define MSR_IA32_SYSENTER_CS 0x00000174 42#define MSR_IA32_SYSENTER_ESP 0x00000175 43#define MSR_IA32_SYSENTER_EIP 0x00000176 44 45#define MSR_IA32_MCG_CAP 0x00000179 46#define MSR_IA32_MCG_STATUS 0x0000017a 47#define MSR_IA32_MCG_CTL 0x0000017b 48 49#define MSR_IA32_PEBS_ENABLE 0x000003f1 50#define MSR_IA32_DS_AREA 0x00000600 51#define MSR_IA32_PERF_CAPABILITIES 0x00000345 52 53#define MSR_MTRRfix64K_00000 0x00000250 54#define MSR_MTRRfix16K_80000 0x00000258 55#define MSR_MTRRfix16K_A0000 0x00000259 56#define MSR_MTRRfix4K_C0000 0x00000268 57#define MSR_MTRRfix4K_C8000 0x00000269 58#define MSR_MTRRfix4K_D0000 0x0000026a 59#define MSR_MTRRfix4K_D8000 0x0000026b 60#define MSR_MTRRfix4K_E0000 0x0000026c 61#define MSR_MTRRfix4K_E8000 0x0000026d 62#define MSR_MTRRfix4K_F0000 0x0000026e 63#define MSR_MTRRfix4K_F8000 0x0000026f 64#define MSR_MTRRdefType 0x000002ff 65 66#define MSR_IA32_DEBUGCTLMSR 0x000001d9 67#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 68#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 69#define MSR_IA32_LASTINTFROMIP 0x000001dd 70#define MSR_IA32_LASTINTTOIP 0x000001de 71 72#define MSR_IA32_MC0_CTL 0x00000400 73#define MSR_IA32_MC0_STATUS 0x00000401 74#define MSR_IA32_MC0_ADDR 0x00000402 75#define MSR_IA32_MC0_MISC 0x00000403 76 77#define MSR_P6_PERFCTR0 0x000000c1 78#define MSR_P6_PERFCTR1 0x000000c2 79#define MSR_P6_EVNTSEL0 0x00000186 80#define MSR_P6_EVNTSEL1 0x00000187 81 82#define MSR_AMD64_IBSFETCHCTL 0xc0011030 83#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 84#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 85#define MSR_AMD64_IBSOPCTL 0xc0011033 86#define MSR_AMD64_IBSOPRIP 0xc0011034 87#define MSR_AMD64_IBSOPDATA 0xc0011035 88#define MSR_AMD64_IBSOPDATA2 0xc0011036 89#define MSR_AMD64_IBSOPDATA3 0xc0011037 90#define MSR_AMD64_IBSDCLINAD 0xc0011038 91#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 92#define MSR_AMD64_IBSCTL 0xc001103a 93 94#define MSR_K8_TOP_MEM1 0xc001001a 95#define MSR_K8_TOP_MEM2 0xc001001d 96#define MSR_K8_SYSCFG 0xc0010010 97#define MSR_K8_HWCR 0xc0010015 98#define MSR_K8_ENABLE_C1E 0xc0010055 99#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 100#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 101#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 102 103#define MSR_K7_EVNTSEL0 0xc0010000 104#define MSR_K7_PERFCTR0 0xc0010004 105#define MSR_K7_EVNTSEL1 0xc0010001 106#define MSR_K7_PERFCTR1 0xc0010005 107#define MSR_K7_EVNTSEL2 0xc0010002 108#define MSR_K7_PERFCTR2 0xc0010006 109#define MSR_K7_EVNTSEL3 0xc0010003 110#define MSR_K7_PERFCTR3 0xc0010007 111#define MSR_K7_CLK_CTL 0xc001001b 112#define MSR_K7_HWCR 0xc0010015 113#define MSR_K7_FID_VID_CTL 0xc0010041 114#define MSR_K7_FID_VID_STATUS 0xc0010042 115 116#define MSR_K6_EFER 0xc0000080 117#define MSR_K6_STAR 0xc0000081 118#define MSR_K6_WHCR 0xc0000082 119#define MSR_K6_UWCCR 0xc0000085 120#define MSR_K6_EPMR 0xc0000086 121#define MSR_K6_PSOR 0xc0000087 122#define MSR_K6_PFIR 0xc0000088 123 124#define MSR_IDT_FCR1 0x00000107 125#define MSR_IDT_FCR2 0x00000108 126#define MSR_IDT_FCR3 0x00000109 127#define MSR_IDT_FCR4 0x0000010a 128 129#define MSR_IDT_MCR0 0x00000110 130#define MSR_IDT_MCR1 0x00000111 131#define MSR_IDT_MCR2 0x00000112 132#define MSR_IDT_MCR3 0x00000113 133#define MSR_IDT_MCR4 0x00000114 134#define MSR_IDT_MCR5 0x00000115 135#define MSR_IDT_MCR6 0x00000116 136#define MSR_IDT_MCR7 0x00000117 137#define MSR_IDT_MCR_CTRL 0x00000120 138 139#define MSR_VIA_FCR 0x00001107 140#define MSR_VIA_LONGHAUL 0x0000110a 141#define MSR_VIA_RNG 0x0000110b 142#define MSR_VIA_BCR2 0x00001147 143 144#define MSR_TMTA_LONGRUN_CTRL 0x80868010 145#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 146#define MSR_TMTA_LRTI_READOUT 0x80868018 147#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 148 149#define MSR_IA32_P5_MC_ADDR 0x00000000 150#define MSR_IA32_P5_MC_TYPE 0x00000001 151#define MSR_IA32_TSC 0x00000010 152#define MSR_IA32_PLATFORM_ID 0x00000017 153#define MSR_IA32_EBL_CR_POWERON 0x0000002a 154 155#define MSR_IA32_APICBASE 0x0000001b 156#define MSR_IA32_APICBASE_BSP (1<<8) 157#define MSR_IA32_APICBASE_ENABLE (1<<11) 158#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 159 160#define MSR_IA32_UCODE_WRITE 0x00000079 161#define MSR_IA32_UCODE_REV 0x0000008b 162 163#define MSR_IA32_PERF_STATUS 0x00000198 164#define MSR_IA32_PERF_CTL 0x00000199 165 166#define MSR_IA32_MPERF 0x000000e7 167#define MSR_IA32_APERF 0x000000e8 168 169#define MSR_IA32_THERM_CONTROL 0x0000019a 170#define MSR_IA32_THERM_INTERRUPT 0x0000019b 171#define MSR_IA32_THERM_STATUS 0x0000019c 172#define MSR_IA32_MISC_ENABLE 0x000001a0 173 174#define MSR_P6_EVNTSEL0 0x00000186 175#define MSR_P6_EVNTSEL1 0x00000187 176 177#define MSR_IA32_MCG_EAX 0x00000180 178#define MSR_IA32_MCG_EBX 0x00000181 179#define MSR_IA32_MCG_ECX 0x00000182 180#define MSR_IA32_MCG_EDX 0x00000183 181#define MSR_IA32_MCG_ESI 0x00000184 182#define MSR_IA32_MCG_EDI 0x00000185 183#define MSR_IA32_MCG_EBP 0x00000186 184#define MSR_IA32_MCG_ESP 0x00000187 185#define MSR_IA32_MCG_EFLAGS 0x00000188 186#define MSR_IA32_MCG_EIP 0x00000189 187#define MSR_IA32_MCG_RESERVED 0x0000018a 188 189#define MSR_P4_BPU_PERFCTR0 0x00000300 190#define MSR_P4_BPU_PERFCTR1 0x00000301 191#define MSR_P4_BPU_PERFCTR2 0x00000302 192#define MSR_P4_BPU_PERFCTR3 0x00000303 193#define MSR_P4_MS_PERFCTR0 0x00000304 194#define MSR_P4_MS_PERFCTR1 0x00000305 195#define MSR_P4_MS_PERFCTR2 0x00000306 196#define MSR_P4_MS_PERFCTR3 0x00000307 197#define MSR_P4_FLAME_PERFCTR0 0x00000308 198#define MSR_P4_FLAME_PERFCTR1 0x00000309 199#define MSR_P4_FLAME_PERFCTR2 0x0000030a 200#define MSR_P4_FLAME_PERFCTR3 0x0000030b 201#define MSR_P4_IQ_PERFCTR0 0x0000030c 202#define MSR_P4_IQ_PERFCTR1 0x0000030d 203#define MSR_P4_IQ_PERFCTR2 0x0000030e 204#define MSR_P4_IQ_PERFCTR3 0x0000030f 205#define MSR_P4_IQ_PERFCTR4 0x00000310 206#define MSR_P4_IQ_PERFCTR5 0x00000311 207#define MSR_P4_BPU_CCCR0 0x00000360 208#define MSR_P4_BPU_CCCR1 0x00000361 209#define MSR_P4_BPU_CCCR2 0x00000362 210#define MSR_P4_BPU_CCCR3 0x00000363 211#define MSR_P4_MS_CCCR0 0x00000364 212#define MSR_P4_MS_CCCR1 0x00000365 213#define MSR_P4_MS_CCCR2 0x00000366 214#define MSR_P4_MS_CCCR3 0x00000367 215#define MSR_P4_FLAME_CCCR0 0x00000368 216#define MSR_P4_FLAME_CCCR1 0x00000369 217#define MSR_P4_FLAME_CCCR2 0x0000036a 218#define MSR_P4_FLAME_CCCR3 0x0000036b 219#define MSR_P4_IQ_CCCR0 0x0000036c 220#define MSR_P4_IQ_CCCR1 0x0000036d 221#define MSR_P4_IQ_CCCR2 0x0000036e 222#define MSR_P4_IQ_CCCR3 0x0000036f 223#define MSR_P4_IQ_CCCR4 0x00000370 224#define MSR_P4_IQ_CCCR5 0x00000371 225#define MSR_P4_ALF_ESCR0 0x000003ca 226#define MSR_P4_ALF_ESCR1 0x000003cb 227#define MSR_P4_BPU_ESCR0 0x000003b2 228#define MSR_P4_BPU_ESCR1 0x000003b3 229#define MSR_P4_BSU_ESCR0 0x000003a0 230#define MSR_P4_BSU_ESCR1 0x000003a1 231#define MSR_P4_CRU_ESCR0 0x000003b8 232#define MSR_P4_CRU_ESCR1 0x000003b9 233#define MSR_P4_CRU_ESCR2 0x000003cc 234#define MSR_P4_CRU_ESCR3 0x000003cd 235#define MSR_P4_CRU_ESCR4 0x000003e0 236#define MSR_P4_CRU_ESCR5 0x000003e1 237#define MSR_P4_DAC_ESCR0 0x000003a8 238#define MSR_P4_DAC_ESCR1 0x000003a9 239#define MSR_P4_FIRM_ESCR0 0x000003a4 240#define MSR_P4_FIRM_ESCR1 0x000003a5 241#define MSR_P4_FLAME_ESCR0 0x000003a6 242#define MSR_P4_FLAME_ESCR1 0x000003a7 243#define MSR_P4_FSB_ESCR0 0x000003a2 244#define MSR_P4_FSB_ESCR1 0x000003a3 245#define MSR_P4_IQ_ESCR0 0x000003ba 246#define MSR_P4_IQ_ESCR1 0x000003bb 247#define MSR_P4_IS_ESCR0 0x000003b4 248#define MSR_P4_IS_ESCR1 0x000003b5 249#define MSR_P4_ITLB_ESCR0 0x000003b6 250#define MSR_P4_ITLB_ESCR1 0x000003b7 251#define MSR_P4_IX_ESCR0 0x000003c8 252#define MSR_P4_IX_ESCR1 0x000003c9 253#define MSR_P4_MOB_ESCR0 0x000003aa 254#define MSR_P4_MOB_ESCR1 0x000003ab 255#define MSR_P4_MS_ESCR0 0x000003c0 256#define MSR_P4_MS_ESCR1 0x000003c1 257#define MSR_P4_PMH_ESCR0 0x000003ac 258#define MSR_P4_PMH_ESCR1 0x000003ad 259#define MSR_P4_RAT_ESCR0 0x000003bc 260#define MSR_P4_RAT_ESCR1 0x000003bd 261#define MSR_P4_SAAT_ESCR0 0x000003ae 262#define MSR_P4_SAAT_ESCR1 0x000003af 263#define MSR_P4_SSU_ESCR0 0x000003be 264#define MSR_P4_SSU_ESCR1 0x000003bf 265 266#define MSR_P4_TBPU_ESCR0 0x000003c2 267#define MSR_P4_TBPU_ESCR1 0x000003c3 268#define MSR_P4_TC_ESCR0 0x000003c4 269#define MSR_P4_TC_ESCR1 0x000003c5 270#define MSR_P4_U2L_ESCR0 0x000003b0 271#define MSR_P4_U2L_ESCR1 0x000003b1 272 273#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 274#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 275#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 276#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 277#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 278#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 279#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 280 281#define MSR_GEODE_BUSCONT_CONF0 0x00001900 282 283#endif 284