1633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 2633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 1999, 2000 Ralf Baechle 3633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 4633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 5633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#ifndef _IOC3_H 6633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define _IOC3_H 7633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 8633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#include <linux/types.h> 9633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 10633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* SUPERIO uart register map */ 11633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamtypedef volatile struct ioc3_uartregs { 12633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham union { 13633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 rbr; /* read only, DLAB == 0 */ 14633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 thr; /* write only, DLAB == 0 */ 15633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 dll; /* DLAB == 1 */ 16633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham } u1; 17633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham union { 18633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 ier; /* DLAB == 0 */ 19633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 dlm; /* DLAB == 1 */ 20633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham } u2; 21633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham union { 22633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 iir; /* read only */ 23633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 fcr; /* write only */ 24633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham } u3; 25633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 iu_lcr; 26633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 iu_mcr; 27633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 iu_lsr; 28633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 iu_msr; 29633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 iu_scr; 30633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} ioc3_uregs_t; 31633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 32633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define iu_rbr u1.rbr 33633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define iu_thr u1.thr 34633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define iu_dll u1.dll 35633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define iu_ier u2.ier 36633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define iu_dlm u2.dlm 37633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define iu_iir u3.iir 38633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define iu_fcr u3.fcr 39633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 40633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct ioc3_sioregs { 41633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 fill[0x141]; /* starts at 0x141 */ 42633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 43633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 uartc; 44633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 kbdcg; 45633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 46633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 fill0[0x150 - 0x142 - 1]; 47633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 48633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 pp_data; 49633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 pp_dsr; 50633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 pp_dcr; 51633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 52633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 fill1[0x158 - 0x152 - 1]; 53633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 54633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 pp_fifa; 55633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 pp_cfgb; 56633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 pp_ecr; 57633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 58633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 fill2[0x168 - 0x15a - 1]; 59633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 60633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 rtcad; 61633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 rtcdat; 62633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 63633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u8 fill3[0x170 - 0x169 - 1]; 64633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 65633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct ioc3_uartregs uartb; /* 0x20170 */ 66633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct ioc3_uartregs uarta; /* 0x20178 */ 67633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 68633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 69633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Register layout of IOC3 in configuration space. */ 70633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct ioc3 { 71633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 pad0[7]; /* 0x00000 */ 72633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 sio_ir; /* 0x0001c */ 73633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 sio_ies; /* 0x00020 */ 74633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 sio_iec; /* 0x00024 */ 75633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 sio_cr; /* 0x00028 */ 76633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 int_out; /* 0x0002c */ 77633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 mcr; /* 0x00030 */ 78633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 79633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* General Purpose I/O registers */ 80633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gpcr_s; /* 0x00034 */ 81633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gpcr_c; /* 0x00038 */ 82633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gpdr; /* 0x0003c */ 83633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_0; /* 0x00040 */ 84633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_1; /* 0x00044 */ 85633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_2; /* 0x00048 */ 86633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_3; /* 0x0004c */ 87633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_4; /* 0x00050 */ 88633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_5; /* 0x00054 */ 89633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_6; /* 0x00058 */ 90633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_7; /* 0x0005c */ 91633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_8; /* 0x00060 */ 92633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_9; /* 0x00064 */ 93633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_10; /* 0x00068 */ 94633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_11; /* 0x0006c */ 95633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_12; /* 0x00070 */ 96633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_13; /* 0x00074 */ 97633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_14; /* 0x00078 */ 98633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 gppr_15; /* 0x0007c */ 99633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 100633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Parallel Port Registers */ 101633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ppbr_h_a; /* 0x00080 */ 102633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ppbr_l_a; /* 0x00084 */ 103633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ppcr_a; /* 0x00088 */ 104633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ppcr; /* 0x0008c */ 105633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ppbr_h_b; /* 0x00090 */ 106633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ppbr_l_b; /* 0x00094 */ 107633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ppcr_b; /* 0x00098 */ 108633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 109633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Keyboard and Mouse Registers */ 110633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 km_csr; /* 0x0009c */ 111633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 k_rd; /* 0x000a0 */ 112633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 m_rd; /* 0x000a4 */ 113633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 k_wd; /* 0x000a8 */ 114633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 m_wd; /* 0x000ac */ 115633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 116633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Serial Port Registers */ 117633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 sbbr_h; /* 0x000b0 */ 118633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 sbbr_l; /* 0x000b4 */ 119633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 sscr_a; /* 0x000b8 */ 120633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 stpir_a; /* 0x000bc */ 121633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 stcir_a; /* 0x000c0 */ 122633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 srpir_a; /* 0x000c4 */ 123633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 srcir_a; /* 0x000c8 */ 124633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 srtr_a; /* 0x000cc */ 125633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 shadow_a; /* 0x000d0 */ 126633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 sscr_b; /* 0x000d4 */ 127633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 stpir_b; /* 0x000d8 */ 128633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 stcir_b; /* 0x000dc */ 129633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 srpir_b; /* 0x000e0 */ 130633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 srcir_b; /* 0x000e4 */ 131633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 srtr_b; /* 0x000e8 */ 132633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 shadow_b; /* 0x000ec */ 133633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 134633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Ethernet Registers */ 135633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 emcr; /* 0x000f0 */ 136633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 eisr; /* 0x000f4 */ 137633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 eier; /* 0x000f8 */ 138633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ercsr; /* 0x000fc */ 139633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 erbr_h; /* 0x00100 */ 140633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 erbr_l; /* 0x00104 */ 141633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 erbar; /* 0x00108 */ 142633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ercir; /* 0x0010c */ 143633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 erpir; /* 0x00110 */ 144633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ertr; /* 0x00114 */ 145633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 etcsr; /* 0x00118 */ 146633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ersr; /* 0x0011c */ 147633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 etcdc; /* 0x00120 */ 148633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ebir; /* 0x00124 */ 149633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 etbr_h; /* 0x00128 */ 150633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 etbr_l; /* 0x0012c */ 151633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 etcir; /* 0x00130 */ 152633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 etpir; /* 0x00134 */ 153633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 emar_h; /* 0x00138 */ 154633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 emar_l; /* 0x0013c */ 155633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ehar_h; /* 0x00140 */ 156633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ehar_l; /* 0x00144 */ 157633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 micr; /* 0x00148 */ 158633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 midr_r; /* 0x0014c */ 159633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 midr_w; /* 0x00150 */ 160633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 pad1[(0x20000 - 0x00154) / 4]; 161633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 162633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* SuperIO Registers XXX */ 163633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham struct ioc3_sioregs sregs; /* 0x20000 */ 164633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 pad2[(0x40000 - 0x20180) / 4]; 165633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 166633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* SSRAM Diagnostic Access */ 167633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham volatile u32 ssram[(0x80000 - 0x40000) / 4]; 168633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 169633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* Bytebus device offsets 170633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 0x80000 - Access to the generic devices selected with DEV0 171633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 0x9FFFF bytebus DEV_SEL_0 172633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 0xA0000 - Access to the generic devices selected with DEV1 173633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 0xBFFFF bytebus DEV_SEL_1 174633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 0xC0000 - Access to the generic devices selected with DEV2 175633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 0xDFFFF bytebus DEV_SEL_2 176633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 0xE0000 - Access to the generic devices selected with DEV3 177633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 0xFFFFF bytebus DEV_SEL_3 */ 178633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 179633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 180633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 181633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Ethernet RX Buffer 182633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 183633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct ioc3_erxbuf { 184633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 w0; /* first word (valid,bcnt,cksum) */ 185633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 err; /* second word various errors */ 186633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* next comes n bytes of padding */ 187633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham /* then the received ethernet frame itself */ 188633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 189633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 190633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_IPCKSUM_MASK 0x0000ffff 191633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_BYTECNT_MASK 0x07ff0000 192633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_BYTECNT_SHIFT 16 193633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_V 0x80000000 194633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 195633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ 196633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ 197633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ 198633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ 199633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ 200633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ 201633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ 202633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ 203633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ 204633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ 205633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ 206633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ 207633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 208633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 209633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Ethernet TX Descriptor 210633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 211633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_DATALEN 104 212633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamstruct ioc3_etxd { 213633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 cmd; /* command field */ 214633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u32 bufcnt; /* buffer counts field */ 215633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u64 p1; /* buffer pointer 1 */ 216633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u64 p2; /* buffer pointer 2 */ 217633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham u8 data[ETXD_DATALEN]; /* opt. tx data */ 218633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham}; 219633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 220633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ 221633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_INTWHENDONE 0x00001000 /* intr when done */ 222633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_D0V 0x00010000 /* data 0 valid */ 223633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B1V 0x00020000 /* buf 1 valid */ 224633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B2V 0x00040000 /* buf 2 valid */ 225633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ 226633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ 227633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_CHKOFF_SHIFT 20 228633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 229633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_D0CNT_MASK 0x0000007f 230633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B1CNT_MASK 0x0007ff00 231633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B1CNT_SHIFT 8 232633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B2CNT_MASK 0x7ff00000 233633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B2CNT_SHIFT 20 234633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 235633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* 236633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * Bytebus device space 237633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 238633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_BYTEBUS_DEV0 0x80000L 239633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_BYTEBUS_DEV1 0xa0000L 240633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_BYTEBUS_DEV2 0xc0000L 241633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_BYTEBUS_DEV3 0xe0000L 242633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 243633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* ------------------------------------------------------------------------- */ 244633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 245633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* Superio Registers (PIO Access) */ 246633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SIO_BASE 0x20000 247633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SIO_UARTC (IOC3_SIO_BASE+0x141) /* UART Config */ 248633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SIO_KBDCG (IOC3_SIO_BASE+0x142) /* KBD Config */ 249633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SIO_PP_BASE (IOC3_SIO_BASE+PP_BASE) /* Parallel Port */ 250633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SIO_RTC_BASE (IOC3_SIO_BASE+0x168) /* Real Time Clock */ 251633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SIO_UB_BASE (IOC3_SIO_BASE+UARTB_BASE) /* UART B */ 252633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SIO_UA_BASE (IOC3_SIO_BASE+UARTA_BASE) /* UART A */ 253633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 254633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* SSRAM Diagnostic Access */ 255633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SSRAM IOC3_RAM_OFF /* base of SSRAM diagnostic access */ 256633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SSRAM_LEN 0x40000 /* 256kb (address space size, may not be fully populated) */ 257633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SSRAM_DM 0x0000ffff /* data mask */ 258633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SSRAM_PM 0x00010000 /* parity mask */ 259633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 260633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for PCI_SCR */ 261633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_PAR_RESP_EN 0x00000040 /* enb PCI parity checking */ 262633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_SERR_EN 0x00000100 /* enable the SERR# driver */ 263633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */ 264633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_RX_SERR (0x1 << 16) 265633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_DROP_MODE (0x1 << 17) 266633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_SIG_PAR_ERR (0x1 << 24) 267633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_SIG_TAR_ABRT (0x1 << 27) 268633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_RX_TAR_ABRT (0x1 << 28) 269633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_SIG_MST_ABRT (0x1 << 29) 270633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_SIG_SERR (0x1 << 30) 271633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PCI_SCR_PAR_ERR (0x1 << 31) 272633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 273633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_KM_CSR */ 274633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_WRT_PEND 0x00000001 /* kbd port xmitting or resetting */ 275633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_WRT_PEND 0x00000002 /* mouse port xmitting or resetting */ 276633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_LCB 0x00000004 /* Line Cntrl Bit for last KBD write */ 277633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_LCB 0x00000008 /* same for mouse */ 278633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_DATA 0x00000010 /* state of kbd data line */ 279633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_CLK 0x00000020 /* state of kbd clock line */ 280633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_PULL_DATA 0x00000040 /* pull kbd data line low */ 281633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_PULL_CLK 0x00000080 /* pull kbd clock line low */ 282633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_DATA 0x00000100 /* state of ms data line */ 283633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_CLK 0x00000200 /* state of ms clock line */ 284633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_PULL_DATA 0x00000400 /* pull ms data line low */ 285633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_PULL_CLK 0x00000800 /* pull ms clock line low */ 286633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_EMM_MODE 0x00001000 /* emulation mode */ 287633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_SIM_MODE 0x00002000 /* clock X8 */ 288633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_SM_IDLE 0x00004000 /* Keyboard is idle */ 289633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_SM_IDLE 0x00008000 /* Mouse is idle */ 290633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_TO 0x00010000 /* Keyboard trying to send/receive */ 291633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_TO 0x00020000 /* Mouse trying to send/receive */ 292633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_TO_EN 0x00040000 /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause 293633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR to assert */ 294633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_TO_EN 0x00080000 /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause 295633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR to assert */ 296633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_CLAMP_ONE 0x00100000 /* Pull K_CLK low after rec. one char */ 297633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_CLAMP_ONE 0x00200000 /* Pull M_CLK low after rec. one char */ 298633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_K_CLAMP_THREE 0x00400000 /* Pull K_CLK low after rec. three chars */ 299633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_CSR_M_CLAMP_THREE 0x00800000 /* Pull M_CLK low after rec. three char */ 300633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 301633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_K_RD and IOC3_M_RD */ 302633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_DATA_2 0x000000ff /* 3rd char recvd since last read */ 303633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_DATA_2_SHIFT 0 304633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_DATA_1 0x0000ff00 /* 2nd char recvd since last read */ 305633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_DATA_1_SHIFT 8 306633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_DATA_0 0x00ff0000 /* 1st char recvd since last read */ 307633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_DATA_0_SHIFT 16 308633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_FRAME_ERR_2 0x01000000 /* framing or parity error in byte 2 */ 309633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_FRAME_ERR_1 0x02000000 /* same for byte 1 */ 310633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_FRAME_ERR_0 0x04000000 /* same for byte 0 */ 311633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 312633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_KBD_MSE 0x08000000 /* 0 if from kbd, 1 if from mouse */ 313633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_OFLO 0x10000000 /* 4th char recvd before this read */ 314633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_VALID_2 0x20000000 /* DATA_2 valid */ 315633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_VALID_1 0x40000000 /* DATA_1 valid */ 316633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_VALID_0 0x80000000 /* DATA_0 valid */ 317633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2) 318633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 319633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_K_WD & IOC3_M_WD */ 320633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_WD_WRT_DATA 0x000000ff /* write to keyboard/mouse port */ 321633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define KM_WD_WRT_DATA_SHIFT 0 322633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 323633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for serial RX status byte */ 324633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define RXSB_OVERRUN 0x01 /* char(s) lost */ 325633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define RXSB_PAR_ERR 0x02 /* parity error */ 326633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define RXSB_FRAME_ERR 0x04 /* framing error */ 327633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define RXSB_BREAK 0x08 /* break character */ 328633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define RXSB_CTS 0x10 /* state of CTS */ 329633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define RXSB_DCD 0x20 /* state of DCD */ 330633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */ 331633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define RXSB_DATA_VALID 0x80 /* data byte, FRAME_ERR PAR_ERR & BREAK valid */ 332633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 333633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for serial TX control byte */ 334633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */ 335633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define TXCB_INVALID 0x00 /* byte is invalid */ 336633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define TXCB_VALID 0x40 /* byte is valid */ 337633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define TXCB_MCR 0x80 /* data<7:0> to modem control register */ 338633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */ 339633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 340633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_SBBR_L */ 341633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SBBR_L_SIZE 0x00000001 /* 0 == 1KB rings, 1 == 4KB rings */ 342633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SBBR_L_BASE 0xfffff000 /* lower serial ring base addr */ 343633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 344633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_SSCR_<A:B> */ 345633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */ 346633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */ 347633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_HFC_EN 0x00020000 /* hardware flow control enabled */ 348633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_RX_RING_DCD 0x00040000 /* post RX record on delta-DCD */ 349633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_RX_RING_CTS 0x00080000 /* post RX record on delta-CTS */ 350633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */ 351633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_DIAG 0x00200000 /* bypass clock divider for sim */ 352633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */ 353633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */ 354633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */ 355633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */ 356633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SSCR_RESET 0x80000000 /* reset DMA channels */ 357633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 358633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* all producer/comsumer pointers are the same bitfield */ 359633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ 360633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ 361633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define PROD_CONS_PTR_OFF 3 362633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 363633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_SRCIR_<A:B> */ 364633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SRCIR_ARM 0x80000000 /* arm RX timer */ 365633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 366633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_SRPIR_<A:B> */ 367633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SRPIR_BYTE_CNT 0x07000000 /* bytes in packer */ 368633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SRPIR_BYTE_CNT_SHIFT 24 369633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 370633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_STCIR_<A:B> */ 371633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define STCIR_BYTE_CNT 0x0f000000 /* bytes in unpacker */ 372633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define STCIR_BYTE_CNT_SHIFT 24 373633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 374633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_SHADOW_<A:B> */ 375633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_DR 0x00000001 /* data ready */ 376633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_OE 0x00000002 /* overrun error */ 377633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_PE 0x00000004 /* parity error */ 378633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_FE 0x00000008 /* framing error */ 379633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_BI 0x00000010 /* break interrupt */ 380633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_THRE 0x00000020 /* transmit holding register empty */ 381633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_TEMT 0x00000040 /* transmit shift register empty */ 382633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_RFCE 0x00000080 /* char in RX fifo has an error */ 383633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_DCTS 0x00010000 /* delta clear to send */ 384633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */ 385633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_CTS 0x00100000 /* clear to send */ 386633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_DCD 0x00800000 /* data carrier detect */ 387633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_DTR 0x01000000 /* data terminal ready */ 388633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_RTS 0x02000000 /* request to send */ 389633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */ 390633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */ 391633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SHADOW_LOOP 0x10000000 /* loopback enabled */ 392633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 393633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_SRTR_<A:B> */ 394633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SRTR_CNT 0x00000fff /* reload value for RX timer */ 395633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */ 396633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SRTR_CNT_VAL_SHIFT 16 397633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SRTR_HZ 16000 /* SRTR clock frequency */ 398633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 399633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES */ 400633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */ 401633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */ 402633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */ 403633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */ 404633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */ 405633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */ 406633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */ 407633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */ 408633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */ 409633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_TX_MT 0x00000200 /* */ 410633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_RX_FULL 0x00000400 /* */ 411633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_RX_HIGH 0x00000800 /* */ 412633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_RX_TIMER 0x00001000 /* */ 413633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_DELTA_DCD 0x00002000 /* */ 414633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_DELTA_CTS 0x00004000 /* */ 415633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_INT 0x00008000 /* */ 416633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_TX_EXPLICIT 0x00010000 /* */ 417633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB_MEMERR 0x00020000 /* */ 418633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */ 419633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */ 420633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */ 421633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */ 422633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */ 423633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */ 424633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */ 425633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_GEN_INT_SHIFT 28 426633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 427633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* per device interrupt masks */ 428633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SA (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \ 429633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \ 430633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \ 431633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \ 432633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_SA_MEMERR) 433633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_SB (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \ 434633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \ 435633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \ 436633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \ 437633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_SB_MEMERR) 438633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \ 439633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham SIO_IR_PP_INTB | SIO_IR_PP_MEMERR) 440633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1) 441633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 442633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* macro to load pending interrupts */ 443633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \ 444633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham PCI_INW(&((mem)->sio_ies_ro))) 445633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 446633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for SIO_CR */ 447633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_SIO_RESET 0x00000001 /* reset the SIO */ 448633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_SER_A_BASE 0x000000fe /* DMA poll addr port A */ 449633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_SER_A_BASE_SHIFT 1 450633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_SER_B_BASE 0x00007f00 /* DMA poll addr port B */ 451633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_SER_B_BASE_SHIFT 8 452633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_SR_CMD_PULSE 0x00078000 /* byte bus strobe length */ 453633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_CMD_PULSE_SHIFT 15 454633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */ 455633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_ARB_DIAG_TXA 0x00000000 456633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_ARB_DIAG_RXA 0x00080000 457633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_ARB_DIAG_TXB 0x00100000 458633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_ARB_DIAG_RXB 0x00180000 459633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_ARB_DIAG_PP 0x00200000 460633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */ 461633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 462633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for INT_OUT */ 463633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_COUNT 0x0000ffff /* pulse interval timer */ 464633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_MODE 0x00070000 /* mode mask */ 465633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_MODE_0 0x00000000 /* set output to 0 */ 466633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_MODE_1 0x00040000 /* set output to 1 */ 467633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_MODE_1PULSE 0x00050000 /* send 1 pulse */ 468633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_MODE_PULSES 0x00060000 /* send 1 pulse every interval */ 469633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_MODE_SQW 0x00070000 /* toggle output every interval */ 470633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_DIAG 0x40000000 /* diag mode */ 471633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_INT_OUT 0x80000000 /* current state of INT_OUT */ 472633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 473633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* time constants for INT_OUT */ 474633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_NS_PER_TICK (30 * 260) /* 30 ns PCI clock, divisor=260 */ 475633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_TICKS_PER_PULSE 3 /* outgoing pulse lasts 3 ticks */ 476633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_US_TO_COUNT(x) /* convert uS to a count value */ \ 477633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham (((x) * 10 + INT_OUT_NS_PER_TICK / 200) * \ 478633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 100 / INT_OUT_NS_PER_TICK - 1) 479633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_COUNT_TO_US(x) /* convert count value to uS */ \ 480633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham (((x) + 1) * INT_OUT_NS_PER_TICK / 1000) 481633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_MIN_TICKS 3 /* min period is width of pulse in "ticks" */ 482633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define INT_OUT_MAX_TICKS INT_OUT_COUNT /* largest possible count */ 483633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 484633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* bitmasks for GPCR */ 485633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_DIR 0x000000ff /* tristate pin input or output */ 486633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_DIR_PIN(x) (1<<(x)) /* access one of the DIR bits */ 487633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_EDGE 0x000f0000 /* extint edge or level sensitive */ 488633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_EDGE_PIN(x) (1<<((x)+15)) /* access one of the EDGE bits */ 489633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 490633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* values for GPCR */ 491633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_INT_OUT_EN 0x00100000 /* enable INT_OUT to pin 0 */ 492633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_MLAN_EN 0x00200000 /* enable MCR to pin 8 */ 493633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_DIR_SERA_XCVR 0x00000080 /* Port A Transceiver select enable */ 494633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_DIR_SERB_XCVR 0x00000040 /* Port B Transceiver select enable */ 495633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_DIR_PHY_RST 0x00000020 /* ethernet PHY reset enable */ 496633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 497633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* defs for some of the generic I/O pins */ 498633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */ 499633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */ 500633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */ 501633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 502633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */ 503633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin controlling uart b mode select */ 504633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin controlling uart a mode select */ 505633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 506633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_DUPLEX 0x00000001 507633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_PROMISC 0x00000002 508633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_PADEN 0x00000004 509633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_RXOFF_MASK 0x000001f8 510633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_RXOFF_SHIFT 3 511633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_RAMPAR 0x00000200 512633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_BADPAR 0x00000800 513633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_BUFSIZ 0x00001000 514633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_TXDMAEN 0x00002000 515633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_TXEN 0x00004000 516633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_RXDMAEN 0x00008000 517633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_RXEN 0x00010000 518633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_LOOPBACK 0x00020000 519633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_ARB_DIAG 0x001c0000 520633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_ARB_DIAG_IDLE 0x00200000 521633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EMCR_RST 0x80000000 522633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 523633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_RXTIMERINT 0x00000001 524633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_RXTHRESHINT 0x00000002 525633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_RXOFLO 0x00000004 526633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_RXBUFOFLO 0x00000008 527633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_RXMEMERR 0x00000010 528633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_RXPARERR 0x00000020 529633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXEMPTY 0x00010000 530633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXRTRY 0x00020000 531633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXEXDEF 0x00040000 532633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXLCOL 0x00080000 533633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXGIANT 0x00100000 534633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXBUFUFLO 0x00200000 535633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXEXPLICIT 0x00400000 536633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXCOLLWRAP 0x00800000 537633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXDEFERWRAP 0x01000000 538633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXMEMERR 0x02000000 539633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EISR_TXPARERR 0x04000000 540633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 541633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERCSR_THRESH_MASK 0x000001ff /* enet RX threshold */ 542633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERCSR_RX_TMR 0x40000000 /* simulation only */ 543633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERCSR_DIAG_OFLO 0x80000000 /* simulation only */ 544633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 545633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERBR_ALIGNMENT 4096 546633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERBR_L_RXRINGBASE_MASK 0xfffff000 547633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 548633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERBAR_BARRIER_BIT 0x0100 549633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERBAR_RXBARR_MASK 0xffff0000 550633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERBAR_RXBARR_SHIFT 16 551633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 552633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERCIR_RXCONSUME_MASK 0x00000fff 553633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 554633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERPIR_RXPRODUCE_MASK 0x00000fff 555633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERPIR_ARM 0x80000000 556633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 557633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERTR_CNT_MASK 0x000007ff 558633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 559633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCSR_IPGT_MASK 0x0000007f 560633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCSR_IPGR1_MASK 0x00007f00 561633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCSR_IPGR1_SHIFT 8 562633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCSR_IPGR2_MASK 0x007f0000 563633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCSR_IPGR2_SHIFT 16 564633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCSR_NOTXCLK 0x80000000 565633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 566633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCDC_COLLCNT_MASK 0x0000ffff 567633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCDC_DEFERCNT_MASK 0xffff0000 568633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCDC_DEFERCNT_SHIFT 16 569633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 570633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETBR_ALIGNMENT (64*1024) 571633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETBR_L_RINGSZ_MASK 0x00000001 572633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETBR_L_RINGSZ128 0 573633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETBR_L_RINGSZ512 1 574633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETBR_L_TXRINGBASE_MASK 0xffffc000 575633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 576633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCIR_TXCONSUME_MASK 0x0000ffff 577633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETCIR_IDLE 0x80000000 578633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 579633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETPIR_TXPRODUCE_MASK 0x0000ffff 580633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 581633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EBIR_TXBUFPROD_MASK 0x0000001f 582633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EBIR_TXBUFCONS_MASK 0x00001f00 583633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EBIR_TXBUFCONS_SHIFT 8 584633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EBIR_RXBUFPROD_MASK 0x007fc000 585633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EBIR_RXBUFPROD_SHIFT 14 586633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EBIR_RXBUFCONS_MASK 0xff800000 587633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define EBIR_RXBUFCONS_SHIFT 23 588633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 589633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MICR_REGADDR_MASK 0x0000001f 590633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MICR_PHYADDR_MASK 0x000003e0 591633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MICR_PHYADDR_SHIFT 5 592633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MICR_READTRIG 0x00000400 593633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MICR_BUSY 0x00000800 594633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 595633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define MIDR_DATA_MASK 0x0000ffff 596633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 597633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_IPCKSUM_MASK 0x0000ffff 598633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_BYTECNT_MASK 0x07ff0000 599633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_BYTECNT_SHIFT 16 600633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_V 0x80000000 601633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 602633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_CRCERR 0x00000001 /* aka RSV15 */ 603633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_FRAMERR 0x00000002 /* aka RSV14 */ 604633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_CODERR 0x00000004 /* aka RSV13 */ 605633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_INVPREAMB 0x00000008 /* aka RSV18 */ 606633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_LOLEN 0x00007000 /* aka RSV2_0 */ 607633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_HILEN 0x03ff0000 /* aka RSV12_3 */ 608633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_MULTICAST 0x04000000 /* aka RSV16 */ 609633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_BROADCAST 0x08000000 /* aka RSV17 */ 610633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_LONGEVENT 0x10000000 /* aka RSV19 */ 611633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_BADPKT 0x20000000 /* aka RSV20 */ 612633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_GOODPKT 0x40000000 /* aka RSV21 */ 613633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ERXBUF_CARRIER 0x80000000 /* aka RSV22 */ 614633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 615633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_BYTECNT_MASK 0x000007ff /* total byte count */ 616633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_INTWHENDONE 0x00001000 /* intr when done */ 617633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_D0V 0x00010000 /* data 0 valid */ 618633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B1V 0x00020000 /* buf 1 valid */ 619633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B2V 0x00040000 /* buf 2 valid */ 620633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_DOCHECKSUM 0x00080000 /* insert ip cksum */ 621633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_CHKOFF_MASK 0x07f00000 /* cksum byte offset */ 622633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_CHKOFF_SHIFT 20 623633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 624633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_D0CNT_MASK 0x0000007f 625633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B1CNT_MASK 0x0007ff00 626633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B1CNT_SHIFT 8 627633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B2CNT_MASK 0x7ff00000 628633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define ETXD_B2CNT_SHIFT 20 629633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 630633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandhamtypedef enum ioc3_subdevs_e { 631633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_subdev_ether, 632633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_subdev_generic, 633633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_subdev_nic, 634633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_subdev_kbms, 635633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_subdev_ttya, 636633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_subdev_ttyb, 637633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_subdev_ecpp, 638633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_subdev_rt, 639633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham ioc3_nsubdevs 640633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham} ioc3_subdev_t; 641633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 642633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham/* subdevice disable bits, 643633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham * from the standard INFO_LBL_SUBDEVS 644633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham */ 645633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_ETHER (1<<ioc3_subdev_ether) 646633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_GENERIC (1<<ioc3_subdev_generic) 647633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_NIC (1<<ioc3_subdev_nic) 648633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_KBMS (1<<ioc3_subdev_kbms) 649633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_TTYA (1<<ioc3_subdev_ttya) 650633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_TTYB (1<<ioc3_subdev_ttyb) 651633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_ECPP (1<<ioc3_subdev_ecpp) 652633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_RT (1<<ioc3_subdev_rt) 653633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 654633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_ALL_SUBDEVS ((1<<ioc3_nsubdevs)-1) 655633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 656633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_SDB_SERIAL (IOC3_SDB_TTYA|IOC3_SDB_TTYB) 657633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 658633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_STD_SUBDEVS IOC3_ALL_SUBDEVS 659633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 660633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_INTA_SUBDEVS IOC3_SDB_ETHER 661633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#define IOC3_INTB_SUBDEVS (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT) 662633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham 663633c3473533ad9f2cca069b22cc5d95cd4e3510bRaghu Gandham#endif /* _IOC3_H */ 664