InlineSpiller.cpp revision 8a06af96698537377275dd7848db69915638dd26
1//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// The inline spiller modifies the machine function directly instead of 11// inserting spills and restores in VirtRegMap. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "regalloc" 16#include "Spiller.h" 17#include "LiveRangeEdit.h" 18#include "VirtRegMap.h" 19#include "llvm/ADT/Statistic.h" 20#include "llvm/ADT/TinyPtrVector.h" 21#include "llvm/Analysis/AliasAnalysis.h" 22#include "llvm/CodeGen/LiveIntervalAnalysis.h" 23#include "llvm/CodeGen/LiveStackAnalysis.h" 24#include "llvm/CodeGen/MachineDominators.h" 25#include "llvm/CodeGen/MachineInstrBundle.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineLoopInfo.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetInstrInfo.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/raw_ostream.h" 35 36using namespace llvm; 37 38STATISTIC(NumSpilledRanges, "Number of spilled live ranges"); 39STATISTIC(NumSnippets, "Number of spilled snippets"); 40STATISTIC(NumSpills, "Number of spills inserted"); 41STATISTIC(NumSpillsRemoved, "Number of spills removed"); 42STATISTIC(NumReloads, "Number of reloads inserted"); 43STATISTIC(NumReloadsRemoved, "Number of reloads removed"); 44STATISTIC(NumFolded, "Number of folded stack accesses"); 45STATISTIC(NumFoldedLoads, "Number of folded loads"); 46STATISTIC(NumRemats, "Number of rematerialized defs for spilling"); 47STATISTIC(NumOmitReloadSpill, "Number of omitted spills of reloads"); 48STATISTIC(NumHoists, "Number of hoisted spills"); 49 50static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden, 51 cl::desc("Disable inline spill hoisting")); 52 53namespace { 54class InlineSpiller : public Spiller { 55 MachineFunctionPass &Pass; 56 MachineFunction &MF; 57 LiveIntervals &LIS; 58 LiveStacks &LSS; 59 AliasAnalysis *AA; 60 MachineDominatorTree &MDT; 61 MachineLoopInfo &Loops; 62 VirtRegMap &VRM; 63 MachineFrameInfo &MFI; 64 MachineRegisterInfo &MRI; 65 const TargetInstrInfo &TII; 66 const TargetRegisterInfo &TRI; 67 68 // Variables that are valid during spill(), but used by multiple methods. 69 LiveRangeEdit *Edit; 70 LiveInterval *StackInt; 71 int StackSlot; 72 unsigned Original; 73 74 // All registers to spill to StackSlot, including the main register. 75 SmallVector<unsigned, 8> RegsToSpill; 76 77 // All COPY instructions to/from snippets. 78 // They are ignored since both operands refer to the same stack slot. 79 SmallPtrSet<MachineInstr*, 8> SnippetCopies; 80 81 // Values that failed to remat at some point. 82 SmallPtrSet<VNInfo*, 8> UsedValues; 83 84public: 85 // Information about a value that was defined by a copy from a sibling 86 // register. 87 struct SibValueInfo { 88 // True when all reaching defs were reloads: No spill is necessary. 89 bool AllDefsAreReloads; 90 91 // True when value is defined by an original PHI not from splitting. 92 bool DefByOrigPHI; 93 94 // True when the COPY defining this value killed its source. 95 bool KillsSource; 96 97 // The preferred register to spill. 98 unsigned SpillReg; 99 100 // The value of SpillReg that should be spilled. 101 VNInfo *SpillVNI; 102 103 // The block where SpillVNI should be spilled. Currently, this must be the 104 // block containing SpillVNI->def. 105 MachineBasicBlock *SpillMBB; 106 107 // A defining instruction that is not a sibling copy or a reload, or NULL. 108 // This can be used as a template for rematerialization. 109 MachineInstr *DefMI; 110 111 // List of values that depend on this one. These values are actually the 112 // same, but live range splitting has placed them in different registers, 113 // or SSA update needed to insert PHI-defs to preserve SSA form. This is 114 // copies of the current value and phi-kills. Usually only phi-kills cause 115 // more than one dependent value. 116 TinyPtrVector<VNInfo*> Deps; 117 118 SibValueInfo(unsigned Reg, VNInfo *VNI) 119 : AllDefsAreReloads(true), DefByOrigPHI(false), KillsSource(false), 120 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} 121 122 // Returns true when a def has been found. 123 bool hasDef() const { return DefByOrigPHI || DefMI; } 124 }; 125 126private: 127 // Values in RegsToSpill defined by sibling copies. 128 typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap; 129 SibValueMap SibValues; 130 131 // Dead defs generated during spilling. 132 SmallVector<MachineInstr*, 8> DeadDefs; 133 134 ~InlineSpiller() {} 135 136public: 137 InlineSpiller(MachineFunctionPass &pass, 138 MachineFunction &mf, 139 VirtRegMap &vrm) 140 : Pass(pass), 141 MF(mf), 142 LIS(pass.getAnalysis<LiveIntervals>()), 143 LSS(pass.getAnalysis<LiveStacks>()), 144 AA(&pass.getAnalysis<AliasAnalysis>()), 145 MDT(pass.getAnalysis<MachineDominatorTree>()), 146 Loops(pass.getAnalysis<MachineLoopInfo>()), 147 VRM(vrm), 148 MFI(*mf.getFrameInfo()), 149 MRI(mf.getRegInfo()), 150 TII(*mf.getTarget().getInstrInfo()), 151 TRI(*mf.getTarget().getRegisterInfo()) {} 152 153 void spill(LiveRangeEdit &); 154 155private: 156 bool isSnippet(const LiveInterval &SnipLI); 157 void collectRegsToSpill(); 158 159 bool isRegToSpill(unsigned Reg) { 160 return std::find(RegsToSpill.begin(), 161 RegsToSpill.end(), Reg) != RegsToSpill.end(); 162 } 163 164 bool isSibling(unsigned Reg); 165 MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*); 166 void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = 0); 167 void analyzeSiblingValues(); 168 169 bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI); 170 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI); 171 172 void markValueUsed(LiveInterval*, VNInfo*); 173 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI); 174 void reMaterializeAll(); 175 176 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg); 177 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> >, 178 MachineInstr *LoadMI = 0); 179 void insertReload(LiveInterval &NewLI, SlotIndex, 180 MachineBasicBlock::iterator MI); 181 void insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI, 182 SlotIndex, MachineBasicBlock::iterator MI); 183 184 void spillAroundUses(unsigned Reg); 185 void spillAll(); 186}; 187} 188 189namespace llvm { 190Spiller *createInlineSpiller(MachineFunctionPass &pass, 191 MachineFunction &mf, 192 VirtRegMap &vrm) { 193 return new InlineSpiller(pass, mf, vrm); 194} 195} 196 197//===----------------------------------------------------------------------===// 198// Snippets 199//===----------------------------------------------------------------------===// 200 201// When spilling a virtual register, we also spill any snippets it is connected 202// to. The snippets are small live ranges that only have a single real use, 203// leftovers from live range splitting. Spilling them enables memory operand 204// folding or tightens the live range around the single use. 205// 206// This minimizes register pressure and maximizes the store-to-load distance for 207// spill slots which can be important in tight loops. 208 209/// isFullCopyOf - If MI is a COPY to or from Reg, return the other register, 210/// otherwise return 0. 211static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { 212 if (!MI->isFullCopy()) 213 return 0; 214 if (MI->getOperand(0).getReg() == Reg) 215 return MI->getOperand(1).getReg(); 216 if (MI->getOperand(1).getReg() == Reg) 217 return MI->getOperand(0).getReg(); 218 return 0; 219} 220 221/// isSnippet - Identify if a live interval is a snippet that should be spilled. 222/// It is assumed that SnipLI is a virtual register with the same original as 223/// Edit->getReg(). 224bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) { 225 unsigned Reg = Edit->getReg(); 226 227 // A snippet is a tiny live range with only a single instruction using it 228 // besides copies to/from Reg or spills/fills. We accept: 229 // 230 // %snip = COPY %Reg / FILL fi# 231 // %snip = USE %snip 232 // %Reg = COPY %snip / SPILL %snip, fi# 233 // 234 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI)) 235 return false; 236 237 MachineInstr *UseMI = 0; 238 239 // Check that all uses satisfy our criteria. 240 for (MachineRegisterInfo::reg_nodbg_iterator 241 RI = MRI.reg_nodbg_begin(SnipLI.reg); 242 MachineInstr *MI = RI.skipInstruction();) { 243 244 // Allow copies to/from Reg. 245 if (isFullCopyOf(MI, Reg)) 246 continue; 247 248 // Allow stack slot loads. 249 int FI; 250 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) 251 continue; 252 253 // Allow stack slot stores. 254 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) 255 continue; 256 257 // Allow a single additional instruction. 258 if (UseMI && MI != UseMI) 259 return false; 260 UseMI = MI; 261 } 262 return true; 263} 264 265/// collectRegsToSpill - Collect live range snippets that only have a single 266/// real use. 267void InlineSpiller::collectRegsToSpill() { 268 unsigned Reg = Edit->getReg(); 269 270 // Main register always spills. 271 RegsToSpill.assign(1, Reg); 272 SnippetCopies.clear(); 273 274 // Snippets all have the same original, so there can't be any for an original 275 // register. 276 if (Original == Reg) 277 return; 278 279 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg); 280 MachineInstr *MI = RI.skipInstruction();) { 281 unsigned SnipReg = isFullCopyOf(MI, Reg); 282 if (!isSibling(SnipReg)) 283 continue; 284 LiveInterval &SnipLI = LIS.getInterval(SnipReg); 285 if (!isSnippet(SnipLI)) 286 continue; 287 SnippetCopies.insert(MI); 288 if (isRegToSpill(SnipReg)) 289 continue; 290 RegsToSpill.push_back(SnipReg); 291 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n'); 292 ++NumSnippets; 293 } 294} 295 296 297//===----------------------------------------------------------------------===// 298// Sibling Values 299//===----------------------------------------------------------------------===// 300 301// After live range splitting, some values to be spilled may be defined by 302// copies from sibling registers. We trace the sibling copies back to the 303// original value if it still exists. We need it for rematerialization. 304// 305// Even when the value can't be rematerialized, we still want to determine if 306// the value has already been spilled, or we may want to hoist the spill from a 307// loop. 308 309bool InlineSpiller::isSibling(unsigned Reg) { 310 return TargetRegisterInfo::isVirtualRegister(Reg) && 311 VRM.getOriginal(Reg) == Original; 312} 313 314#ifndef NDEBUG 315static raw_ostream &operator<<(raw_ostream &OS, 316 const InlineSpiller::SibValueInfo &SVI) { 317 OS << "spill " << PrintReg(SVI.SpillReg) << ':' 318 << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def; 319 if (SVI.SpillMBB) 320 OS << " in BB#" << SVI.SpillMBB->getNumber(); 321 if (SVI.AllDefsAreReloads) 322 OS << " all-reloads"; 323 if (SVI.DefByOrigPHI) 324 OS << " orig-phi"; 325 if (SVI.KillsSource) 326 OS << " kill"; 327 OS << " deps["; 328 for (unsigned i = 0, e = SVI.Deps.size(); i != e; ++i) 329 OS << ' ' << SVI.Deps[i]->id << '@' << SVI.Deps[i]->def; 330 OS << " ]"; 331 if (SVI.DefMI) 332 OS << " def: " << *SVI.DefMI; 333 else 334 OS << '\n'; 335 return OS; 336} 337#endif 338 339/// propagateSiblingValue - Propagate the value in SVI to dependents if it is 340/// known. Otherwise remember the dependency for later. 341/// 342/// @param SVI SibValues entry to propagate. 343/// @param VNI Dependent value, or NULL to propagate to all saved dependents. 344void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVI, 345 VNInfo *VNI) { 346 // When VNI is non-NULL, add it to SVI's deps, and only propagate to that. 347 TinyPtrVector<VNInfo*> FirstDeps; 348 if (VNI) { 349 FirstDeps.push_back(VNI); 350 SVI->second.Deps.push_back(VNI); 351 } 352 353 // Has the value been completely determined yet? If not, defer propagation. 354 if (!SVI->second.hasDef()) 355 return; 356 357 // Work list of values to propagate. It would be nice to use a SetVector 358 // here, but then we would be forced to use a SmallSet. 359 SmallVector<SibValueMap::iterator, 8> WorkList(1, SVI); 360 SmallPtrSet<VNInfo*, 8> WorkSet; 361 362 do { 363 SVI = WorkList.pop_back_val(); 364 WorkSet.erase(SVI->first); 365 TinyPtrVector<VNInfo*> *Deps = VNI ? &FirstDeps : &SVI->second.Deps; 366 VNI = 0; 367 368 SibValueInfo &SV = SVI->second; 369 if (!SV.SpillMBB) 370 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def); 371 372 DEBUG(dbgs() << " prop to " << Deps->size() << ": " 373 << SVI->first->id << '@' << SVI->first->def << ":\t" << SV); 374 375 assert(SV.hasDef() && "Propagating undefined value"); 376 377 // Should this value be propagated as a preferred spill candidate? We don't 378 // propagate values of registers that are about to spill. 379 bool PropSpill = !DisableHoisting && !isRegToSpill(SV.SpillReg); 380 unsigned SpillDepth = ~0u; 381 382 for (TinyPtrVector<VNInfo*>::iterator DepI = Deps->begin(), 383 DepE = Deps->end(); DepI != DepE; ++DepI) { 384 SibValueMap::iterator DepSVI = SibValues.find(*DepI); 385 assert(DepSVI != SibValues.end() && "Dependent value not in SibValues"); 386 SibValueInfo &DepSV = DepSVI->second; 387 if (!DepSV.SpillMBB) 388 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def); 389 390 bool Changed = false; 391 392 // Propagate defining instruction. 393 if (!DepSV.hasDef()) { 394 Changed = true; 395 DepSV.DefMI = SV.DefMI; 396 DepSV.DefByOrigPHI = SV.DefByOrigPHI; 397 } 398 399 // Propagate AllDefsAreReloads. For PHI values, this computes an AND of 400 // all predecessors. 401 if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) { 402 Changed = true; 403 DepSV.AllDefsAreReloads = false; 404 } 405 406 // Propagate best spill value. 407 if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) { 408 if (SV.SpillMBB == DepSV.SpillMBB) { 409 // DepSV is in the same block. Hoist when dominated. 410 if (DepSV.KillsSource && SV.SpillVNI->def < DepSV.SpillVNI->def) { 411 // This is an alternative def earlier in the same MBB. 412 // Hoist the spill as far as possible in SpillMBB. This can ease 413 // register pressure: 414 // 415 // x = def 416 // y = use x 417 // s = copy x 418 // 419 // Hoisting the spill of s to immediately after the def removes the 420 // interference between x and y: 421 // 422 // x = def 423 // spill x 424 // y = use x<kill> 425 // 426 // This hoist only helps when the DepSV copy kills its source. 427 Changed = true; 428 DepSV.SpillReg = SV.SpillReg; 429 DepSV.SpillVNI = SV.SpillVNI; 430 DepSV.SpillMBB = SV.SpillMBB; 431 } 432 } else { 433 // DepSV is in a different block. 434 if (SpillDepth == ~0u) 435 SpillDepth = Loops.getLoopDepth(SV.SpillMBB); 436 437 // Also hoist spills to blocks with smaller loop depth, but make sure 438 // that the new value dominates. Non-phi dependents are always 439 // dominated, phis need checking. 440 if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) && 441 (!DepSVI->first->isPHIDef() || 442 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) { 443 Changed = true; 444 DepSV.SpillReg = SV.SpillReg; 445 DepSV.SpillVNI = SV.SpillVNI; 446 DepSV.SpillMBB = SV.SpillMBB; 447 } 448 } 449 } 450 451 if (!Changed) 452 continue; 453 454 // Something changed in DepSVI. Propagate to dependents. 455 if (WorkSet.insert(DepSVI->first)) 456 WorkList.push_back(DepSVI); 457 458 DEBUG(dbgs() << " update " << DepSVI->first->id << '@' 459 << DepSVI->first->def << " to:\t" << DepSV); 460 } 461 } while (!WorkList.empty()); 462} 463 464/// traceSiblingValue - Trace a value that is about to be spilled back to the 465/// real defining instructions by looking through sibling copies. Always stay 466/// within the range of OrigVNI so the registers are known to carry the same 467/// value. 468/// 469/// Determine if the value is defined by all reloads, so spilling isn't 470/// necessary - the value is already in the stack slot. 471/// 472/// Return a defining instruction that may be a candidate for rematerialization. 473/// 474MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI, 475 VNInfo *OrigVNI) { 476 // Check if a cached value already exists. 477 SibValueMap::iterator SVI; 478 bool Inserted; 479 tie(SVI, Inserted) = 480 SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI))); 481 if (!Inserted) { 482 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':' 483 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second); 484 return SVI->second.DefMI; 485 } 486 487 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':' 488 << UseVNI->id << '@' << UseVNI->def << '\n'); 489 490 // List of (Reg, VNI) that have been inserted into SibValues, but need to be 491 // processed. 492 SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList; 493 WorkList.push_back(std::make_pair(UseReg, UseVNI)); 494 495 do { 496 unsigned Reg; 497 VNInfo *VNI; 498 tie(Reg, VNI) = WorkList.pop_back_val(); 499 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def 500 << ":\t"); 501 502 // First check if this value has already been computed. 503 SVI = SibValues.find(VNI); 504 assert(SVI != SibValues.end() && "Missing SibValues entry"); 505 506 // Trace through PHI-defs created by live range splitting. 507 if (VNI->isPHIDef()) { 508 // Stop at original PHIs. We don't know the value at the predecessors. 509 if (VNI->def == OrigVNI->def) { 510 DEBUG(dbgs() << "orig phi value\n"); 511 SVI->second.DefByOrigPHI = true; 512 SVI->second.AllDefsAreReloads = false; 513 propagateSiblingValue(SVI); 514 continue; 515 } 516 517 // This is a PHI inserted by live range splitting. We could trace the 518 // live-out value from predecessor blocks, but that search can be very 519 // expensive if there are many predecessors and many more PHIs as 520 // generated by tail-dup when it sees an indirectbr. Instead, look at 521 // all the non-PHI defs that have the same value as OrigVNI. They must 522 // jointly dominate VNI->def. This is not optimal since VNI may actually 523 // be jointly dominated by a smaller subset of defs, so there is a change 524 // we will miss a AllDefsAreReloads optimization. 525 526 // Separate all values dominated by OrigVNI into PHIs and non-PHIs. 527 SmallVector<VNInfo*, 8> PHIs, NonPHIs; 528 LiveInterval &LI = LIS.getInterval(Reg); 529 LiveInterval &OrigLI = LIS.getInterval(Original); 530 531 for (LiveInterval::vni_iterator VI = LI.vni_begin(), VE = LI.vni_end(); 532 VI != VE; ++VI) { 533 VNInfo *VNI2 = *VI; 534 if (VNI2->isUnused()) 535 continue; 536 if (!OrigLI.containsOneValue() && 537 OrigLI.getVNInfoAt(VNI2->def) != OrigVNI) 538 continue; 539 if (VNI2->isPHIDef() && VNI2->def != OrigVNI->def) 540 PHIs.push_back(VNI2); 541 else 542 NonPHIs.push_back(VNI2); 543 } 544 DEBUG(dbgs() << "split phi value, checking " << PHIs.size() 545 << " phi-defs, and " << NonPHIs.size() 546 << " non-phi/orig defs\n"); 547 548 // Create entries for all the PHIs. Don't add them to the worklist, we 549 // are processing all of them in one go here. 550 for (unsigned i = 0, e = PHIs.size(); i != e; ++i) 551 SibValues.insert(std::make_pair(PHIs[i], SibValueInfo(Reg, PHIs[i]))); 552 553 // Add every PHI as a dependent of all the non-PHIs. 554 for (unsigned i = 0, e = NonPHIs.size(); i != e; ++i) { 555 VNInfo *NonPHI = NonPHIs[i]; 556 // Known value? Try an insertion. 557 tie(SVI, Inserted) = 558 SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI))); 559 // Add all the PHIs as dependents of NonPHI. 560 for (unsigned pi = 0, pe = PHIs.size(); pi != pe; ++pi) 561 SVI->second.Deps.push_back(PHIs[pi]); 562 // This is the first time we see NonPHI, add it to the worklist. 563 if (Inserted) 564 WorkList.push_back(std::make_pair(Reg, NonPHI)); 565 else 566 // Propagate to all inserted PHIs, not just VNI. 567 propagateSiblingValue(SVI); 568 } 569 570 // Next work list item. 571 continue; 572 } 573 574 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); 575 assert(MI && "Missing def"); 576 577 // Trace through sibling copies. 578 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) { 579 if (isSibling(SrcReg)) { 580 LiveInterval &SrcLI = LIS.getInterval(SrcReg); 581 LiveRange *SrcLR = SrcLI.getLiveRangeContaining(VNI->def.getRegSlot(true)); 582 assert(SrcLR && "Copy from non-existing value"); 583 // Check if this COPY kills its source. 584 SVI->second.KillsSource = (SrcLR->end == VNI->def); 585 VNInfo *SrcVNI = SrcLR->valno; 586 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':' 587 << SrcVNI->id << '@' << SrcVNI->def 588 << " kill=" << unsigned(SVI->second.KillsSource) << '\n'); 589 // Known sibling source value? Try an insertion. 590 tie(SVI, Inserted) = SibValues.insert(std::make_pair(SrcVNI, 591 SibValueInfo(SrcReg, SrcVNI))); 592 // This is the first time we see Src, add it to the worklist. 593 if (Inserted) 594 WorkList.push_back(std::make_pair(SrcReg, SrcVNI)); 595 propagateSiblingValue(SVI, VNI); 596 // Next work list item. 597 continue; 598 } 599 } 600 601 // Track reachable reloads. 602 SVI->second.DefMI = MI; 603 SVI->second.SpillMBB = MI->getParent(); 604 int FI; 605 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) { 606 DEBUG(dbgs() << "reload\n"); 607 propagateSiblingValue(SVI); 608 // Next work list item. 609 continue; 610 } 611 612 // Potential remat candidate. 613 DEBUG(dbgs() << "def " << *MI); 614 SVI->second.AllDefsAreReloads = false; 615 propagateSiblingValue(SVI); 616 } while (!WorkList.empty()); 617 618 // Look up the value we were looking for. We already did this lokup at the 619 // top of the function, but SibValues may have been invalidated. 620 SVI = SibValues.find(UseVNI); 621 assert(SVI != SibValues.end() && "Didn't compute requested info"); 622 DEBUG(dbgs() << " traced to:\t" << SVI->second); 623 return SVI->second.DefMI; 624} 625 626/// analyzeSiblingValues - Trace values defined by sibling copies back to 627/// something that isn't a sibling copy. 628/// 629/// Keep track of values that may be rematerializable. 630void InlineSpiller::analyzeSiblingValues() { 631 SibValues.clear(); 632 633 // No siblings at all? 634 if (Edit->getReg() == Original) 635 return; 636 637 LiveInterval &OrigLI = LIS.getInterval(Original); 638 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) { 639 unsigned Reg = RegsToSpill[i]; 640 LiveInterval &LI = LIS.getInterval(Reg); 641 for (LiveInterval::const_vni_iterator VI = LI.vni_begin(), 642 VE = LI.vni_end(); VI != VE; ++VI) { 643 VNInfo *VNI = *VI; 644 if (VNI->isUnused()) 645 continue; 646 MachineInstr *DefMI = 0; 647 if (!VNI->isPHIDef()) { 648 DefMI = LIS.getInstructionFromIndex(VNI->def); 649 assert(DefMI && "No defining instruction"); 650 } 651 // Check possible sibling copies. 652 if (VNI->isPHIDef() || DefMI->isCopy()) { 653 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def); 654 assert(OrigVNI && "Def outside original live range"); 655 if (OrigVNI->def != VNI->def) 656 DefMI = traceSiblingValue(Reg, VNI, OrigVNI); 657 } 658 if (DefMI && Edit->checkRematerializable(VNI, DefMI, AA)) { 659 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@' 660 << VNI->def << " may remat from " << *DefMI); 661 } 662 } 663 } 664} 665 666/// hoistSpill - Given a sibling copy that defines a value to be spilled, insert 667/// a spill at a better location. 668bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) { 669 SlotIndex Idx = LIS.getInstructionIndex(CopyMI); 670 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot()); 671 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy"); 672 SibValueMap::iterator I = SibValues.find(VNI); 673 if (I == SibValues.end()) 674 return false; 675 676 const SibValueInfo &SVI = I->second; 677 678 // Let the normal folding code deal with the boring case. 679 if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI) 680 return false; 681 682 // SpillReg may have been deleted by remat and DCE. 683 if (!LIS.hasInterval(SVI.SpillReg)) { 684 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n'); 685 SibValues.erase(I); 686 return false; 687 } 688 689 LiveInterval &SibLI = LIS.getInterval(SVI.SpillReg); 690 if (!SibLI.containsValue(SVI.SpillVNI)) { 691 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n'); 692 SibValues.erase(I); 693 return false; 694 } 695 696 // Conservatively extend the stack slot range to the range of the original 697 // value. We may be able to do better with stack slot coloring by being more 698 // careful here. 699 assert(StackInt && "No stack slot assigned yet."); 700 LiveInterval &OrigLI = LIS.getInterval(Original); 701 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx); 702 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0)); 703 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": " 704 << *StackInt << '\n'); 705 706 // Already spilled everywhere. 707 if (SVI.AllDefsAreReloads) { 708 DEBUG(dbgs() << "\tno spill needed: " << SVI); 709 ++NumOmitReloadSpill; 710 return true; 711 } 712 // We are going to spill SVI.SpillVNI immediately after its def, so clear out 713 // any later spills of the same value. 714 eliminateRedundantSpills(SibLI, SVI.SpillVNI); 715 716 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def); 717 MachineBasicBlock::iterator MII; 718 if (SVI.SpillVNI->isPHIDef()) 719 MII = MBB->SkipPHIsAndLabels(MBB->begin()); 720 else { 721 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def); 722 assert(DefMI && "Defining instruction disappeared"); 723 MII = DefMI; 724 ++MII; 725 } 726 // Insert spill without kill flag immediately after def. 727 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot, 728 MRI.getRegClass(SVI.SpillReg), &TRI); 729 --MII; // Point to store instruction. 730 LIS.InsertMachineInstrInMaps(MII); 731 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII); 732 733 ++NumSpills; 734 ++NumHoists; 735 return true; 736} 737 738/// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any 739/// redundant spills of this value in SLI.reg and sibling copies. 740void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) { 741 assert(VNI && "Missing value"); 742 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList; 743 WorkList.push_back(std::make_pair(&SLI, VNI)); 744 assert(StackInt && "No stack slot assigned yet."); 745 746 do { 747 LiveInterval *LI; 748 tie(LI, VNI) = WorkList.pop_back_val(); 749 unsigned Reg = LI->reg; 750 DEBUG(dbgs() << "Checking redundant spills for " 751 << VNI->id << '@' << VNI->def << " in " << *LI << '\n'); 752 753 // Regs to spill are taken care of. 754 if (isRegToSpill(Reg)) 755 continue; 756 757 // Add all of VNI's live range to StackInt. 758 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0)); 759 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n'); 760 761 // Find all spills and copies of VNI. 762 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg); 763 MachineInstr *MI = UI.skipInstruction();) { 764 if (!MI->isCopy() && !MI->mayStore()) 765 continue; 766 SlotIndex Idx = LIS.getInstructionIndex(MI); 767 if (LI->getVNInfoAt(Idx) != VNI) 768 continue; 769 770 // Follow sibling copies down the dominator tree. 771 if (unsigned DstReg = isFullCopyOf(MI, Reg)) { 772 if (isSibling(DstReg)) { 773 LiveInterval &DstLI = LIS.getInterval(DstReg); 774 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot()); 775 assert(DstVNI && "Missing defined value"); 776 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot"); 777 WorkList.push_back(std::make_pair(&DstLI, DstVNI)); 778 } 779 continue; 780 } 781 782 // Erase spills. 783 int FI; 784 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) { 785 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI); 786 // eliminateDeadDefs won't normally remove stores, so switch opcode. 787 MI->setDesc(TII.get(TargetOpcode::KILL)); 788 DeadDefs.push_back(MI); 789 ++NumSpillsRemoved; 790 --NumSpills; 791 } 792 } 793 } while (!WorkList.empty()); 794} 795 796 797//===----------------------------------------------------------------------===// 798// Rematerialization 799//===----------------------------------------------------------------------===// 800 801/// markValueUsed - Remember that VNI failed to rematerialize, so its defining 802/// instruction cannot be eliminated. See through snippet copies 803void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) { 804 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList; 805 WorkList.push_back(std::make_pair(LI, VNI)); 806 do { 807 tie(LI, VNI) = WorkList.pop_back_val(); 808 if (!UsedValues.insert(VNI)) 809 continue; 810 811 if (VNI->isPHIDef()) { 812 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def); 813 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), 814 PE = MBB->pred_end(); PI != PE; ++PI) { 815 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(*PI)); 816 if (PVNI) 817 WorkList.push_back(std::make_pair(LI, PVNI)); 818 } 819 continue; 820 } 821 822 // Follow snippet copies. 823 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); 824 if (!SnippetCopies.count(MI)) 825 continue; 826 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg()); 827 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy"); 828 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true)); 829 assert(SnipVNI && "Snippet undefined before copy"); 830 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI)); 831 } while (!WorkList.empty()); 832} 833 834/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading. 835bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, 836 MachineBasicBlock::iterator MI) { 837 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); 838 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); 839 840 if (!ParentVNI) { 841 DEBUG(dbgs() << "\tadding <undef> flags: "); 842 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 843 MachineOperand &MO = MI->getOperand(i); 844 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) 845 MO.setIsUndef(); 846 } 847 DEBUG(dbgs() << UseIdx << '\t' << *MI); 848 return true; 849 } 850 851 if (SnippetCopies.count(MI)) 852 return false; 853 854 // Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy. 855 LiveRangeEdit::Remat RM(ParentVNI); 856 SibValueMap::const_iterator SibI = SibValues.find(ParentVNI); 857 if (SibI != SibValues.end()) 858 RM.OrigMI = SibI->second.DefMI; 859 if (!Edit->canRematerializeAt(RM, UseIdx, false)) { 860 markValueUsed(&VirtReg, ParentVNI); 861 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI); 862 return false; 863 } 864 865 // If the instruction also writes VirtReg.reg, it had better not require the 866 // same register for uses and defs. 867 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops; 868 MIBundleOperands::RegInfo RI = 869 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops); 870 if (RI.Tied) { 871 markValueUsed(&VirtReg, ParentVNI); 872 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI); 873 return false; 874 } 875 876 // Before rematerializing into a register for a single instruction, try to 877 // fold a load into the instruction. That avoids allocating a new register. 878 if (RM.OrigMI->canFoldAsLoad() && 879 foldMemoryOperand(Ops, RM.OrigMI)) { 880 Edit->markRematerialized(RM.ParentVNI); 881 ++NumFoldedLoads; 882 return true; 883 } 884 885 // Alocate a new register for the remat. 886 LiveInterval &NewLI = Edit->createFrom(Original); 887 NewLI.markNotSpillable(); 888 889 // Finally we can rematerialize OrigMI before MI. 890 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM, 891 TRI); 892 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' 893 << *LIS.getInstructionFromIndex(DefIdx)); 894 895 // Replace operands 896 for (unsigned i = 0, e = Ops.size(); i != e; ++i) { 897 MachineOperand &MO = MI->getOperand(Ops[i].second); 898 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { 899 MO.setReg(NewLI.reg); 900 MO.setIsKill(); 901 } 902 } 903 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI); 904 905 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, LIS.getVNInfoAllocator()); 906 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI)); 907 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n'); 908 ++NumRemats; 909 return true; 910} 911 912/// reMaterializeAll - Try to rematerialize as many uses as possible, 913/// and trim the live ranges after. 914void InlineSpiller::reMaterializeAll() { 915 // analyzeSiblingValues has already tested all relevant defining instructions. 916 if (!Edit->anyRematerializable(AA)) 917 return; 918 919 UsedValues.clear(); 920 921 // Try to remat before all uses of snippets. 922 bool anyRemat = false; 923 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) { 924 unsigned Reg = RegsToSpill[i]; 925 LiveInterval &LI = LIS.getInterval(Reg); 926 for (MachineRegisterInfo::use_nodbg_iterator 927 RI = MRI.use_nodbg_begin(Reg); 928 MachineInstr *MI = RI.skipBundle();) 929 anyRemat |= reMaterializeFor(LI, MI); 930 } 931 if (!anyRemat) 932 return; 933 934 // Remove any values that were completely rematted. 935 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) { 936 unsigned Reg = RegsToSpill[i]; 937 LiveInterval &LI = LIS.getInterval(Reg); 938 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end(); 939 I != E; ++I) { 940 VNInfo *VNI = *I; 941 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI)) 942 continue; 943 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); 944 MI->addRegisterDead(Reg, &TRI); 945 if (!MI->allDefsAreDead()) 946 continue; 947 DEBUG(dbgs() << "All defs dead: " << *MI); 948 DeadDefs.push_back(MI); 949 } 950 } 951 952 // Eliminate dead code after remat. Note that some snippet copies may be 953 // deleted here. 954 if (DeadDefs.empty()) 955 return; 956 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n"); 957 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill); 958 959 // Get rid of deleted and empty intervals. 960 for (unsigned i = RegsToSpill.size(); i != 0; --i) { 961 unsigned Reg = RegsToSpill[i-1]; 962 if (!LIS.hasInterval(Reg)) { 963 RegsToSpill.erase(RegsToSpill.begin() + (i - 1)); 964 continue; 965 } 966 LiveInterval &LI = LIS.getInterval(Reg); 967 if (!LI.empty()) 968 continue; 969 Edit->eraseVirtReg(Reg); 970 RegsToSpill.erase(RegsToSpill.begin() + (i - 1)); 971 } 972 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n"); 973} 974 975 976//===----------------------------------------------------------------------===// 977// Spilling 978//===----------------------------------------------------------------------===// 979 980/// If MI is a load or store of StackSlot, it can be removed. 981bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) { 982 int FI = 0; 983 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI); 984 bool IsLoad = InstrReg; 985 if (!IsLoad) 986 InstrReg = TII.isStoreToStackSlot(MI, FI); 987 988 // We have a stack access. Is it the right register and slot? 989 if (InstrReg != Reg || FI != StackSlot) 990 return false; 991 992 DEBUG(dbgs() << "Coalescing stack access: " << *MI); 993 LIS.RemoveMachineInstrFromMaps(MI); 994 MI->eraseFromParent(); 995 996 if (IsLoad) { 997 ++NumReloadsRemoved; 998 --NumReloads; 999 } else { 1000 ++NumSpillsRemoved; 1001 --NumSpills; 1002 } 1003 1004 return true; 1005} 1006 1007/// foldMemoryOperand - Try folding stack slot references in Ops into their 1008/// instructions. 1009/// 1010/// @param Ops Operand indices from analyzeVirtReg(). 1011/// @param LoadMI Load instruction to use instead of stack slot when non-null. 1012/// @return True on success. 1013bool InlineSpiller:: 1014foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops, 1015 MachineInstr *LoadMI) { 1016 if (Ops.empty()) 1017 return false; 1018 // Don't attempt folding in bundles. 1019 MachineInstr *MI = Ops.front().first; 1020 if (Ops.back().first != MI || MI->isBundled()) 1021 return false; 1022 1023 bool WasCopy = MI->isCopy(); 1024 unsigned ImpReg = 0; 1025 1026 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied 1027 // operands. 1028 SmallVector<unsigned, 8> FoldOps; 1029 for (unsigned i = 0, e = Ops.size(); i != e; ++i) { 1030 unsigned Idx = Ops[i].second; 1031 MachineOperand &MO = MI->getOperand(Idx); 1032 if (MO.isImplicit()) { 1033 ImpReg = MO.getReg(); 1034 continue; 1035 } 1036 // FIXME: Teach targets to deal with subregs. 1037 if (MO.getSubReg()) 1038 return false; 1039 // We cannot fold a load instruction into a def. 1040 if (LoadMI && MO.isDef()) 1041 return false; 1042 // Tied use operands should not be passed to foldMemoryOperand. 1043 if (!MI->isRegTiedToDefOperand(Idx)) 1044 FoldOps.push_back(Idx); 1045 } 1046 1047 MachineInstr *FoldMI = 1048 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI) 1049 : TII.foldMemoryOperand(MI, FoldOps, StackSlot); 1050 if (!FoldMI) 1051 return false; 1052 LIS.ReplaceMachineInstrInMaps(MI, FoldMI); 1053 MI->eraseFromParent(); 1054 1055 // TII.foldMemoryOperand may have left some implicit operands on the 1056 // instruction. Strip them. 1057 if (ImpReg) 1058 for (unsigned i = FoldMI->getNumOperands(); i; --i) { 1059 MachineOperand &MO = FoldMI->getOperand(i - 1); 1060 if (!MO.isReg() || !MO.isImplicit()) 1061 break; 1062 if (MO.getReg() == ImpReg) 1063 FoldMI->RemoveOperand(i - 1); 1064 } 1065 1066 DEBUG(dbgs() << "\tfolded: " << LIS.getInstructionIndex(FoldMI) << '\t' 1067 << *FoldMI); 1068 if (!WasCopy) 1069 ++NumFolded; 1070 else if (Ops.front().second == 0) 1071 ++NumSpills; 1072 else 1073 ++NumReloads; 1074 return true; 1075} 1076 1077/// insertReload - Insert a reload of NewLI.reg before MI. 1078void InlineSpiller::insertReload(LiveInterval &NewLI, 1079 SlotIndex Idx, 1080 MachineBasicBlock::iterator MI) { 1081 MachineBasicBlock &MBB = *MI->getParent(); 1082 TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot, 1083 MRI.getRegClass(NewLI.reg), &TRI); 1084 --MI; // Point to load instruction. 1085 SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getRegSlot(); 1086 DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI); 1087 VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, LIS.getVNInfoAllocator()); 1088 NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI)); 1089 ++NumReloads; 1090} 1091 1092/// insertSpill - Insert a spill of NewLI.reg after MI. 1093void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI, 1094 SlotIndex Idx, MachineBasicBlock::iterator MI) { 1095 MachineBasicBlock &MBB = *MI->getParent(); 1096 TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot, 1097 MRI.getRegClass(NewLI.reg), &TRI); 1098 --MI; // Point to store instruction. 1099 SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getRegSlot(); 1100 DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI); 1101 VNInfo *StoreVNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator()); 1102 NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI)); 1103 ++NumSpills; 1104} 1105 1106/// spillAroundUses - insert spill code around each use of Reg. 1107void InlineSpiller::spillAroundUses(unsigned Reg) { 1108 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n'); 1109 LiveInterval &OldLI = LIS.getInterval(Reg); 1110 1111 // Iterate over instructions using Reg. 1112 for (MachineRegisterInfo::reg_iterator RegI = MRI.reg_begin(Reg); 1113 MachineInstr *MI = RegI.skipBundle();) { 1114 1115 // Debug values are not allowed to affect codegen. 1116 if (MI->isDebugValue()) { 1117 // Modify DBG_VALUE now that the value is in a spill slot. 1118 uint64_t Offset = MI->getOperand(1).getImm(); 1119 const MDNode *MDPtr = MI->getOperand(2).getMetadata(); 1120 DebugLoc DL = MI->getDebugLoc(); 1121 if (MachineInstr *NewDV = TII.emitFrameIndexDebugValue(MF, StackSlot, 1122 Offset, MDPtr, DL)) { 1123 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI); 1124 MachineBasicBlock *MBB = MI->getParent(); 1125 MBB->insert(MBB->erase(MI), NewDV); 1126 } else { 1127 DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI); 1128 MI->eraseFromParent(); 1129 } 1130 continue; 1131 } 1132 1133 // Ignore copies to/from snippets. We'll delete them. 1134 if (SnippetCopies.count(MI)) 1135 continue; 1136 1137 // Stack slot accesses may coalesce away. 1138 if (coalesceStackAccess(MI, Reg)) 1139 continue; 1140 1141 // Analyze instruction. 1142 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops; 1143 MIBundleOperands::RegInfo RI = 1144 MIBundleOperands(MI).analyzeVirtReg(Reg, &Ops); 1145 1146 // Find the slot index where this instruction reads and writes OldLI. 1147 // This is usually the def slot, except for tied early clobbers. 1148 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot(); 1149 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true))) 1150 if (SlotIndex::isSameInstr(Idx, VNI->def)) 1151 Idx = VNI->def; 1152 1153 // Check for a sibling copy. 1154 unsigned SibReg = isFullCopyOf(MI, Reg); 1155 if (SibReg && isSibling(SibReg)) { 1156 // This may actually be a copy between snippets. 1157 if (isRegToSpill(SibReg)) { 1158 DEBUG(dbgs() << "Found new snippet copy: " << *MI); 1159 SnippetCopies.insert(MI); 1160 continue; 1161 } 1162 if (RI.Writes) { 1163 // Hoist the spill of a sib-reg copy. 1164 if (hoistSpill(OldLI, MI)) { 1165 // This COPY is now dead, the value is already in the stack slot. 1166 MI->getOperand(0).setIsDead(); 1167 DeadDefs.push_back(MI); 1168 continue; 1169 } 1170 } else { 1171 // This is a reload for a sib-reg copy. Drop spills downstream. 1172 LiveInterval &SibLI = LIS.getInterval(SibReg); 1173 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx)); 1174 // The COPY will fold to a reload below. 1175 } 1176 } 1177 1178 // Attempt to fold memory ops. 1179 if (foldMemoryOperand(Ops)) 1180 continue; 1181 1182 // Allocate interval around instruction. 1183 // FIXME: Infer regclass from instruction alone. 1184 LiveInterval &NewLI = Edit->createFrom(Reg); 1185 NewLI.markNotSpillable(); 1186 1187 if (RI.Reads) 1188 insertReload(NewLI, Idx, MI); 1189 1190 // Rewrite instruction operands. 1191 bool hasLiveDef = false; 1192 for (unsigned i = 0, e = Ops.size(); i != e; ++i) { 1193 MachineOperand &MO = Ops[i].first->getOperand(Ops[i].second); 1194 MO.setReg(NewLI.reg); 1195 if (MO.isUse()) { 1196 if (!Ops[i].first->isRegTiedToDefOperand(Ops[i].second)) 1197 MO.setIsKill(); 1198 } else { 1199 if (!MO.isDead()) 1200 hasLiveDef = true; 1201 } 1202 } 1203 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI); 1204 1205 // FIXME: Use a second vreg if instruction has no tied ops. 1206 if (RI.Writes) { 1207 if (hasLiveDef) 1208 insertSpill(NewLI, OldLI, Idx, MI); 1209 else { 1210 // This instruction defines a dead value. We don't need to spill it, 1211 // but do create a live range for the dead value. 1212 VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator()); 1213 NewLI.addRange(LiveRange(Idx, Idx.getDeadSlot(), VNI)); 1214 } 1215 } 1216 1217 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n'); 1218 } 1219} 1220 1221/// spillAll - Spill all registers remaining after rematerialization. 1222void InlineSpiller::spillAll() { 1223 // Update LiveStacks now that we are committed to spilling. 1224 if (StackSlot == VirtRegMap::NO_STACK_SLOT) { 1225 StackSlot = VRM.assignVirt2StackSlot(Original); 1226 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); 1227 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator()); 1228 } else 1229 StackInt = &LSS.getInterval(StackSlot); 1230 1231 if (Original != Edit->getReg()) 1232 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot); 1233 1234 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values"); 1235 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) 1236 StackInt->MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]), 1237 StackInt->getValNumInfo(0)); 1238 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n'); 1239 1240 // Spill around uses of all RegsToSpill. 1241 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) 1242 spillAroundUses(RegsToSpill[i]); 1243 1244 // Hoisted spills may cause dead code. 1245 if (!DeadDefs.empty()) { 1246 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n"); 1247 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill); 1248 } 1249 1250 // Finally delete the SnippetCopies. 1251 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) { 1252 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(RegsToSpill[i]); 1253 MachineInstr *MI = RI.skipInstruction();) { 1254 assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy"); 1255 // FIXME: Do this with a LiveRangeEdit callback. 1256 LIS.RemoveMachineInstrFromMaps(MI); 1257 MI->eraseFromParent(); 1258 } 1259 } 1260 1261 // Delete all spilled registers. 1262 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) 1263 Edit->eraseVirtReg(RegsToSpill[i]); 1264} 1265 1266void InlineSpiller::spill(LiveRangeEdit &edit) { 1267 ++NumSpilledRanges; 1268 Edit = &edit; 1269 assert(!TargetRegisterInfo::isStackSlot(edit.getReg()) 1270 && "Trying to spill a stack slot."); 1271 // Share a stack slot among all descendants of Original. 1272 Original = VRM.getOriginal(edit.getReg()); 1273 StackSlot = VRM.getStackSlot(Original); 1274 StackInt = 0; 1275 1276 DEBUG(dbgs() << "Inline spilling " 1277 << MRI.getRegClass(edit.getReg())->getName() 1278 << ':' << edit.getParent() << "\nFrom original " 1279 << LIS.getInterval(Original) << '\n'); 1280 assert(edit.getParent().isSpillable() && 1281 "Attempting to spill already spilled value."); 1282 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs"); 1283 1284 collectRegsToSpill(); 1285 analyzeSiblingValues(); 1286 reMaterializeAll(); 1287 1288 // Remat may handle everything. 1289 if (!RegsToSpill.empty()) 1290 spillAll(); 1291 1292 Edit->calculateRegClassAndHint(MF, Loops); 1293} 1294