PHIElimination.cpp revision 3e20475feebca3bfb29375ac7f3e5acbeb2a95c8
1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass eliminates machine instruction PHI nodes by inserting copy 11// instructions. This destroys SSA information, but is the desired input for 12// some register allocators. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "phielim" 17#include "PHIElimination.h" 18#include "llvm/BasicBlock.h" 19#include "llvm/Instructions.h" 20#include "llvm/CodeGen/LiveVariables.h" 21#include "llvm/CodeGen/Passes.h" 22#include "llvm/CodeGen/MachineFunctionPass.h" 23#include "llvm/CodeGen/MachineInstr.h" 24#include "llvm/CodeGen/MachineInstrBuilder.h" 25#include "llvm/CodeGen/MachineRegisterInfo.h" 26#include "llvm/Function.h" 27#include "llvm/Target/TargetMachine.h" 28#include "llvm/ADT/SmallPtrSet.h" 29#include "llvm/ADT/STLExtras.h" 30#include "llvm/ADT/Statistic.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Compiler.h" 33#include "llvm/Support/Debug.h" 34#include <algorithm> 35#include <map> 36using namespace llvm; 37 38STATISTIC(NumAtomic, "Number of atomic phis lowered"); 39STATISTIC(NumSplits, "Number of critical edges split on demand"); 40 41static cl::opt<bool> 42SplitEdges("split-phi-edges", 43 cl::desc("Split critical edges during phi elimination"), 44 cl::init(false), cl::Hidden); 45 46char PHIElimination::ID = 0; 47static RegisterPass<PHIElimination> 48X("phi-node-elimination", "Eliminate PHI nodes for register allocation"); 49 50const PassInfo *const llvm::PHIEliminationID = &X; 51 52void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { 53 AU.addPreserved<LiveVariables>(); 54 if (SplitEdges) { 55 AU.addRequired<LiveVariables>(); 56 } else { 57 AU.setPreservesCFG(); 58 AU.addPreservedID(MachineLoopInfoID); 59 AU.addPreservedID(MachineDominatorsID); 60 } 61 MachineFunctionPass::getAnalysisUsage(AU); 62} 63 64bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &Fn) { 65 MRI = &Fn.getRegInfo(); 66 67 PHIDefs.clear(); 68 PHIKills.clear(); 69 70 bool Changed = false; 71 72 // Split critical edges to help the coalescer 73 if (SplitEdges) 74 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 75 Changed |= SplitPHIEdges(Fn, *I); 76 77 // Populate VRegPHIUseCount 78 analyzePHINodes(Fn); 79 80 // Eliminate PHI instructions by inserting copies into predecessor blocks. 81 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 82 Changed |= EliminatePHINodes(Fn, *I); 83 84 // Remove dead IMPLICIT_DEF instructions. 85 for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(), 86 E = ImpDefs.end(); I != E; ++I) { 87 MachineInstr *DefMI = *I; 88 unsigned DefReg = DefMI->getOperand(0).getReg(); 89 if (MRI->use_empty(DefReg)) 90 DefMI->eraseFromParent(); 91 } 92 93 ImpDefs.clear(); 94 VRegPHIUseCount.clear(); 95 return Changed; 96} 97 98/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in 99/// predecessor basic blocks. 100/// 101bool llvm::PHIElimination::EliminatePHINodes(MachineFunction &MF, 102 MachineBasicBlock &MBB) { 103 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI) 104 return false; // Quick exit for basic blocks without PHIs. 105 106 // Get an iterator to the first instruction after the last PHI node (this may 107 // also be the end of the basic block). 108 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin()); 109 110 while (MBB.front().getOpcode() == TargetInstrInfo::PHI) 111 LowerAtomicPHINode(MBB, AfterPHIsIt); 112 113 return true; 114} 115 116/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node 117/// are implicit_def's. 118static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, 119 const MachineRegisterInfo *MRI) { 120 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) { 121 unsigned SrcReg = MPhi->getOperand(i).getReg(); 122 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 123 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) 124 return false; 125 } 126 return true; 127} 128 129// FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg. 130// This needs to be after any def or uses of SrcReg, but before any subsequent 131// point where control flow might jump out of the basic block. 132MachineBasicBlock::iterator 133llvm::PHIElimination::FindCopyInsertPoint(MachineBasicBlock &MBB, 134 unsigned SrcReg) { 135 // Handle the trivial case trivially. 136 if (MBB.empty()) 137 return MBB.begin(); 138 139 // If this basic block does not contain an invoke, then control flow always 140 // reaches the end of it, so place the copy there. The logic below works in 141 // this case too, but is more expensive. 142 if (!isa<InvokeInst>(MBB.getBasicBlock()->getTerminator())) 143 return MBB.getFirstTerminator(); 144 145 // Discover any definition/uses in this basic block. 146 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB; 147 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), 148 RE = MRI->reg_end(); RI != RE; ++RI) { 149 MachineInstr *DefUseMI = &*RI; 150 if (DefUseMI->getParent() == &MBB) 151 DefUsesInMBB.insert(DefUseMI); 152 } 153 154 MachineBasicBlock::iterator InsertPoint; 155 if (DefUsesInMBB.empty()) { 156 // No def/uses. Insert the copy at the start of the basic block. 157 InsertPoint = MBB.begin(); 158 } else if (DefUsesInMBB.size() == 1) { 159 // Insert the copy immediately after the definition/use. 160 InsertPoint = *DefUsesInMBB.begin(); 161 ++InsertPoint; 162 } else { 163 // Insert the copy immediately after the last definition/use. 164 InsertPoint = MBB.end(); 165 while (!DefUsesInMBB.count(&*--InsertPoint)) {} 166 ++InsertPoint; 167 } 168 169 // Make sure the copy goes after any phi nodes however. 170 return SkipPHIsAndLabels(MBB, InsertPoint); 171} 172 173/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block, 174/// under the assuption that it needs to be lowered in a way that supports 175/// atomic execution of PHIs. This lowering method is always correct all of the 176/// time. 177/// 178void llvm::PHIElimination::LowerAtomicPHINode( 179 MachineBasicBlock &MBB, 180 MachineBasicBlock::iterator AfterPHIsIt) { 181 // Unlink the PHI node from the basic block, but don't delete the PHI yet. 182 MachineInstr *MPhi = MBB.remove(MBB.begin()); 183 184 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; 185 unsigned DestReg = MPhi->getOperand(0).getReg(); 186 bool isDead = MPhi->getOperand(0).isDead(); 187 188 // Create a new register for the incoming PHI arguments. 189 MachineFunction &MF = *MBB.getParent(); 190 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); 191 unsigned IncomingReg = 0; 192 193 // Insert a register to register copy at the top of the current block (but 194 // after any remaining phi nodes) which copies the new incoming register 195 // into the phi node destination. 196 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); 197 if (isSourceDefinedByImplicitDef(MPhi, MRI)) 198 // If all sources of a PHI node are implicit_def, just emit an 199 // implicit_def instead of a copy. 200 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), 201 TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg); 202 else { 203 IncomingReg = MF.getRegInfo().createVirtualRegister(RC); 204 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); 205 } 206 207 // Record PHI def. 208 assert(!hasPHIDef(DestReg) && "Vreg has multiple phi-defs?"); 209 PHIDefs[DestReg] = &MBB; 210 211 // Update live variable information if there is any. 212 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>(); 213 if (LV) { 214 MachineInstr *PHICopy = prior(AfterPHIsIt); 215 216 if (IncomingReg) { 217 // Increment use count of the newly created virtual register. 218 LV->getVarInfo(IncomingReg).NumUses++; 219 220 // Add information to LiveVariables to know that the incoming value is 221 // killed. Note that because the value is defined in several places (once 222 // each for each incoming block), the "def" block and instruction fields 223 // for the VarInfo is not filled in. 224 LV->addVirtualRegisterKilled(IncomingReg, PHICopy); 225 } 226 227 // Since we are going to be deleting the PHI node, if it is the last use of 228 // any registers, or if the value itself is dead, we need to move this 229 // information over to the new copy we just inserted. 230 LV->removeVirtualRegistersKilled(MPhi); 231 232 // If the result is dead, update LV. 233 if (isDead) { 234 LV->addVirtualRegisterDead(DestReg, PHICopy); 235 LV->removeVirtualRegisterDead(DestReg, MPhi); 236 } 237 } 238 239 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. 240 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 241 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(), 242 MPhi->getOperand(i).getReg())]; 243 244 // Now loop over all of the incoming arguments, changing them to copy into the 245 // IncomingReg register in the corresponding predecessor basic block. 246 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto; 247 for (int i = NumSrcs - 1; i >= 0; --i) { 248 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); 249 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && 250 "Machine PHI Operands must all be virtual registers!"); 251 252 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source 253 // path the PHI. 254 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB(); 255 256 // Record the kill. 257 PHIKills[SrcReg].insert(&opBlock); 258 259 // If source is defined by an implicit def, there is no need to insert a 260 // copy. 261 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 262 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { 263 ImpDefs.insert(DefMI); 264 continue; 265 } 266 267 // Check to make sure we haven't already emitted the copy for this block. 268 // This can happen because PHI nodes may have multiple entries for the same 269 // basic block. 270 if (!MBBsInsertedInto.insert(&opBlock)) 271 continue; // If the copy has already been emitted, we're done. 272 273 // Find a safe location to insert the copy, this may be the first terminator 274 // in the block (or end()). 275 MachineBasicBlock::iterator InsertPos = FindCopyInsertPoint(opBlock, SrcReg); 276 277 // Insert the copy. 278 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC); 279 280 // Now update live variable information if we have it. Otherwise we're done 281 if (!LV) continue; 282 283 // We want to be able to insert a kill of the register if this PHI (aka, the 284 // copy we just inserted) is the last use of the source value. Live 285 // variable analysis conservatively handles this by saying that the value is 286 // live until the end of the block the PHI entry lives in. If the value 287 // really is dead at the PHI copy, there will be no successor blocks which 288 // have the value live-in. 289 290 // Also check to see if this register is in use by another PHI node which 291 // has not yet been eliminated. If so, it will be killed at an appropriate 292 // point later. 293 294 // Is it used by any PHI instructions in this block? 295 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0; 296 297 // Okay, if we now know that the value is not live out of the block, we can 298 // add a kill marker in this block saying that it kills the incoming value! 299 // When SplitEdges is enabled, the value is never live out. 300 if (!ValueIsUsed && !isLiveOut(SrcReg, opBlock, *LV)) { 301 // In our final twist, we have to decide which instruction kills the 302 // register. In most cases this is the copy, however, the first 303 // terminator instruction at the end of the block may also use the value. 304 // In this case, we should mark *it* as being the killing block, not the 305 // copy. 306 MachineBasicBlock::iterator KillInst = prior(InsertPos); 307 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator(); 308 if (Term != opBlock.end()) { 309 if (Term->readsRegister(SrcReg)) 310 KillInst = Term; 311 312 // Check that no other terminators use values. 313#ifndef NDEBUG 314 for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end(); 315 ++TI) { 316 assert(!TI->readsRegister(SrcReg) && 317 "Terminator instructions cannot use virtual registers unless" 318 "they are the first terminator in a block!"); 319 } 320#endif 321 } 322 323 // Finally, mark it killed. 324 LV->addVirtualRegisterKilled(SrcReg, KillInst); 325 326 // This vreg no longer lives all of the way through opBlock. 327 unsigned opBlockNum = opBlock.getNumber(); 328 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum); 329 } 330 } 331 332 // Really delete the PHI instruction now! 333 MF.DeleteMachineInstr(MPhi); 334 ++NumAtomic; 335} 336 337/// analyzePHINodes - Gather information about the PHI nodes in here. In 338/// particular, we want to map the number of uses of a virtual register which is 339/// used in a PHI node. We map that to the BB the vreg is coming from. This is 340/// used later to determine when the vreg is killed in the BB. 341/// 342void llvm::PHIElimination::analyzePHINodes(const MachineFunction& Fn) { 343 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end(); 344 I != E; ++I) 345 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 346 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) 347 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 348 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(), 349 BBI->getOperand(i).getReg())]; 350} 351 352bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF, 353 MachineBasicBlock &MBB) { 354 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI) 355 return false; // Quick exit for basic blocks without PHIs. 356 LiveVariables &LV = getAnalysis<LiveVariables>(); 357 for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end(); 358 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) { 359 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 360 unsigned Reg = BBI->getOperand(i).getReg(); 361 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB(); 362 // We break edges when registers are live out from the predecessor block 363 // (not considering PHI nodes). If the register is live in to this block 364 // anyway, we would gain nothing from splitting. 365 if (isLiveOut(Reg, *PreMBB, LV) && !isLiveIn(Reg, MBB, LV)) 366 SplitCriticalEdge(PreMBB, &MBB); 367 } 368 } 369 return true; 370} 371 372bool llvm::PHIElimination::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB, 373 LiveVariables &LV) { 374 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg); 375 376 // Loop over all of the successors of the basic block, checking to see if 377 // the value is either live in the block, or if it is killed in the block. 378 std::vector<MachineBasicBlock*> OpSuccBlocks; 379 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(), 380 E = MBB.succ_end(); SI != E; ++SI) { 381 MachineBasicBlock *SuccMBB = *SI; 382 383 // Is it alive in this successor? 384 unsigned SuccIdx = SuccMBB->getNumber(); 385 if (VI.AliveBlocks.test(SuccIdx)) 386 return true; 387 OpSuccBlocks.push_back(SuccMBB); 388 } 389 390 // Check to see if this value is live because there is a use in a successor 391 // that kills it. 392 switch (OpSuccBlocks.size()) { 393 case 1: { 394 MachineBasicBlock *SuccMBB = OpSuccBlocks[0]; 395 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i) 396 if (VI.Kills[i]->getParent() == SuccMBB) 397 return true; 398 break; 399 } 400 case 2: { 401 MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1]; 402 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i) 403 if (VI.Kills[i]->getParent() == SuccMBB1 || 404 VI.Kills[i]->getParent() == SuccMBB2) 405 return true; 406 break; 407 } 408 default: 409 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end()); 410 for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i) 411 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(), 412 VI.Kills[i]->getParent())) 413 return true; 414 } 415 return false; 416} 417 418bool llvm::PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock &MBB, 419 LiveVariables &LV) { 420 LiveVariables::VarInfo &VI = LV.getVarInfo(Reg); 421 422 return VI.AliveBlocks.test(MBB.getNumber()) || VI.findKill(&MBB); 423} 424 425MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A, 426 MachineBasicBlock *B) { 427 assert(A && B && "Missing MBB end point"); 428 ++NumSplits; 429 430 BasicBlock *ABB = const_cast<BasicBlock*>(A->getBasicBlock()); 431 BasicBlock *BBB = const_cast<BasicBlock*>(B->getBasicBlock()); 432 assert(ABB && BBB && "End points must have a basic block"); 433 BasicBlock *BB = BasicBlock::Create(BBB->getContext(), 434 ABB->getName() + "." + BBB->getName() + 435 "_phi_edge"); 436 Function *F = ABB->getParent(); 437 F->getBasicBlockList().insert(F->end(), BB); 438 439 BranchInst::Create(BBB, BB); 440 // We could do more here to produce correct IR, compare 441 // llvm::SplitCriticalEdge 442 443 MachineFunction *MF = A->getParent(); 444 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(BB); 445 MF->push_back(NMBB); 446 const unsigned NewNum = NMBB->getNumber(); 447 DEBUG(errs() << "PHIElimination splitting critical edge:" 448 " BB#" << A->getNumber() 449 << " -- BB#" << NewNum 450 << " -- BB#" << B->getNumber() << '\n'); 451 452 A->ReplaceUsesOfBlockWith(B, NMBB); 453 NMBB->addSuccessor(B); 454 455 // Insert unconditional "jump B" instruction in NMBB. 456 SmallVector<MachineOperand, 4> Cond; 457 MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond); 458 459 if (LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>()) 460 LV->addNewBlock(NMBB, A); 461 462 // Fix PHI nodes in B so they refer to NMBB instead of A 463 for (MachineBasicBlock::iterator i = B->begin(), e = B->end(); 464 i != e && i->getOpcode() == TargetInstrInfo::PHI; ++i) 465 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2) 466 if (i->getOperand(ni+1).getMBB() == A) 467 i->getOperand(ni+1).setMBB(NMBB); 468 return NMBB; 469} 470