PHIElimination.cpp revision 518bb53485df640d7b7e3f6b0544099020c42aa7
1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass eliminates machine instruction PHI nodes by inserting copy 11// instructions. This destroys SSA information, but is the desired input for 12// some register allocators. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "phielim" 17#include "PHIElimination.h" 18#include "llvm/CodeGen/LiveVariables.h" 19#include "llvm/CodeGen/Passes.h" 20#include "llvm/CodeGen/MachineDominators.h" 21#include "llvm/CodeGen/MachineInstr.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/Target/TargetInstrInfo.h" 25#include "llvm/Function.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/ADT/SmallPtrSet.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/ADT/Statistic.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Compiler.h" 32#include "llvm/Support/Debug.h" 33#include <algorithm> 34#include <map> 35using namespace llvm; 36 37STATISTIC(NumAtomic, "Number of atomic phis lowered"); 38STATISTIC(NumSplits, "Number of critical edges split on demand"); 39STATISTIC(NumReused, "Number of reused lowered phis"); 40 41char PHIElimination::ID = 0; 42static RegisterPass<PHIElimination> 43X("phi-node-elimination", "Eliminate PHI nodes for register allocation"); 44 45const PassInfo *const llvm::PHIEliminationID = &X; 46 47void llvm::PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const { 48 AU.addPreserved<LiveVariables>(); 49 AU.addPreserved<MachineDominatorTree>(); 50 // rdar://7401784 This would be nice: 51 // AU.addPreservedID(MachineLoopInfoID); 52 MachineFunctionPass::getAnalysisUsage(AU); 53} 54 55bool llvm::PHIElimination::runOnMachineFunction(MachineFunction &Fn) { 56 MRI = &Fn.getRegInfo(); 57 58 PHIDefs.clear(); 59 PHIKills.clear(); 60 bool Changed = false; 61 62 // Split critical edges to help the coalescer 63 if (LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>()) 64 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 65 Changed |= SplitPHIEdges(Fn, *I, *LV); 66 67 // Populate VRegPHIUseCount 68 analyzePHINodes(Fn); 69 70 // Eliminate PHI instructions by inserting copies into predecessor blocks. 71 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 72 Changed |= EliminatePHINodes(Fn, *I); 73 74 // Remove dead IMPLICIT_DEF instructions. 75 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(), 76 E = ImpDefs.end(); I != E; ++I) { 77 MachineInstr *DefMI = *I; 78 unsigned DefReg = DefMI->getOperand(0).getReg(); 79 if (MRI->use_empty(DefReg)) 80 DefMI->eraseFromParent(); 81 } 82 83 // Clean up the lowered PHI instructions. 84 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end(); 85 I != E; ++I) 86 Fn.DeleteMachineInstr(I->first); 87 88 LoweredPHIs.clear(); 89 ImpDefs.clear(); 90 VRegPHIUseCount.clear(); 91 return Changed; 92} 93 94/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in 95/// predecessor basic blocks. 96/// 97bool llvm::PHIElimination::EliminatePHINodes(MachineFunction &MF, 98 MachineBasicBlock &MBB) { 99 if (MBB.empty() || !MBB.front().isPHI()) 100 return false; // Quick exit for basic blocks without PHIs. 101 102 // Get an iterator to the first instruction after the last PHI node (this may 103 // also be the end of the basic block). 104 MachineBasicBlock::iterator AfterPHIsIt = SkipPHIsAndLabels(MBB, MBB.begin()); 105 106 while (MBB.front().isPHI()) 107 LowerAtomicPHINode(MBB, AfterPHIsIt); 108 109 return true; 110} 111 112/// isSourceDefinedByImplicitDef - Return true if all sources of the phi node 113/// are implicit_def's. 114static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, 115 const MachineRegisterInfo *MRI) { 116 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) { 117 unsigned SrcReg = MPhi->getOperand(i).getReg(); 118 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 119 if (!DefMI || !DefMI->isImplicitDef()) 120 return false; 121 } 122 return true; 123} 124 125// FindCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg 126// when following the CFG edge to SuccMBB. This needs to be after any def of 127// SrcReg, but before any subsequent point where control flow might jump out of 128// the basic block. 129MachineBasicBlock::iterator 130llvm::PHIElimination::FindCopyInsertPoint(MachineBasicBlock &MBB, 131 MachineBasicBlock &SuccMBB, 132 unsigned SrcReg) { 133 // Handle the trivial case trivially. 134 if (MBB.empty()) 135 return MBB.begin(); 136 137 // Usually, we just want to insert the copy before the first terminator 138 // instruction. However, for the edge going to a landing pad, we must insert 139 // the copy before the call/invoke instruction. 140 if (!SuccMBB.isLandingPad()) 141 return MBB.getFirstTerminator(); 142 143 // Discover any defs/uses in this basic block. 144 SmallPtrSet<MachineInstr*, 8> DefUsesInMBB; 145 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), 146 RE = MRI->reg_end(); RI != RE; ++RI) { 147 MachineInstr *DefUseMI = &*RI; 148 if (DefUseMI->getParent() == &MBB) 149 DefUsesInMBB.insert(DefUseMI); 150 } 151 152 MachineBasicBlock::iterator InsertPoint; 153 if (DefUsesInMBB.empty()) { 154 // No defs. Insert the copy at the start of the basic block. 155 InsertPoint = MBB.begin(); 156 } else if (DefUsesInMBB.size() == 1) { 157 // Insert the copy immediately after the def/use. 158 InsertPoint = *DefUsesInMBB.begin(); 159 ++InsertPoint; 160 } else { 161 // Insert the copy immediately after the last def/use. 162 InsertPoint = MBB.end(); 163 while (!DefUsesInMBB.count(&*--InsertPoint)) {} 164 ++InsertPoint; 165 } 166 167 // Make sure the copy goes after any phi nodes however. 168 return SkipPHIsAndLabels(MBB, InsertPoint); 169} 170 171/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block, 172/// under the assuption that it needs to be lowered in a way that supports 173/// atomic execution of PHIs. This lowering method is always correct all of the 174/// time. 175/// 176void llvm::PHIElimination::LowerAtomicPHINode( 177 MachineBasicBlock &MBB, 178 MachineBasicBlock::iterator AfterPHIsIt) { 179 ++NumAtomic; 180 // Unlink the PHI node from the basic block, but don't delete the PHI yet. 181 MachineInstr *MPhi = MBB.remove(MBB.begin()); 182 183 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; 184 unsigned DestReg = MPhi->getOperand(0).getReg(); 185 bool isDead = MPhi->getOperand(0).isDead(); 186 187 // Create a new register for the incoming PHI arguments. 188 MachineFunction &MF = *MBB.getParent(); 189 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); 190 unsigned IncomingReg = 0; 191 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI? 192 193 // Insert a register to register copy at the top of the current block (but 194 // after any remaining phi nodes) which copies the new incoming register 195 // into the phi node destination. 196 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); 197 if (isSourceDefinedByImplicitDef(MPhi, MRI)) 198 // If all sources of a PHI node are implicit_def, just emit an 199 // implicit_def instead of a copy. 200 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(), 201 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); 202 else { 203 // Can we reuse an earlier PHI node? This only happens for critical edges, 204 // typically those created by tail duplication. 205 unsigned &entry = LoweredPHIs[MPhi]; 206 if (entry) { 207 // An identical PHI node was already lowered. Reuse the incoming register. 208 IncomingReg = entry; 209 reusedIncoming = true; 210 ++NumReused; 211 DEBUG(dbgs() << "Reusing %reg" << IncomingReg << " for " << *MPhi); 212 } else { 213 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC); 214 } 215 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); 216 } 217 218 // Record PHI def. 219 assert(!hasPHIDef(DestReg) && "Vreg has multiple phi-defs?"); 220 PHIDefs[DestReg] = &MBB; 221 222 // Update live variable information if there is any. 223 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>(); 224 if (LV) { 225 MachineInstr *PHICopy = prior(AfterPHIsIt); 226 227 if (IncomingReg) { 228 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg); 229 230 // Increment use count of the newly created virtual register. 231 VI.NumUses++; 232 233 // When we are reusing the incoming register, it may already have been 234 // killed in this block. The old kill will also have been inserted at 235 // AfterPHIsIt, so it appears before the current PHICopy. 236 if (reusedIncoming) 237 if (MachineInstr *OldKill = VI.findKill(&MBB)) { 238 DEBUG(dbgs() << "Remove old kill from " << *OldKill); 239 LV->removeVirtualRegisterKilled(IncomingReg, OldKill); 240 DEBUG(MBB.dump()); 241 } 242 243 // Add information to LiveVariables to know that the incoming value is 244 // killed. Note that because the value is defined in several places (once 245 // each for each incoming block), the "def" block and instruction fields 246 // for the VarInfo is not filled in. 247 LV->addVirtualRegisterKilled(IncomingReg, PHICopy); 248 } 249 250 // Since we are going to be deleting the PHI node, if it is the last use of 251 // any registers, or if the value itself is dead, we need to move this 252 // information over to the new copy we just inserted. 253 LV->removeVirtualRegistersKilled(MPhi); 254 255 // If the result is dead, update LV. 256 if (isDead) { 257 LV->addVirtualRegisterDead(DestReg, PHICopy); 258 LV->removeVirtualRegisterDead(DestReg, MPhi); 259 } 260 } 261 262 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. 263 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 264 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(), 265 MPhi->getOperand(i).getReg())]; 266 267 // Now loop over all of the incoming arguments, changing them to copy into the 268 // IncomingReg register in the corresponding predecessor basic block. 269 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto; 270 for (int i = NumSrcs - 1; i >= 0; --i) { 271 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); 272 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && 273 "Machine PHI Operands must all be virtual registers!"); 274 275 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source 276 // path the PHI. 277 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB(); 278 279 // Record the kill. 280 PHIKills[SrcReg].insert(&opBlock); 281 282 // If source is defined by an implicit def, there is no need to insert a 283 // copy. 284 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 285 if (DefMI->isImplicitDef()) { 286 ImpDefs.insert(DefMI); 287 continue; 288 } 289 290 // Check to make sure we haven't already emitted the copy for this block. 291 // This can happen because PHI nodes may have multiple entries for the same 292 // basic block. 293 if (!MBBsInsertedInto.insert(&opBlock)) 294 continue; // If the copy has already been emitted, we're done. 295 296 // Find a safe location to insert the copy, this may be the first terminator 297 // in the block (or end()). 298 MachineBasicBlock::iterator InsertPos = 299 FindCopyInsertPoint(opBlock, MBB, SrcReg); 300 301 // Insert the copy. 302 if (!reusedIncoming && IncomingReg) 303 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC); 304 305 // Now update live variable information if we have it. Otherwise we're done 306 if (!LV) continue; 307 308 // We want to be able to insert a kill of the register if this PHI (aka, the 309 // copy we just inserted) is the last use of the source value. Live 310 // variable analysis conservatively handles this by saying that the value is 311 // live until the end of the block the PHI entry lives in. If the value 312 // really is dead at the PHI copy, there will be no successor blocks which 313 // have the value live-in. 314 315 // Also check to see if this register is in use by another PHI node which 316 // has not yet been eliminated. If so, it will be killed at an appropriate 317 // point later. 318 319 // Is it used by any PHI instructions in this block? 320 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]; 321 322 // Okay, if we now know that the value is not live out of the block, we can 323 // add a kill marker in this block saying that it kills the incoming value! 324 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) { 325 // In our final twist, we have to decide which instruction kills the 326 // register. In most cases this is the copy, however, the first 327 // terminator instruction at the end of the block may also use the value. 328 // In this case, we should mark *it* as being the killing block, not the 329 // copy. 330 MachineBasicBlock::iterator KillInst; 331 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator(); 332 if (Term != opBlock.end() && Term->readsRegister(SrcReg)) { 333 KillInst = Term; 334 335 // Check that no other terminators use values. 336#ifndef NDEBUG 337 for (MachineBasicBlock::iterator TI = llvm::next(Term); 338 TI != opBlock.end(); ++TI) { 339 assert(!TI->readsRegister(SrcReg) && 340 "Terminator instructions cannot use virtual registers unless" 341 "they are the first terminator in a block!"); 342 } 343#endif 344 } else if (reusedIncoming || !IncomingReg) { 345 // We may have to rewind a bit if we didn't insert a copy this time. 346 KillInst = Term; 347 while (KillInst != opBlock.begin()) 348 if ((--KillInst)->readsRegister(SrcReg)) 349 break; 350 } else { 351 // We just inserted this copy. 352 KillInst = prior(InsertPos); 353 } 354 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction"); 355 356 // Finally, mark it killed. 357 LV->addVirtualRegisterKilled(SrcReg, KillInst); 358 359 // This vreg no longer lives all of the way through opBlock. 360 unsigned opBlockNum = opBlock.getNumber(); 361 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum); 362 } 363 } 364 365 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map. 366 if (reusedIncoming || !IncomingReg) 367 MF.DeleteMachineInstr(MPhi); 368} 369 370/// analyzePHINodes - Gather information about the PHI nodes in here. In 371/// particular, we want to map the number of uses of a virtual register which is 372/// used in a PHI node. We map that to the BB the vreg is coming from. This is 373/// used later to determine when the vreg is killed in the BB. 374/// 375void llvm::PHIElimination::analyzePHINodes(const MachineFunction& Fn) { 376 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end(); 377 I != E; ++I) 378 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 379 BBI != BBE && BBI->isPHI(); ++BBI) 380 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 381 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(), 382 BBI->getOperand(i).getReg())]; 383} 384 385bool llvm::PHIElimination::SplitPHIEdges(MachineFunction &MF, 386 MachineBasicBlock &MBB, 387 LiveVariables &LV) { 388 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad()) 389 return false; // Quick exit for basic blocks without PHIs. 390 391 for (MachineBasicBlock::const_iterator BBI = MBB.begin(), BBE = MBB.end(); 392 BBI != BBE && BBI->isPHI(); ++BBI) { 393 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) { 394 unsigned Reg = BBI->getOperand(i).getReg(); 395 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB(); 396 // We break edges when registers are live out from the predecessor block 397 // (not considering PHI nodes). If the register is live in to this block 398 // anyway, we would gain nothing from splitting. 399 if (!LV.isLiveIn(Reg, MBB) && LV.isLiveOut(Reg, *PreMBB)) 400 SplitCriticalEdge(PreMBB, &MBB); 401 } 402 } 403 return true; 404} 405 406MachineBasicBlock *PHIElimination::SplitCriticalEdge(MachineBasicBlock *A, 407 MachineBasicBlock *B) { 408 assert(A && B && "Missing MBB end point"); 409 410 MachineFunction *MF = A->getParent(); 411 412 // We may need to update A's terminator, but we can't do that if AnalyzeBranch 413 // fails. If A uses a jump table, we won't touch it. 414 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 415 MachineBasicBlock *TBB = 0, *FBB = 0; 416 SmallVector<MachineOperand, 4> Cond; 417 if (TII->AnalyzeBranch(*A, TBB, FBB, Cond)) 418 return NULL; 419 420 ++NumSplits; 421 422 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); 423 MF->insert(llvm::next(MachineFunction::iterator(A)), NMBB); 424 DEBUG(dbgs() << "PHIElimination splitting critical edge:" 425 " BB#" << A->getNumber() 426 << " -- BB#" << NMBB->getNumber() 427 << " -- BB#" << B->getNumber() << '\n'); 428 429 A->ReplaceUsesOfBlockWith(B, NMBB); 430 A->updateTerminator(); 431 432 // Insert unconditional "jump B" instruction in NMBB if necessary. 433 NMBB->addSuccessor(B); 434 if (!NMBB->isLayoutSuccessor(B)) { 435 Cond.clear(); 436 MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond); 437 } 438 439 // Fix PHI nodes in B so they refer to NMBB instead of A 440 for (MachineBasicBlock::iterator i = B->begin(), e = B->end(); 441 i != e && i->isPHI(); ++i) 442 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2) 443 if (i->getOperand(ni+1).getMBB() == A) 444 i->getOperand(ni+1).setMBB(NMBB); 445 446 if (LiveVariables *LV=getAnalysisIfAvailable<LiveVariables>()) 447 LV->addNewBlock(NMBB, A, B); 448 449 if (MachineDominatorTree *MDT=getAnalysisIfAvailable<MachineDominatorTree>()) 450 MDT->addNewBlock(NMBB, A); 451 452 return NMBB; 453} 454 455unsigned 456PHIElimination::PHINodeTraits::getHashValue(const MachineInstr *MI) { 457 if (!MI || MI==getEmptyKey() || MI==getTombstoneKey()) 458 return DenseMapInfo<MachineInstr*>::getHashValue(MI); 459 unsigned hash = 0; 460 for (unsigned ni = 1, ne = MI->getNumOperands(); ni != ne; ni += 2) 461 hash = hash*37 + DenseMapInfo<BBVRegPair>:: 462 getHashValue(BBVRegPair(MI->getOperand(ni+1).getMBB()->getNumber(), 463 MI->getOperand(ni).getReg())); 464 return hash; 465} 466 467bool PHIElimination::PHINodeTraits::isEqual(const MachineInstr *LHS, 468 const MachineInstr *RHS) { 469 const MachineInstr *EmptyKey = getEmptyKey(); 470 const MachineInstr *TombstoneKey = getTombstoneKey(); 471 if (!LHS || !RHS || LHS==EmptyKey || RHS==EmptyKey || 472 LHS==TombstoneKey || RHS==TombstoneKey) 473 return LHS==RHS; 474 475 unsigned ne = LHS->getNumOperands(); 476 if (ne != RHS->getNumOperands()) 477 return false; 478 // Ignore operand 0, the defined register. 479 for (unsigned ni = 1; ni != ne; ni += 2) 480 if (LHS->getOperand(ni).getReg() != RHS->getOperand(ni).getReg() || 481 LHS->getOperand(ni+1).getMBB() != RHS->getOperand(ni+1).getMBB()) 482 return false; 483 return true; 484} 485