PHIElimination.cpp revision 8aa797aa51cd4ea1ec6f46f4891a6897944b75b2
1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass eliminates machine instruction PHI nodes by inserting copy 11// instructions. This destroys SSA information, but is the desired input for 12// some register allocators. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "phielim" 17#include "llvm/CodeGen/LiveVariables.h" 18#include "llvm/CodeGen/Passes.h" 19#include "llvm/CodeGen/MachineFunctionPass.h" 20#include "llvm/CodeGen/MachineInstr.h" 21#include "llvm/CodeGen/SSARegMap.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/ADT/STLExtras.h" 25#include "llvm/ADT/Statistic.h" 26#include "llvm/Support/Compiler.h" 27#include <set> 28#include <algorithm> 29using namespace llvm; 30 31STATISTIC(NumAtomic, "Number of atomic phis lowered"); 32//STATISTIC(NumSimple, "Number of simple phis lowered"); 33 34namespace { 35 struct VISIBILITY_HIDDEN PNE : public MachineFunctionPass { 36 static char ID; // Pass identification, replacement for typeid 37 PNE() : MachineFunctionPass((intptr_t)&ID) {} 38 39 bool runOnMachineFunction(MachineFunction &Fn) { 40 analyzePHINodes(Fn); 41 42 bool Changed = false; 43 44 // Eliminate PHI instructions by inserting copies into predecessor blocks. 45 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 46 Changed |= EliminatePHINodes(Fn, *I); 47 48 VRegPHIUseCount.clear(); 49 return Changed; 50 } 51 52 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 53 AU.addPreserved<LiveVariables>(); 54 MachineFunctionPass::getAnalysisUsage(AU); 55 } 56 57 private: 58 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions 59 /// in predecessor basic blocks. 60 /// 61 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB); 62 void LowerAtomicPHINode(MachineBasicBlock &MBB, 63 MachineBasicBlock::iterator AfterPHIsIt); 64 65 /// analyzePHINodes - Gather information about the PHI nodes in 66 /// here. In particular, we want to map the number of uses of a virtual 67 /// register which is used in a PHI node. We map that to the BB the 68 /// vreg is coming from. This is used later to determine when the vreg 69 /// is killed in the BB. 70 /// 71 void analyzePHINodes(const MachineFunction& Fn); 72 73 typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair; 74 typedef std::map<BBVRegPair, unsigned> VRegPHIUse; 75 76 VRegPHIUse VRegPHIUseCount; 77 }; 78 79 char PNE::ID = 0; 80 RegisterPass<PNE> X("phi-node-elimination", 81 "Eliminate PHI nodes for register allocation"); 82} 83 84const PassInfo *llvm::PHIEliminationID = X.getPassInfo(); 85 86/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in 87/// predecessor basic blocks. 88/// 89bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) { 90 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI) 91 return false; // Quick exit for basic blocks without PHIs. 92 93 // Get an iterator to the first instruction after the last PHI node (this may 94 // also be the end of the basic block). 95 MachineBasicBlock::iterator AfterPHIsIt = MBB.begin(); 96 while (AfterPHIsIt != MBB.end() && 97 AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI) 98 ++AfterPHIsIt; // Skip over all of the PHI nodes... 99 100 while (MBB.front().getOpcode() == TargetInstrInfo::PHI) 101 LowerAtomicPHINode(MBB, AfterPHIsIt); 102 103 return true; 104} 105 106/// InstructionUsesRegister - Return true if the specified machine instr has a 107/// use of the specified register. 108static bool InstructionUsesRegister(MachineInstr *MI, unsigned SrcReg) { 109 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) 110 if (MI->getOperand(i).isRegister() && 111 MI->getOperand(i).getReg() == SrcReg && 112 MI->getOperand(i).isUse()) 113 return true; 114 return false; 115} 116 117/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block, 118/// under the assuption that it needs to be lowered in a way that supports 119/// atomic execution of PHIs. This lowering method is always correct all of the 120/// time. 121void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, 122 MachineBasicBlock::iterator AfterPHIsIt) { 123 // Unlink the PHI node from the basic block, but don't delete the PHI yet. 124 MachineInstr *MPhi = MBB.remove(MBB.begin()); 125 126 unsigned DestReg = MPhi->getOperand(0).getReg(); 127 128 // Create a new register for the incoming PHI arguments. 129 MachineFunction &MF = *MBB.getParent(); 130 const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg); 131 unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC); 132 133 // Insert a register to register copy in the top of the current block (but 134 // after any remaining phi nodes) which copies the new incoming register 135 // into the phi node destination. 136 // 137 const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 138 RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); 139 140 // Update live variable information if there is any... 141 LiveVariables *LV = getAnalysisToUpdate<LiveVariables>(); 142 if (LV) { 143 MachineInstr *PHICopy = prior(AfterPHIsIt); 144 145 // Increment use count of the newly created virtual register. 146 LV->getVarInfo(IncomingReg).NumUses++; 147 148 // Add information to LiveVariables to know that the incoming value is 149 // killed. Note that because the value is defined in several places (once 150 // each for each incoming block), the "def" block and instruction fields 151 // for the VarInfo is not filled in. 152 // 153 LV->addVirtualRegisterKilled(IncomingReg, PHICopy); 154 155 // Since we are going to be deleting the PHI node, if it is the last use 156 // of any registers, or if the value itself is dead, we need to move this 157 // information over to the new copy we just inserted. 158 // 159 LV->removeVirtualRegistersKilled(MPhi); 160 161 // If the result is dead, update LV. 162 if (LV->RegisterDefIsDead(MPhi, DestReg)) { 163 LV->addVirtualRegisterDead(DestReg, PHICopy); 164 LV->removeVirtualRegistersDead(MPhi); 165 } 166 167 // Realize that the destination register is defined by the PHI copy now, not 168 // the PHI itself. 169 LV->getVarInfo(DestReg).DefInst = PHICopy; 170 171 LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true; 172 } 173 174 // Adjust the VRegPHIUseCount map to account for the removal of this PHI 175 // node. 176 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 177 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(), 178 MPhi->getOperand(i).getReg())]; 179 180 // Now loop over all of the incoming arguments, changing them to copy into 181 // the IncomingReg register in the corresponding predecessor basic block. 182 // 183 std::set<MachineBasicBlock*> MBBsInsertedInto; 184 for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) { 185 unsigned SrcReg = MPhi->getOperand(i-1).getReg(); 186 assert(MRegisterInfo::isVirtualRegister(SrcReg) && 187 "Machine PHI Operands must all be virtual registers!"); 188 189 // Get the MachineBasicBlock equivalent of the BasicBlock that is the 190 // source path the PHI. 191 MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMBB(); 192 193 // Check to make sure we haven't already emitted the copy for this block. 194 // This can happen because PHI nodes may have multiple entries for the 195 // same basic block. 196 if (!MBBsInsertedInto.insert(&opBlock).second) 197 continue; // If the copy has already been emitted, we're done. 198 199 // Get an iterator pointing to the first terminator in the block (or end()). 200 // This is the point where we can insert a copy if we'd like to. 201 MachineBasicBlock::iterator I = opBlock.getFirstTerminator(); 202 203 // Insert the copy. 204 RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC); 205 206 // Now update live variable information if we have it. Otherwise we're done 207 if (!LV) continue; 208 209 // We want to be able to insert a kill of the register if this PHI 210 // (aka, the copy we just inserted) is the last use of the source 211 // value. Live variable analysis conservatively handles this by 212 // saying that the value is live until the end of the block the PHI 213 // entry lives in. If the value really is dead at the PHI copy, there 214 // will be no successor blocks which have the value live-in. 215 // 216 // Check to see if the copy is the last use, and if so, update the 217 // live variables information so that it knows the copy source 218 // instruction kills the incoming value. 219 // 220 LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg); 221 InRegVI.UsedBlocks[opBlock.getNumber()] = true; 222 223 // Loop over all of the successors of the basic block, checking to see 224 // if the value is either live in the block, or if it is killed in the 225 // block. Also check to see if this register is in use by another PHI 226 // node which has not yet been eliminated. If so, it will be killed 227 // at an appropriate point later. 228 // 229 230 // Is it used by any PHI instructions in this block? 231 bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0; 232 233 std::vector<MachineBasicBlock*> OpSuccBlocks; 234 235 // Otherwise, scan successors, including the BB the PHI node lives in. 236 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(), 237 E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) { 238 MachineBasicBlock *SuccMBB = *SI; 239 240 // Is it alive in this successor? 241 unsigned SuccIdx = SuccMBB->getNumber(); 242 if (SuccIdx < InRegVI.AliveBlocks.size() && 243 InRegVI.AliveBlocks[SuccIdx]) { 244 ValueIsLive = true; 245 break; 246 } 247 248 OpSuccBlocks.push_back(SuccMBB); 249 } 250 251 // Check to see if this value is live because there is a use in a successor 252 // that kills it. 253 if (!ValueIsLive) { 254 switch (OpSuccBlocks.size()) { 255 case 1: { 256 MachineBasicBlock *MBB = OpSuccBlocks[0]; 257 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 258 if (InRegVI.Kills[i]->getParent() == MBB) { 259 ValueIsLive = true; 260 break; 261 } 262 break; 263 } 264 case 2: { 265 MachineBasicBlock *MBB1 = OpSuccBlocks[0], *MBB2 = OpSuccBlocks[1]; 266 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 267 if (InRegVI.Kills[i]->getParent() == MBB1 || 268 InRegVI.Kills[i]->getParent() == MBB2) { 269 ValueIsLive = true; 270 break; 271 } 272 break; 273 } 274 default: 275 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end()); 276 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 277 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(), 278 InRegVI.Kills[i]->getParent())) { 279 ValueIsLive = true; 280 break; 281 } 282 } 283 } 284 285 // Okay, if we now know that the value is not live out of the block, 286 // we can add a kill marker in this block saying that it kills the incoming 287 // value! 288 if (!ValueIsLive) { 289 // In our final twist, we have to decide which instruction kills the 290 // register. In most cases this is the copy, however, the first 291 // terminator instruction at the end of the block may also use the value. 292 // In this case, we should mark *it* as being the killing block, not the 293 // copy. 294 bool FirstTerminatorUsesValue = false; 295 if (I != opBlock.end()) { 296 FirstTerminatorUsesValue = InstructionUsesRegister(I, SrcReg); 297 298 // Check that no other terminators use values. 299#ifndef NDEBUG 300 for (MachineBasicBlock::iterator TI = next(I); TI != opBlock.end(); 301 ++TI) { 302 assert(!InstructionUsesRegister(TI, SrcReg) && 303 "Terminator instructions cannot use virtual registers unless" 304 "they are the first terminator in a block!"); 305 } 306#endif 307 } 308 309 MachineBasicBlock::iterator KillInst; 310 if (!FirstTerminatorUsesValue) 311 KillInst = prior(I); 312 else 313 KillInst = I; 314 315 // Finally, mark it killed. 316 LV->addVirtualRegisterKilled(SrcReg, KillInst); 317 318 // This vreg no longer lives all of the way through opBlock. 319 unsigned opBlockNum = opBlock.getNumber(); 320 if (opBlockNum < InRegVI.AliveBlocks.size()) 321 InRegVI.AliveBlocks[opBlockNum] = false; 322 } 323 } 324 325 // Really delete the PHI instruction now! 326 delete MPhi; 327 ++NumAtomic; 328} 329 330/// analyzePHINodes - Gather information about the PHI nodes in here. In 331/// particular, we want to map the number of uses of a virtual register which is 332/// used in a PHI node. We map that to the BB the vreg is coming from. This is 333/// used later to determine when the vreg is killed in the BB. 334/// 335void PNE::analyzePHINodes(const MachineFunction& Fn) { 336 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end(); 337 I != E; ++I) 338 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 339 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) 340 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 341 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(), 342 BBI->getOperand(i).getReg())]; 343} 344