InstrEmitter.cpp revision 06a26637daff1bb785ef0945d1ba05f6ccdfab86
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "SDDbgValue.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetLowering.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33/// CountResults - The results of target nodes have register or immediate 34/// operands first, then an optional chain, and optional flag operands (which do 35/// not go into the resulting MachineInstr). 36unsigned InstrEmitter::CountResults(SDNode *Node) { 37 unsigned N = Node->getNumValues(); 38 while (N && Node->getValueType(N - 1) == MVT::Flag) 39 --N; 40 if (N && Node->getValueType(N - 1) == MVT::Other) 41 --N; // Skip over chain result. 42 return N; 43} 44 45/// CountOperands - The inputs to target nodes have any actual inputs first, 46/// followed by an optional chain operand, then an optional flag operand. 47/// Compute the number of actual operands that will go into the resulting 48/// MachineInstr. 49unsigned InstrEmitter::CountOperands(SDNode *Node) { 50 unsigned N = Node->getNumOperands(); 51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52 --N; 53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54 --N; // Ignore chain if it exists. 55 return N; 56} 57 58/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59/// implicit physical register output. 60void InstrEmitter:: 61EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63 unsigned VRBase = 0; 64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65 // Just use the input register directly! 66 SDValue Op(Node, ResNo); 67 if (IsClone) 68 VRBaseMap.erase(Op); 69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70 isNew = isNew; // Silence compiler warning. 71 assert(isNew && "Node emitted out of order - early"); 72 return; 73 } 74 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76 // the CopyToReg'd destination register instead of creating a new vreg. 77 bool MatchReg = true; 78 const TargetRegisterClass *UseRC = NULL; 79 if (!IsClone && !IsCloned) 80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81 UI != E; ++UI) { 82 SDNode *User = *UI; 83 bool Match = true; 84 if (User->getOpcode() == ISD::CopyToReg && 85 User->getOperand(2).getNode() == Node && 86 User->getOperand(2).getResNo() == ResNo) { 87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89 VRBase = DestReg; 90 Match = false; 91 } else if (DestReg != SrcReg) 92 Match = false; 93 } else { 94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95 SDValue Op = User->getOperand(i); 96 if (Op.getNode() != Node || Op.getResNo() != ResNo) 97 continue; 98 EVT VT = Node->getValueType(Op.getResNo()); 99 if (VT == MVT::Other || VT == MVT::Flag) 100 continue; 101 Match = false; 102 if (User->isMachineOpcode()) { 103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104 const TargetRegisterClass *RC = 0; 105 if (i+II.getNumDefs() < II.getNumOperands()) 106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107 if (!UseRC) 108 UseRC = RC; 109 else if (RC) { 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111 // If multiple uses expect disjoint register classes, we emit 112 // copies in AddRegisterOperand. 113 if (ComRC) 114 UseRC = ComRC; 115 } 116 } 117 } 118 } 119 MatchReg &= Match; 120 if (VRBase) 121 break; 122 } 123 124 EVT VT = Node->getValueType(ResNo); 125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 127 128 // Figure out the register class to create for the destreg. 129 if (VRBase) { 130 DstRC = MRI->getRegClass(VRBase); 131 } else if (UseRC) { 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133 DstRC = UseRC; 134 } else { 135 DstRC = TLI->getRegClassFor(VT); 136 } 137 138 // If all uses are reading from the src physical register and copying the 139 // register is either impossible or very expensive, then don't create a copy. 140 if (MatchReg && SrcRC->getCopyCost() < 0) { 141 VRBase = SrcReg; 142 } else { 143 // Create the reg, emit the copy. 144 VRBase = MRI->createVirtualRegister(DstRC); 145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 146 DstRC, SrcRC); 147 148 assert(Emitted && "Unable to issue a copy instruction!\n"); 149 (void) Emitted; 150 } 151 152 SDValue Op(Node, ResNo); 153 if (IsClone) 154 VRBaseMap.erase(Op); 155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 156 isNew = isNew; // Silence compiler warning. 157 assert(isNew && "Node emitted out of order - early"); 158} 159 160/// getDstOfCopyToRegUse - If the only use of the specified result number of 161/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163 unsigned ResNo) const { 164 if (!Node->hasOneUse()) 165 return 0; 166 167 SDNode *User = *Node->use_begin(); 168 if (User->getOpcode() == ISD::CopyToReg && 169 User->getOperand(2).getNode() == Node && 170 User->getOperand(2).getResNo() == ResNo) { 171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 172 if (TargetRegisterInfo::isVirtualRegister(Reg)) 173 return Reg; 174 } 175 return 0; 176} 177 178void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179 const TargetInstrDesc &II, 180 bool IsClone, bool IsCloned, 181 DenseMap<SDValue, unsigned> &VRBaseMap) { 182 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 183 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 184 185 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 186 // If the specific node value is only used by a CopyToReg and the dest reg 187 // is a vreg in the same register class, use the CopyToReg'd destination 188 // register instead of creating a new vreg. 189 unsigned VRBase = 0; 190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 191 if (II.OpInfo[i].isOptionalDef()) { 192 // Optional def must be a physical register. 193 unsigned NumResults = CountResults(Node); 194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 196 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 197 } 198 199 if (!VRBase && !IsClone && !IsCloned) 200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201 UI != E; ++UI) { 202 SDNode *User = *UI; 203 if (User->getOpcode() == ISD::CopyToReg && 204 User->getOperand(2).getNode() == Node && 205 User->getOperand(2).getResNo() == i) { 206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209 if (RegRC == RC) { 210 VRBase = Reg; 211 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212 break; 213 } 214 } 215 } 216 } 217 218 // Create the result registers for this node and add the result regs to 219 // the machine instruction. 220 if (VRBase == 0) { 221 assert(RC && "Isn't a register operand!"); 222 VRBase = MRI->createVirtualRegister(RC); 223 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 224 } 225 226 SDValue Op(Node, i); 227 if (IsClone) 228 VRBaseMap.erase(Op); 229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 230 isNew = isNew; // Silence compiler warning. 231 assert(isNew && "Node emitted out of order - early"); 232 } 233} 234 235/// getVR - Return the virtual register corresponding to the specified result 236/// of the specified node. 237unsigned InstrEmitter::getVR(SDValue Op, 238 DenseMap<SDValue, unsigned> &VRBaseMap) { 239 if (Op.isMachineOpcode() && 240 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 241 // Add an IMPLICIT_DEF instruction before every use. 242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 244 // does not include operand register class info. 245 if (!VReg) { 246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247 VReg = MRI->createVirtualRegister(RC); 248 } 249 BuildMI(MBB, Op.getDebugLoc(), 250 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 251 return VReg; 252 } 253 254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 255 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 256 return I->second; 257} 258 259 260/// AddRegisterOperand - Add the specified register as an operand to the 261/// specified machine instr. Insert register copies if the register is 262/// not in the required register class. 263void 264InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265 unsigned IIOpNum, 266 const TargetInstrDesc *II, 267 DenseMap<SDValue, unsigned> &VRBaseMap) { 268 assert(Op.getValueType() != MVT::Other && 269 Op.getValueType() != MVT::Flag && 270 "Chain and flag operands should occur at end of operand list!"); 271 // Get/emit the operand. 272 unsigned VReg = getVR(Op, VRBaseMap); 273 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 274 275 const TargetInstrDesc &TID = MI->getDesc(); 276 bool isOptDef = IIOpNum < TID.getNumOperands() && 277 TID.OpInfo[IIOpNum].isOptionalDef(); 278 279 // If the instruction requires a register in a different class, create 280 // a new virtual register and copy the value into it. 281 if (II) { 282 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 283 const TargetRegisterClass *DstRC = 0; 284 if (IIOpNum < II->getNumOperands()) 285 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 286 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 287 "Don't have operand info for this instruction!"); 288 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 289 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 290 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 291 DstRC, SrcRC); 292 assert(Emitted && "Unable to issue a copy instruction!\n"); 293 (void) Emitted; 294 VReg = NewVReg; 295 } 296 } 297 298 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); 299} 300 301/// AddOperand - Add the specified operand to the specified machine instr. II 302/// specifies the instruction information for the node, and IIOpNum is the 303/// operand number (in the II) that we are adding. IIOpNum and II are used for 304/// assertions only. 305void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 306 unsigned IIOpNum, 307 const TargetInstrDesc *II, 308 DenseMap<SDValue, unsigned> &VRBaseMap) { 309 if (Op.isMachineOpcode()) { 310 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap); 311 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 312 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 313 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 314 const ConstantFP *CFP = F->getConstantFPValue(); 315 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 316 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 317 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 318 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 319 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 320 TGA->getTargetFlags())); 321 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 322 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 323 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 324 MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 325 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 326 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 327 JT->getTargetFlags())); 328 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 329 int Offset = CP->getOffset(); 330 unsigned Align = CP->getAlignment(); 331 const Type *Type = CP->getType(); 332 // MachineConstantPool wants an explicit alignment. 333 if (Align == 0) { 334 Align = TM->getTargetData()->getPrefTypeAlignment(Type); 335 if (Align == 0) { 336 // Alignment of vector types. FIXME! 337 Align = TM->getTargetData()->getTypeAllocSize(Type); 338 } 339 } 340 341 unsigned Idx; 342 MachineConstantPool *MCP = MF->getConstantPool(); 343 if (CP->isMachineConstantPoolEntry()) 344 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 345 else 346 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 347 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 348 CP->getTargetFlags())); 349 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 350 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 351 ES->getTargetFlags())); 352 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 353 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 354 BA->getTargetFlags())); 355 } else { 356 assert(Op.getValueType() != MVT::Other && 357 Op.getValueType() != MVT::Flag && 358 "Chain and flag operands should occur at end of operand list!"); 359 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap); 360 } 361} 362 363/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 364/// "SubIdx"'th sub-register class is the specified register class and whose 365/// type matches the specified type. 366static const TargetRegisterClass* 367getSuperRegisterRegClass(const TargetRegisterClass *TRC, 368 unsigned SubIdx, EVT VT) { 369 // Pick the register class of the superegister for this type 370 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 371 E = TRC->superregclasses_end(); I != E; ++I) 372 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 373 return *I; 374 assert(false && "Couldn't find the register class"); 375 return 0; 376} 377 378/// EmitSubregNode - Generate machine code for subreg nodes. 379/// 380void InstrEmitter::EmitSubregNode(SDNode *Node, 381 DenseMap<SDValue, unsigned> &VRBaseMap){ 382 unsigned VRBase = 0; 383 unsigned Opc = Node->getMachineOpcode(); 384 385 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 386 // the CopyToReg'd destination register instead of creating a new vreg. 387 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 388 UI != E; ++UI) { 389 SDNode *User = *UI; 390 if (User->getOpcode() == ISD::CopyToReg && 391 User->getOperand(2).getNode() == Node) { 392 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 393 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 394 VRBase = DestReg; 395 break; 396 } 397 } 398 } 399 400 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 401 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 402 403 // Create the extract_subreg machine instruction. 404 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 405 TII->get(TargetOpcode::EXTRACT_SUBREG)); 406 407 // Figure out the register class to create for the destreg. 408 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 409 const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 410 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 411 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 412 413 // Figure out the register class to create for the destreg. 414 // Note that if we're going to directly use an existing register, 415 // it must be precisely the required class, and not a subclass 416 // thereof. 417 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 418 // Create the reg 419 assert(SRC && "Couldn't find source register class"); 420 VRBase = MRI->createVirtualRegister(SRC); 421 } 422 423 // Add def, source, and subreg index 424 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 425 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); 426 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 427 MBB->insert(InsertPos, MI); 428 } else if (Opc == TargetOpcode::INSERT_SUBREG || 429 Opc == TargetOpcode::SUBREG_TO_REG) { 430 SDValue N0 = Node->getOperand(0); 431 SDValue N1 = Node->getOperand(1); 432 SDValue N2 = Node->getOperand(2); 433 unsigned SubReg = getVR(N1, VRBaseMap); 434 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 435 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 436 const TargetRegisterClass *SRC = 437 getSuperRegisterRegClass(TRC, SubIdx, 438 Node->getValueType(0)); 439 440 // Figure out the register class to create for the destreg. 441 // Note that if we're going to directly use an existing register, 442 // it must be precisely the required class, and not a subclass 443 // thereof. 444 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 445 // Create the reg 446 assert(SRC && "Couldn't find source register class"); 447 VRBase = MRI->createVirtualRegister(SRC); 448 } 449 450 // Create the insert_subreg or subreg_to_reg machine instruction. 451 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 452 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 453 454 // If creating a subreg_to_reg, then the first input operand 455 // is an implicit value immediate, otherwise it's a register 456 if (Opc == TargetOpcode::SUBREG_TO_REG) { 457 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 458 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 459 } else 460 AddOperand(MI, N0, 0, 0, VRBaseMap); 461 // Add the subregster being inserted 462 AddOperand(MI, N1, 0, 0, VRBaseMap); 463 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 464 MBB->insert(InsertPos, MI); 465 } else 466 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 467 468 SDValue Op(Node, 0); 469 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 470 isNew = isNew; // Silence compiler warning. 471 assert(isNew && "Node emitted out of order - early"); 472} 473 474/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 475/// COPY_TO_REGCLASS is just a normal copy, except that the destination 476/// register is constrained to be in a particular register class. 477/// 478void 479InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 480 DenseMap<SDValue, unsigned> &VRBaseMap) { 481 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 482 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 483 484 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 485 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 486 487 // Create the new VReg in the destination class and emit a copy. 488 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 489 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 490 DstRC, SrcRC); 491 assert(Emitted && 492 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 493 (void) Emitted; 494 495 SDValue Op(Node, 0); 496 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 497 isNew = isNew; // Silence compiler warning. 498 assert(isNew && "Node emitted out of order - early"); 499} 500 501/// EmitDbgValue - Generate any debug info that refers to this Node. Constant 502/// dbg_value is not handled here. 503void 504InstrEmitter::EmitDbgValue(SDNode *Node, 505 DenseMap<SDValue, unsigned> &VRBaseMap, 506 SDDbgValue *sd) { 507 if (!Node->getHasDebugValue()) 508 return; 509 if (!sd) 510 return; 511 unsigned VReg = getVR(SDValue(sd->getSDNode(), sd->getResNo()), VRBaseMap); 512 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 513 DebugLoc DL = sd->getDebugLoc(); 514 MachineInstr *MI; 515 if (VReg) { 516 MI = BuildMI(*MF, DL, II).addReg(VReg, RegState::Debug). 517 addImm(sd->getOffset()). 518 addMetadata(sd->getMDPtr()); 519 } else { 520 // Insert an Undef so we can see what we dropped. 521 MI = BuildMI(*MF, DL, II).addReg(0U).addImm(sd->getOffset()). 522 addMetadata(sd->getMDPtr()); 523 } 524 MBB->insert(InsertPos, MI); 525} 526 527/// EmitDbgValue - Generate constant debug info. No SDNode is involved. 528void 529InstrEmitter::EmitDbgValue(SDDbgValue *sd) { 530 if (!sd) 531 return; 532 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 533 DebugLoc DL = sd->getDebugLoc(); 534 MachineInstr *MI; 535 Value *V = sd->getConst(); 536 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 537 MI = BuildMI(*MF, DL, II).addImm(CI->getZExtValue()). 538 addImm(sd->getOffset()). 539 addMetadata(sd->getMDPtr()); 540 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 541 MI = BuildMI(*MF, DL, II).addFPImm(CF).addImm(sd->getOffset()). 542 addMetadata(sd->getMDPtr()); 543 } else { 544 // Insert an Undef so we can see what we dropped. 545 MI = BuildMI(*MF, DL, II).addReg(0U).addImm(sd->getOffset()). 546 addMetadata(sd->getMDPtr()); 547 } 548 MBB->insert(InsertPos, MI); 549} 550 551/// EmitNode - Generate machine code for a node and needed dependencies. 552/// 553void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 554 DenseMap<SDValue, unsigned> &VRBaseMap, 555 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) { 556 // If machine instruction 557 if (Node->isMachineOpcode()) { 558 unsigned Opc = Node->getMachineOpcode(); 559 560 // Handle subreg insert/extract specially 561 if (Opc == TargetOpcode::EXTRACT_SUBREG || 562 Opc == TargetOpcode::INSERT_SUBREG || 563 Opc == TargetOpcode::SUBREG_TO_REG) { 564 EmitSubregNode(Node, VRBaseMap); 565 return; 566 } 567 568 // Handle COPY_TO_REGCLASS specially. 569 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 570 EmitCopyToRegClassNode(Node, VRBaseMap); 571 return; 572 } 573 574 if (Opc == TargetOpcode::IMPLICIT_DEF) 575 // We want a unique VR for each IMPLICIT_DEF use. 576 return; 577 578 const TargetInstrDesc &II = TII->get(Opc); 579 unsigned NumResults = CountResults(Node); 580 unsigned NodeOperands = CountOperands(Node); 581 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && 582 II.getImplicitDefs() != 0; 583#ifndef NDEBUG 584 unsigned NumMIOperands = NodeOperands + NumResults; 585 assert((II.getNumOperands() == NumMIOperands || 586 HasPhysRegOuts || II.isVariadic()) && 587 "#operands for dag node doesn't match .td file!"); 588#endif 589 590 // Create the new machine instruction. 591 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 592 593 // Add result register values for things that are defined by this 594 // instruction. 595 if (NumResults) 596 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 597 598 // Emit all of the actual operands of this instruction, adding them to the 599 // instruction as appropriate. 600 bool HasOptPRefs = II.getNumDefs() > NumResults; 601 assert((!HasOptPRefs || !HasPhysRegOuts) && 602 "Unable to cope with optional defs and phys regs defs!"); 603 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 604 for (unsigned i = NumSkip; i != NodeOperands; ++i) 605 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 606 VRBaseMap); 607 608 // Transfer all of the memory reference descriptions of this instruction. 609 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 610 cast<MachineSDNode>(Node)->memoperands_end()); 611 612 if (II.usesCustomInsertionHook()) { 613 // Insert this instruction into the basic block using a target 614 // specific inserter which may returns a new basic block. 615 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM); 616 InsertPos = MBB->end(); 617 } else { 618 MBB->insert(InsertPos, MI); 619 } 620 621 // Additional results must be an physical register def. 622 if (HasPhysRegOuts) { 623 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 624 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 625 if (Node->hasAnyUseOfValue(i)) 626 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 627 // If there are no uses, mark the register as dead now, so that 628 // MachineLICM/Sink can see that it's dead. Don't do this if the 629 // node has a Flag value, for the benefit of targets still using 630 // Flag for values in physregs. 631 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 632 MI->addRegisterDead(Reg, TRI); 633 } 634 } 635 return; 636 } 637 638 switch (Node->getOpcode()) { 639 default: 640#ifndef NDEBUG 641 Node->dump(); 642#endif 643 llvm_unreachable("This target-independent node should have been selected!"); 644 break; 645 case ISD::EntryToken: 646 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 647 break; 648 case ISD::MERGE_VALUES: 649 case ISD::TokenFactor: // fall thru 650 break; 651 case ISD::CopyToReg: { 652 unsigned SrcReg; 653 SDValue SrcVal = Node->getOperand(2); 654 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 655 SrcReg = R->getReg(); 656 else 657 SrcReg = getVR(SrcVal, VRBaseMap); 658 659 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 660 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 661 break; 662 663 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 664 // Get the register classes of the src/dst. 665 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 666 SrcTRC = MRI->getRegClass(SrcReg); 667 else 668 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 669 670 if (TargetRegisterInfo::isVirtualRegister(DestReg)) 671 DstTRC = MRI->getRegClass(DestReg); 672 else 673 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 674 Node->getOperand(1).getValueType()); 675 676 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 677 DstTRC, SrcTRC); 678 assert(Emitted && "Unable to issue a copy instruction!\n"); 679 (void) Emitted; 680 break; 681 } 682 case ISD::CopyFromReg: { 683 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 684 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 685 break; 686 } 687 case ISD::INLINEASM: { 688 unsigned NumOps = Node->getNumOperands(); 689 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 690 --NumOps; // Ignore the flag operand. 691 692 // Create the inline asm machine instruction. 693 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 694 TII->get(TargetOpcode::INLINEASM)); 695 696 // Add the asm string as an external symbol operand. 697 const char *AsmStr = 698 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol(); 699 MI->addOperand(MachineOperand::CreateES(AsmStr)); 700 701 // Add all of the operand registers to the instruction. 702 for (unsigned i = 2; i != NumOps;) { 703 unsigned Flags = 704 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 705 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 706 707 MI->addOperand(MachineOperand::CreateImm(Flags)); 708 ++i; // Skip the ID value. 709 710 switch (Flags & 7) { 711 default: llvm_unreachable("Bad flags!"); 712 case 2: // Def of register. 713 for (; NumVals; --NumVals, ++i) { 714 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 715 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 716 } 717 break; 718 case 6: // Def of earlyclobber register. 719 for (; NumVals; --NumVals, ++i) { 720 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 721 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 722 false, false, true)); 723 } 724 break; 725 case 1: // Use of register. 726 case 3: // Immediate. 727 case 4: // Addressing mode. 728 // The addressing mode has been selected, just add all of the 729 // operands to the machine instruction. 730 for (; NumVals; --NumVals, ++i) 731 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 732 break; 733 } 734 } 735 MBB->insert(InsertPos, MI); 736 break; 737 } 738 } 739} 740 741/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 742/// at the given position in the given block. 743InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 744 MachineBasicBlock::iterator insertpos) 745 : MF(mbb->getParent()), 746 MRI(&MF->getRegInfo()), 747 TM(&MF->getTarget()), 748 TII(TM->getInstrInfo()), 749 TRI(TM->getRegisterInfo()), 750 TLI(TM->getTargetLowering()), 751 MBB(mbb), InsertPos(insertpos) { 752} 753