InstrEmitter.cpp revision 29cbade25aa094ca9a149a96a8614cf6f3247480
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "llvm/CodeGen/MachineConstantPool.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineRegisterInfo.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetInstrInfo.h" 25#include "llvm/Target/TargetLowering.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33/// CountResults - The results of target nodes have register or immediate 34/// operands first, then an optional chain, and optional flag operands (which do 35/// not go into the resulting MachineInstr). 36unsigned InstrEmitter::CountResults(SDNode *Node) { 37 unsigned N = Node->getNumValues(); 38 while (N && Node->getValueType(N - 1) == MVT::Flag) 39 --N; 40 if (N && Node->getValueType(N - 1) == MVT::Other) 41 --N; // Skip over chain result. 42 return N; 43} 44 45/// CountOperands - The inputs to target nodes have any actual inputs first, 46/// followed by an optional chain operand, then an optional flag operand. 47/// Compute the number of actual operands that will go into the resulting 48/// MachineInstr. 49unsigned InstrEmitter::CountOperands(SDNode *Node) { 50 unsigned N = Node->getNumOperands(); 51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52 --N; 53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54 --N; // Ignore chain if it exists. 55 return N; 56} 57 58/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59/// implicit physical register output. 60void InstrEmitter:: 61EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63 unsigned VRBase = 0; 64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65 // Just use the input register directly! 66 SDValue Op(Node, ResNo); 67 if (IsClone) 68 VRBaseMap.erase(Op); 69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70 isNew = isNew; // Silence compiler warning. 71 assert(isNew && "Node emitted out of order - early"); 72 return; 73 } 74 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76 // the CopyToReg'd destination register instead of creating a new vreg. 77 bool MatchReg = true; 78 const TargetRegisterClass *UseRC = NULL; 79 if (!IsClone && !IsCloned) 80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81 UI != E; ++UI) { 82 SDNode *User = *UI; 83 bool Match = true; 84 if (User->getOpcode() == ISD::CopyToReg && 85 User->getOperand(2).getNode() == Node && 86 User->getOperand(2).getResNo() == ResNo) { 87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89 VRBase = DestReg; 90 Match = false; 91 } else if (DestReg != SrcReg) 92 Match = false; 93 } else { 94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95 SDValue Op = User->getOperand(i); 96 if (Op.getNode() != Node || Op.getResNo() != ResNo) 97 continue; 98 EVT VT = Node->getValueType(Op.getResNo()); 99 if (VT == MVT::Other || VT == MVT::Flag) 100 continue; 101 Match = false; 102 if (User->isMachineOpcode()) { 103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104 const TargetRegisterClass *RC = 0; 105 if (i+II.getNumDefs() < II.getNumOperands()) 106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107 if (!UseRC) 108 UseRC = RC; 109 else if (RC) { 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111 // If multiple uses expect disjoint register classes, we emit 112 // copies in AddRegisterOperand. 113 if (ComRC) 114 UseRC = ComRC; 115 } 116 } 117 } 118 } 119 MatchReg &= Match; 120 if (VRBase) 121 break; 122 } 123 124 EVT VT = Node->getValueType(ResNo); 125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 127 128 // Figure out the register class to create for the destreg. 129 if (VRBase) { 130 DstRC = MRI->getRegClass(VRBase); 131 } else if (UseRC) { 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133 DstRC = UseRC; 134 } else { 135 DstRC = TLI->getRegClassFor(VT); 136 } 137 138 // If all uses are reading from the src physical register and copying the 139 // register is either impossible or very expensive, then don't create a copy. 140 if (MatchReg && SrcRC->getCopyCost() < 0) { 141 VRBase = SrcReg; 142 } else { 143 // Create the reg, emit the copy. 144 VRBase = MRI->createVirtualRegister(DstRC); 145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 146 DstRC, SrcRC); 147 148 assert(Emitted && "Unable to issue a copy instruction!\n"); 149 (void) Emitted; 150 } 151 152 SDValue Op(Node, ResNo); 153 if (IsClone) 154 VRBaseMap.erase(Op); 155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 156 isNew = isNew; // Silence compiler warning. 157 assert(isNew && "Node emitted out of order - early"); 158} 159 160/// getDstOfCopyToRegUse - If the only use of the specified result number of 161/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163 unsigned ResNo) const { 164 if (!Node->hasOneUse()) 165 return 0; 166 167 SDNode *User = *Node->use_begin(); 168 if (User->getOpcode() == ISD::CopyToReg && 169 User->getOperand(2).getNode() == Node && 170 User->getOperand(2).getResNo() == ResNo) { 171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 172 if (TargetRegisterInfo::isVirtualRegister(Reg)) 173 return Reg; 174 } 175 return 0; 176} 177 178void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179 const TargetInstrDesc &II, 180 bool IsClone, bool IsCloned, 181 DenseMap<SDValue, unsigned> &VRBaseMap) { 182 assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF && 183 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 184 185 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 186 // If the specific node value is only used by a CopyToReg and the dest reg 187 // is a vreg in the same register class, use the CopyToReg'd destination 188 // register instead of creating a new vreg. 189 unsigned VRBase = 0; 190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 191 if (II.OpInfo[i].isOptionalDef()) { 192 // Optional def must be a physical register. 193 unsigned NumResults = CountResults(Node); 194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 196 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 197 } 198 199 if (!VRBase && !IsClone && !IsCloned) 200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201 UI != E; ++UI) { 202 SDNode *User = *UI; 203 if (User->getOpcode() == ISD::CopyToReg && 204 User->getOperand(2).getNode() == Node && 205 User->getOperand(2).getResNo() == i) { 206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209 if (RegRC == RC) { 210 VRBase = Reg; 211 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212 break; 213 } 214 } 215 } 216 } 217 218 // Create the result registers for this node and add the result regs to 219 // the machine instruction. 220 if (VRBase == 0) { 221 assert(RC && "Isn't a register operand!"); 222 VRBase = MRI->createVirtualRegister(RC); 223 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 224 } 225 226 SDValue Op(Node, i); 227 if (IsClone) 228 VRBaseMap.erase(Op); 229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 230 isNew = isNew; // Silence compiler warning. 231 assert(isNew && "Node emitted out of order - early"); 232 } 233} 234 235/// getVR - Return the virtual register corresponding to the specified result 236/// of the specified node. 237unsigned InstrEmitter::getVR(SDValue Op, 238 DenseMap<SDValue, unsigned> &VRBaseMap) { 239 if (Op.isMachineOpcode() && 240 Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) { 241 // Add an IMPLICIT_DEF instruction before every use. 242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 244 // does not include operand register class info. 245 if (!VReg) { 246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247 VReg = MRI->createVirtualRegister(RC); 248 } 249 BuildMI(MBB, Op.getDebugLoc(), 250 TII->get(TargetInstrInfo::IMPLICIT_DEF), VReg); 251 return VReg; 252 } 253 254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 255 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 256 return I->second; 257} 258 259 260/// AddRegisterOperand - Add the specified register as an operand to the 261/// specified machine instr. Insert register copies if the register is 262/// not in the required register class. 263void 264InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265 unsigned IIOpNum, 266 const TargetInstrDesc *II, 267 DenseMap<SDValue, unsigned> &VRBaseMap) { 268 assert(Op.getValueType() != MVT::Other && 269 Op.getValueType() != MVT::Flag && 270 "Chain and flag operands should occur at end of operand list!"); 271 // Get/emit the operand. 272 unsigned VReg = getVR(Op, VRBaseMap); 273 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 274 275 const TargetInstrDesc &TID = MI->getDesc(); 276 bool isOptDef = IIOpNum < TID.getNumOperands() && 277 TID.OpInfo[IIOpNum].isOptionalDef(); 278 279 // If the instruction requires a register in a different class, create 280 // a new virtual register and copy the value into it. 281 if (II) { 282 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 283 const TargetRegisterClass *DstRC = 0; 284 if (IIOpNum < II->getNumOperands()) 285 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 286 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 287 "Don't have operand info for this instruction!"); 288 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 289 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 290 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 291 DstRC, SrcRC); 292 assert(Emitted && "Unable to issue a copy instruction!\n"); 293 (void) Emitted; 294 VReg = NewVReg; 295 } 296 } 297 298 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); 299} 300 301/// AddOperand - Add the specified operand to the specified machine instr. II 302/// specifies the instruction information for the node, and IIOpNum is the 303/// operand number (in the II) that we are adding. IIOpNum and II are used for 304/// assertions only. 305void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 306 unsigned IIOpNum, 307 const TargetInstrDesc *II, 308 DenseMap<SDValue, unsigned> &VRBaseMap) { 309 if (Op.isMachineOpcode()) { 310 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap); 311 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 312 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 313 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 314 const ConstantFP *CFP = F->getConstantFPValue(); 315 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 316 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 317 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 318 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 319 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 320 TGA->getTargetFlags())); 321 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 322 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 323 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 324 MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 325 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 326 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 327 JT->getTargetFlags())); 328 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 329 int Offset = CP->getOffset(); 330 unsigned Align = CP->getAlignment(); 331 const Type *Type = CP->getType(); 332 // MachineConstantPool wants an explicit alignment. 333 if (Align == 0) { 334 Align = TM->getTargetData()->getPrefTypeAlignment(Type); 335 if (Align == 0) { 336 // Alignment of vector types. FIXME! 337 Align = TM->getTargetData()->getTypeAllocSize(Type); 338 } 339 } 340 341 unsigned Idx; 342 MachineConstantPool *MCP = MF->getConstantPool(); 343 if (CP->isMachineConstantPoolEntry()) 344 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 345 else 346 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 347 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 348 CP->getTargetFlags())); 349 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 350 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 351 ES->getTargetFlags())); 352 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 353 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 354 BA->getTargetFlags())); 355 } else { 356 assert(Op.getValueType() != MVT::Other && 357 Op.getValueType() != MVT::Flag && 358 "Chain and flag operands should occur at end of operand list!"); 359 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap); 360 } 361} 362 363/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 364/// "SubIdx"'th sub-register class is the specified register class and whose 365/// type matches the specified type. 366static const TargetRegisterClass* 367getSuperRegisterRegClass(const TargetRegisterClass *TRC, 368 unsigned SubIdx, EVT VT) { 369 // Pick the register class of the superegister for this type 370 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 371 E = TRC->superregclasses_end(); I != E; ++I) 372 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 373 return *I; 374 assert(false && "Couldn't find the register class"); 375 return 0; 376} 377 378/// EmitSubregNode - Generate machine code for subreg nodes. 379/// 380void InstrEmitter::EmitSubregNode(SDNode *Node, 381 DenseMap<SDValue, unsigned> &VRBaseMap){ 382 unsigned VRBase = 0; 383 unsigned Opc = Node->getMachineOpcode(); 384 385 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 386 // the CopyToReg'd destination register instead of creating a new vreg. 387 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 388 UI != E; ++UI) { 389 SDNode *User = *UI; 390 if (User->getOpcode() == ISD::CopyToReg && 391 User->getOperand(2).getNode() == Node) { 392 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 393 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 394 VRBase = DestReg; 395 break; 396 } 397 } 398 } 399 400 if (Opc == TargetInstrInfo::EXTRACT_SUBREG) { 401 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 402 403 // Create the extract_subreg machine instruction. 404 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 405 TII->get(TargetInstrInfo::EXTRACT_SUBREG)); 406 407 // Figure out the register class to create for the destreg. 408 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 409 const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 410 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 411 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 412 413 // Figure out the register class to create for the destreg. 414 // Note that if we're going to directly use an existing register, 415 // it must be precisely the required class, and not a subclass 416 // thereof. 417 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 418 // Create the reg 419 assert(SRC && "Couldn't find source register class"); 420 VRBase = MRI->createVirtualRegister(SRC); 421 } 422 423 // Add def, source, and subreg index 424 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 425 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); 426 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 427 MBB->insert(InsertPos, MI); 428 } else if (Opc == TargetInstrInfo::INSERT_SUBREG || 429 Opc == TargetInstrInfo::SUBREG_TO_REG) { 430 SDValue N0 = Node->getOperand(0); 431 SDValue N1 = Node->getOperand(1); 432 SDValue N2 = Node->getOperand(2); 433 unsigned SubReg = getVR(N1, VRBaseMap); 434 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 435 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 436 const TargetRegisterClass *SRC = 437 getSuperRegisterRegClass(TRC, SubIdx, 438 Node->getValueType(0)); 439 440 // Figure out the register class to create for the destreg. 441 // Note that if we're going to directly use an existing register, 442 // it must be precisely the required class, and not a subclass 443 // thereof. 444 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 445 // Create the reg 446 assert(SRC && "Couldn't find source register class"); 447 VRBase = MRI->createVirtualRegister(SRC); 448 } 449 450 // Create the insert_subreg or subreg_to_reg machine instruction. 451 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 452 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 453 454 // If creating a subreg_to_reg, then the first input operand 455 // is an implicit value immediate, otherwise it's a register 456 if (Opc == TargetInstrInfo::SUBREG_TO_REG) { 457 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 458 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 459 } else 460 AddOperand(MI, N0, 0, 0, VRBaseMap); 461 // Add the subregster being inserted 462 AddOperand(MI, N1, 0, 0, VRBaseMap); 463 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 464 MBB->insert(InsertPos, MI); 465 } else 466 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 467 468 SDValue Op(Node, 0); 469 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 470 isNew = isNew; // Silence compiler warning. 471 assert(isNew && "Node emitted out of order - early"); 472} 473 474/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 475/// COPY_TO_REGCLASS is just a normal copy, except that the destination 476/// register is constrained to be in a particular register class. 477/// 478void 479InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 480 DenseMap<SDValue, unsigned> &VRBaseMap) { 481 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 482 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 483 484 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 485 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 486 487 // Create the new VReg in the destination class and emit a copy. 488 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 489 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 490 DstRC, SrcRC); 491 assert(Emitted && 492 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 493 (void) Emitted; 494 495 SDValue Op(Node, 0); 496 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 497 isNew = isNew; // Silence compiler warning. 498 assert(isNew && "Node emitted out of order - early"); 499} 500 501/// EmitNode - Generate machine code for a node and needed dependencies. 502/// 503void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 504 DenseMap<SDValue, unsigned> &VRBaseMap, 505 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) { 506 // If machine instruction 507 if (Node->isMachineOpcode()) { 508 unsigned Opc = Node->getMachineOpcode(); 509 510 // Handle subreg insert/extract specially 511 if (Opc == TargetInstrInfo::EXTRACT_SUBREG || 512 Opc == TargetInstrInfo::INSERT_SUBREG || 513 Opc == TargetInstrInfo::SUBREG_TO_REG) { 514 EmitSubregNode(Node, VRBaseMap); 515 return; 516 } 517 518 // Handle COPY_TO_REGCLASS specially. 519 if (Opc == TargetInstrInfo::COPY_TO_REGCLASS) { 520 EmitCopyToRegClassNode(Node, VRBaseMap); 521 return; 522 } 523 524 if (Opc == TargetInstrInfo::IMPLICIT_DEF) 525 // We want a unique VR for each IMPLICIT_DEF use. 526 return; 527 528 const TargetInstrDesc &II = TII->get(Opc); 529 unsigned NumResults = CountResults(Node); 530 unsigned NodeOperands = CountOperands(Node); 531 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && 532 II.getImplicitDefs() != 0; 533#ifndef NDEBUG 534 unsigned NumMIOperands = NodeOperands + NumResults; 535 assert((II.getNumOperands() == NumMIOperands || 536 HasPhysRegOuts || II.isVariadic()) && 537 "#operands for dag node doesn't match .td file!"); 538#endif 539 540 // Create the new machine instruction. 541 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 542 543 // Add result register values for things that are defined by this 544 // instruction. 545 if (NumResults) 546 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 547 548 // Emit all of the actual operands of this instruction, adding them to the 549 // instruction as appropriate. 550 bool HasOptPRefs = II.getNumDefs() > NumResults; 551 assert((!HasOptPRefs || !HasPhysRegOuts) && 552 "Unable to cope with optional defs and phys regs defs!"); 553 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 554 for (unsigned i = NumSkip; i != NodeOperands; ++i) 555 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 556 VRBaseMap); 557 558 // Transfer all of the memory reference descriptions of this instruction. 559 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 560 cast<MachineSDNode>(Node)->memoperands_end()); 561 562 if (II.usesCustomInsertionHook()) { 563 // Insert this instruction into the basic block using a target 564 // specific inserter which may returns a new basic block. 565 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM); 566 InsertPos = MBB->end(); 567 } else { 568 MBB->insert(InsertPos, MI); 569 } 570 571 // Additional results must be an physical register def. 572 if (HasPhysRegOuts) { 573 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 574 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 575 if (Node->hasAnyUseOfValue(i)) 576 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 577 // If there are no uses, mark the register as dead now, so that 578 // MachineLICM/Sink can see that it's dead. Don't do this if the 579 // node has a Flag value, for the benefit of targets still using 580 // Flag for values in physregs. 581 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 582 MI->addRegisterDead(Reg, TRI); 583 } 584 } 585 return; 586 } 587 588 switch (Node->getOpcode()) { 589 default: 590#ifndef NDEBUG 591 Node->dump(); 592#endif 593 llvm_unreachable("This target-independent node should have been selected!"); 594 break; 595 case ISD::EntryToken: 596 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 597 break; 598 case ISD::MERGE_VALUES: 599 case ISD::TokenFactor: // fall thru 600 break; 601 case ISD::CopyToReg: { 602 unsigned SrcReg; 603 SDValue SrcVal = Node->getOperand(2); 604 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 605 SrcReg = R->getReg(); 606 else 607 SrcReg = getVR(SrcVal, VRBaseMap); 608 609 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 610 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 611 break; 612 613 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 614 // Get the register classes of the src/dst. 615 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 616 SrcTRC = MRI->getRegClass(SrcReg); 617 else 618 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 619 620 if (TargetRegisterInfo::isVirtualRegister(DestReg)) 621 DstTRC = MRI->getRegClass(DestReg); 622 else 623 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 624 Node->getOperand(1).getValueType()); 625 626 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 627 DstTRC, SrcTRC); 628 assert(Emitted && "Unable to issue a copy instruction!\n"); 629 (void) Emitted; 630 break; 631 } 632 case ISD::CopyFromReg: { 633 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 634 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 635 break; 636 } 637 case ISD::INLINEASM: { 638 unsigned NumOps = Node->getNumOperands(); 639 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 640 --NumOps; // Ignore the flag operand. 641 642 // Create the inline asm machine instruction. 643 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 644 TII->get(TargetInstrInfo::INLINEASM)); 645 646 // Add the asm string as an external symbol operand. 647 const char *AsmStr = 648 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol(); 649 MI->addOperand(MachineOperand::CreateES(AsmStr)); 650 651 // Add all of the operand registers to the instruction. 652 for (unsigned i = 2; i != NumOps;) { 653 unsigned Flags = 654 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 655 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 656 657 MI->addOperand(MachineOperand::CreateImm(Flags)); 658 ++i; // Skip the ID value. 659 660 switch (Flags & 7) { 661 default: llvm_unreachable("Bad flags!"); 662 case 2: // Def of register. 663 for (; NumVals; --NumVals, ++i) { 664 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 665 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 666 } 667 break; 668 case 6: // Def of earlyclobber register. 669 for (; NumVals; --NumVals, ++i) { 670 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 671 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 672 false, false, true)); 673 } 674 break; 675 case 1: // Use of register. 676 case 3: // Immediate. 677 case 4: // Addressing mode. 678 // The addressing mode has been selected, just add all of the 679 // operands to the machine instruction. 680 for (; NumVals; --NumVals, ++i) 681 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 682 break; 683 } 684 } 685 MBB->insert(InsertPos, MI); 686 break; 687 } 688 } 689} 690 691/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 692/// at the given position in the given block. 693InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 694 MachineBasicBlock::iterator insertpos) 695 : MF(mbb->getParent()), 696 MRI(&MF->getRegInfo()), 697 TM(&MF->getTarget()), 698 TII(TM->getInstrInfo()), 699 TRI(TM->getRegisterInfo()), 700 TLI(TM->getTargetLowering()), 701 MBB(mbb), InsertPos(insertpos) { 702} 703