InstrEmitter.cpp revision 891ff8fbd61a06ef8ea57461fa377ebbb663ed09
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "SDNodeDbgValue.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetLowering.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33/// CountResults - The results of target nodes have register or immediate 34/// operands first, then an optional chain, and optional flag operands (which do 35/// not go into the resulting MachineInstr). 36unsigned InstrEmitter::CountResults(SDNode *Node) { 37 unsigned N = Node->getNumValues(); 38 while (N && Node->getValueType(N - 1) == MVT::Flag) 39 --N; 40 if (N && Node->getValueType(N - 1) == MVT::Other) 41 --N; // Skip over chain result. 42 return N; 43} 44 45/// CountOperands - The inputs to target nodes have any actual inputs first, 46/// followed by an optional chain operand, then an optional flag operand. 47/// Compute the number of actual operands that will go into the resulting 48/// MachineInstr. 49unsigned InstrEmitter::CountOperands(SDNode *Node) { 50 unsigned N = Node->getNumOperands(); 51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52 --N; 53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54 --N; // Ignore chain if it exists. 55 return N; 56} 57 58/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59/// implicit physical register output. 60void InstrEmitter:: 61EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63 unsigned VRBase = 0; 64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65 // Just use the input register directly! 66 SDValue Op(Node, ResNo); 67 if (IsClone) 68 VRBaseMap.erase(Op); 69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70 isNew = isNew; // Silence compiler warning. 71 assert(isNew && "Node emitted out of order - early"); 72 return; 73 } 74 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76 // the CopyToReg'd destination register instead of creating a new vreg. 77 bool MatchReg = true; 78 const TargetRegisterClass *UseRC = NULL; 79 if (!IsClone && !IsCloned) 80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81 UI != E; ++UI) { 82 SDNode *User = *UI; 83 bool Match = true; 84 if (User->getOpcode() == ISD::CopyToReg && 85 User->getOperand(2).getNode() == Node && 86 User->getOperand(2).getResNo() == ResNo) { 87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89 VRBase = DestReg; 90 Match = false; 91 } else if (DestReg != SrcReg) 92 Match = false; 93 } else { 94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95 SDValue Op = User->getOperand(i); 96 if (Op.getNode() != Node || Op.getResNo() != ResNo) 97 continue; 98 EVT VT = Node->getValueType(Op.getResNo()); 99 if (VT == MVT::Other || VT == MVT::Flag) 100 continue; 101 Match = false; 102 if (User->isMachineOpcode()) { 103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104 const TargetRegisterClass *RC = 0; 105 if (i+II.getNumDefs() < II.getNumOperands()) 106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107 if (!UseRC) 108 UseRC = RC; 109 else if (RC) { 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111 // If multiple uses expect disjoint register classes, we emit 112 // copies in AddRegisterOperand. 113 if (ComRC) 114 UseRC = ComRC; 115 } 116 } 117 } 118 } 119 MatchReg &= Match; 120 if (VRBase) 121 break; 122 } 123 124 EVT VT = Node->getValueType(ResNo); 125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 127 128 // Figure out the register class to create for the destreg. 129 if (VRBase) { 130 DstRC = MRI->getRegClass(VRBase); 131 } else if (UseRC) { 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133 DstRC = UseRC; 134 } else { 135 DstRC = TLI->getRegClassFor(VT); 136 } 137 138 // If all uses are reading from the src physical register and copying the 139 // register is either impossible or very expensive, then don't create a copy. 140 if (MatchReg && SrcRC->getCopyCost() < 0) { 141 VRBase = SrcReg; 142 } else { 143 // Create the reg, emit the copy. 144 VRBase = MRI->createVirtualRegister(DstRC); 145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 146 DstRC, SrcRC); 147 148 assert(Emitted && "Unable to issue a copy instruction!\n"); 149 (void) Emitted; 150 } 151 152 SDValue Op(Node, ResNo); 153 if (IsClone) 154 VRBaseMap.erase(Op); 155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 156 isNew = isNew; // Silence compiler warning. 157 assert(isNew && "Node emitted out of order - early"); 158} 159 160/// getDstOfCopyToRegUse - If the only use of the specified result number of 161/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163 unsigned ResNo) const { 164 if (!Node->hasOneUse()) 165 return 0; 166 167 SDNode *User = *Node->use_begin(); 168 if (User->getOpcode() == ISD::CopyToReg && 169 User->getOperand(2).getNode() == Node && 170 User->getOperand(2).getResNo() == ResNo) { 171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 172 if (TargetRegisterInfo::isVirtualRegister(Reg)) 173 return Reg; 174 } 175 return 0; 176} 177 178void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179 const TargetInstrDesc &II, 180 bool IsClone, bool IsCloned, 181 DenseMap<SDValue, unsigned> &VRBaseMap) { 182 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 183 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 184 185 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 186 // If the specific node value is only used by a CopyToReg and the dest reg 187 // is a vreg in the same register class, use the CopyToReg'd destination 188 // register instead of creating a new vreg. 189 unsigned VRBase = 0; 190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 191 if (II.OpInfo[i].isOptionalDef()) { 192 // Optional def must be a physical register. 193 unsigned NumResults = CountResults(Node); 194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 196 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 197 } 198 199 if (!VRBase && !IsClone && !IsCloned) 200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201 UI != E; ++UI) { 202 SDNode *User = *UI; 203 if (User->getOpcode() == ISD::CopyToReg && 204 User->getOperand(2).getNode() == Node && 205 User->getOperand(2).getResNo() == i) { 206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209 if (RegRC == RC) { 210 VRBase = Reg; 211 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212 break; 213 } 214 } 215 } 216 } 217 218 // Create the result registers for this node and add the result regs to 219 // the machine instruction. 220 if (VRBase == 0) { 221 assert(RC && "Isn't a register operand!"); 222 VRBase = MRI->createVirtualRegister(RC); 223 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 224 } 225 226 SDValue Op(Node, i); 227 if (IsClone) 228 VRBaseMap.erase(Op); 229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 230 isNew = isNew; // Silence compiler warning. 231 assert(isNew && "Node emitted out of order - early"); 232 } 233} 234 235/// getVR - Return the virtual register corresponding to the specified result 236/// of the specified node. 237unsigned InstrEmitter::getVR(SDValue Op, 238 DenseMap<SDValue, unsigned> &VRBaseMap) { 239 if (Op.isMachineOpcode() && 240 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 241 // Add an IMPLICIT_DEF instruction before every use. 242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 244 // does not include operand register class info. 245 if (!VReg) { 246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247 VReg = MRI->createVirtualRegister(RC); 248 } 249 BuildMI(MBB, Op.getDebugLoc(), 250 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 251 return VReg; 252 } 253 254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 255 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 256 return I->second; 257} 258 259 260/// AddRegisterOperand - Add the specified register as an operand to the 261/// specified machine instr. Insert register copies if the register is 262/// not in the required register class. 263void 264InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265 unsigned IIOpNum, 266 const TargetInstrDesc *II, 267 DenseMap<SDValue, unsigned> &VRBaseMap, 268 bool IsDebug) { 269 assert(Op.getValueType() != MVT::Other && 270 Op.getValueType() != MVT::Flag && 271 "Chain and flag operands should occur at end of operand list!"); 272 // Get/emit the operand. 273 unsigned VReg = getVR(Op, VRBaseMap); 274 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 275 276 const TargetInstrDesc &TID = MI->getDesc(); 277 bool isOptDef = IIOpNum < TID.getNumOperands() && 278 TID.OpInfo[IIOpNum].isOptionalDef(); 279 280 // If the instruction requires a register in a different class, create 281 // a new virtual register and copy the value into it. 282 if (II) { 283 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 284 const TargetRegisterClass *DstRC = 0; 285 if (IIOpNum < II->getNumOperands()) 286 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 287 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 288 "Don't have operand info for this instruction!"); 289 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 290 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 291 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 292 DstRC, SrcRC); 293 assert(Emitted && "Unable to issue a copy instruction!\n"); 294 (void) Emitted; 295 VReg = NewVReg; 296 } 297 } 298 299#if 0 300 // If this value has only one use, that use is a kill. This is a 301 // conservative approximation. Tied operands are never killed, so we need 302 // to check that. And that means we need to determine the index of the 303 // operand. 304 unsigned Idx = MI->getNumOperands(); 305 while (Idx > 0 && 306 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 307 --Idx; 308 bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1; 309 bool isKill = Op.hasOneUse() && !isTied; 310#else 311 bool isKill = false; 312#endif 313 314 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 315 false/*isImp*/, isKill, 316 false/*isDead*/, false/*isUndef*/, 317 false/*isEarlyClobber*/, 318 0/*SubReg*/, IsDebug)); 319} 320 321/// AddOperand - Add the specified operand to the specified machine instr. II 322/// specifies the instruction information for the node, and IIOpNum is the 323/// operand number (in the II) that we are adding. IIOpNum and II are used for 324/// assertions only. 325void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 326 unsigned IIOpNum, 327 const TargetInstrDesc *II, 328 DenseMap<SDValue, unsigned> &VRBaseMap, 329 bool IsDebug) { 330 if (Op.isMachineOpcode()) { 331 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 332 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 333 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 334 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 335 const ConstantFP *CFP = F->getConstantFPValue(); 336 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 337 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 338 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 339 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 340 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 341 TGA->getTargetFlags())); 342 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 343 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 344 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 345 MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 346 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 347 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 348 JT->getTargetFlags())); 349 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 350 int Offset = CP->getOffset(); 351 unsigned Align = CP->getAlignment(); 352 const Type *Type = CP->getType(); 353 // MachineConstantPool wants an explicit alignment. 354 if (Align == 0) { 355 Align = TM->getTargetData()->getPrefTypeAlignment(Type); 356 if (Align == 0) { 357 // Alignment of vector types. FIXME! 358 Align = TM->getTargetData()->getTypeAllocSize(Type); 359 } 360 } 361 362 unsigned Idx; 363 MachineConstantPool *MCP = MF->getConstantPool(); 364 if (CP->isMachineConstantPoolEntry()) 365 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 366 else 367 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 368 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 369 CP->getTargetFlags())); 370 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 371 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 372 ES->getTargetFlags())); 373 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 374 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 375 BA->getTargetFlags())); 376 } else { 377 assert(Op.getValueType() != MVT::Other && 378 Op.getValueType() != MVT::Flag && 379 "Chain and flag operands should occur at end of operand list!"); 380 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 381 } 382} 383 384/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 385/// "SubIdx"'th sub-register class is the specified register class and whose 386/// type matches the specified type. 387static const TargetRegisterClass* 388getSuperRegisterRegClass(const TargetRegisterClass *TRC, 389 unsigned SubIdx, EVT VT) { 390 // Pick the register class of the superegister for this type 391 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 392 E = TRC->superregclasses_end(); I != E; ++I) 393 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 394 return *I; 395 assert(false && "Couldn't find the register class"); 396 return 0; 397} 398 399/// EmitSubregNode - Generate machine code for subreg nodes. 400/// 401void InstrEmitter::EmitSubregNode(SDNode *Node, 402 DenseMap<SDValue, unsigned> &VRBaseMap){ 403 unsigned VRBase = 0; 404 unsigned Opc = Node->getMachineOpcode(); 405 406 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 407 // the CopyToReg'd destination register instead of creating a new vreg. 408 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 409 UI != E; ++UI) { 410 SDNode *User = *UI; 411 if (User->getOpcode() == ISD::CopyToReg && 412 User->getOperand(2).getNode() == Node) { 413 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 414 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 415 VRBase = DestReg; 416 break; 417 } 418 } 419 } 420 421 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 422 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 423 424 // Create the extract_subreg machine instruction. 425 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 426 TII->get(TargetOpcode::EXTRACT_SUBREG)); 427 428 // Figure out the register class to create for the destreg. 429 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 430 const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 431 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 432 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 433 434 // Figure out the register class to create for the destreg. 435 // Note that if we're going to directly use an existing register, 436 // it must be precisely the required class, and not a subclass 437 // thereof. 438 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 439 // Create the reg 440 assert(SRC && "Couldn't find source register class"); 441 VRBase = MRI->createVirtualRegister(SRC); 442 } 443 444 // Add def, source, and subreg index 445 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 446 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); 447 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 448 MBB->insert(InsertPos, MI); 449 } else if (Opc == TargetOpcode::INSERT_SUBREG || 450 Opc == TargetOpcode::SUBREG_TO_REG) { 451 SDValue N0 = Node->getOperand(0); 452 SDValue N1 = Node->getOperand(1); 453 SDValue N2 = Node->getOperand(2); 454 unsigned SubReg = getVR(N1, VRBaseMap); 455 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 456 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 457 const TargetRegisterClass *SRC = 458 getSuperRegisterRegClass(TRC, SubIdx, 459 Node->getValueType(0)); 460 461 // Figure out the register class to create for the destreg. 462 // Note that if we're going to directly use an existing register, 463 // it must be precisely the required class, and not a subclass 464 // thereof. 465 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 466 // Create the reg 467 assert(SRC && "Couldn't find source register class"); 468 VRBase = MRI->createVirtualRegister(SRC); 469 } 470 471 // Create the insert_subreg or subreg_to_reg machine instruction. 472 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 473 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 474 475 // If creating a subreg_to_reg, then the first input operand 476 // is an implicit value immediate, otherwise it's a register 477 if (Opc == TargetOpcode::SUBREG_TO_REG) { 478 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 479 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 480 } else 481 AddOperand(MI, N0, 0, 0, VRBaseMap); 482 // Add the subregster being inserted 483 AddOperand(MI, N1, 0, 0, VRBaseMap); 484 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 485 MBB->insert(InsertPos, MI); 486 } else 487 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 488 489 SDValue Op(Node, 0); 490 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 491 isNew = isNew; // Silence compiler warning. 492 assert(isNew && "Node emitted out of order - early"); 493} 494 495/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 496/// COPY_TO_REGCLASS is just a normal copy, except that the destination 497/// register is constrained to be in a particular register class. 498/// 499void 500InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 501 DenseMap<SDValue, unsigned> &VRBaseMap) { 502 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 503 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 504 505 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 506 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 507 508 // Create the new VReg in the destination class and emit a copy. 509 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 510 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 511 DstRC, SrcRC); 512 assert(Emitted && 513 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 514 (void) Emitted; 515 516 SDValue Op(Node, 0); 517 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 518 isNew = isNew; // Silence compiler warning. 519 assert(isNew && "Node emitted out of order - early"); 520} 521 522/// EmitDbgValue - Generate machine instruction for a dbg_value node. 523/// 524MachineInstr * 525InstrEmitter::EmitDbgValue(SDDbgValue *SD, 526 DenseMap<SDValue, unsigned> &VRBaseMap) { 527 uint64_t Offset = SD->getOffset(); 528 MDNode* MDPtr = SD->getMDPtr(); 529 DebugLoc DL = SD->getDebugLoc(); 530 531 if (SD->getKind() == SDDbgValue::FRAMEIX) { 532 // Stack address; this needs to be lowered in target-dependent fashion. 533 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 534 unsigned FrameIx = SD->getFrameIx(); 535 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 536 } 537 // Otherwise, we're going to create an instruction here. 538 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 539 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 540 if (SD->getKind() == SDDbgValue::SDNODE) { 541 SDNode *Node = SD->getSDNode(); 542 SDValue Op = SDValue(Node, SD->getResNo()); 543 // It's possible we replaced this SDNode with other(s) and therefore 544 // didn't generate code for it. It's better to catch these cases where 545 // they happen and transfer the debug info, but trying to guarantee that 546 // in all cases would be very fragile; this is a safeguard for any 547 // that were missed. 548 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 549 if (I==VRBaseMap.end()) 550 MIB.addReg(0U); // undef 551 else 552 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 553 true /*IsDebug*/); 554 } else if (SD->getKind() == SDDbgValue::CONST) { 555 const Value *V = SD->getConst(); 556 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 557 MIB.addImm(CI->getSExtValue()); 558 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 559 MIB.addFPImm(CF); 560 } else { 561 // Could be an Undef. In any case insert an Undef so we can see what we 562 // dropped. 563 MIB.addReg(0U); 564 } 565 } else { 566 // Insert an Undef so we can see what we dropped. 567 MIB.addReg(0U); 568 } 569 570 MIB.addImm(Offset).addMetadata(MDPtr); 571 return &*MIB; 572} 573 574/// EmitMachineNode - Generate machine code for a target-specific node and 575/// needed dependencies. 576/// 577void InstrEmitter:: 578EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 579 DenseMap<SDValue, unsigned> &VRBaseMap, 580 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) { 581 unsigned Opc = Node->getMachineOpcode(); 582 583 // Handle subreg insert/extract specially 584 if (Opc == TargetOpcode::EXTRACT_SUBREG || 585 Opc == TargetOpcode::INSERT_SUBREG || 586 Opc == TargetOpcode::SUBREG_TO_REG) { 587 EmitSubregNode(Node, VRBaseMap); 588 return; 589 } 590 591 // Handle COPY_TO_REGCLASS specially. 592 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 593 EmitCopyToRegClassNode(Node, VRBaseMap); 594 return; 595 } 596 597 if (Opc == TargetOpcode::IMPLICIT_DEF) 598 // We want a unique VR for each IMPLICIT_DEF use. 599 return; 600 601 const TargetInstrDesc &II = TII->get(Opc); 602 unsigned NumResults = CountResults(Node); 603 unsigned NodeOperands = CountOperands(Node); 604 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 605#ifndef NDEBUG 606 unsigned NumMIOperands = NodeOperands + NumResults; 607 if (II.isVariadic()) 608 assert(NumMIOperands >= II.getNumOperands() && 609 "Too few operands for a variadic node!"); 610 else 611 assert(NumMIOperands >= II.getNumOperands() && 612 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 613 "#operands for dag node doesn't match .td file!"); 614#endif 615 616 // Create the new machine instruction. 617 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 618 619 // Add result register values for things that are defined by this 620 // instruction. 621 if (NumResults) 622 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 623 624 // Emit all of the actual operands of this instruction, adding them to the 625 // instruction as appropriate. 626 bool HasOptPRefs = II.getNumDefs() > NumResults; 627 assert((!HasOptPRefs || !HasPhysRegOuts) && 628 "Unable to cope with optional defs and phys regs defs!"); 629 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 630 for (unsigned i = NumSkip; i != NodeOperands; ++i) 631 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 632 VRBaseMap); 633 634 // Transfer all of the memory reference descriptions of this instruction. 635 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 636 cast<MachineSDNode>(Node)->memoperands_end()); 637 638 if (II.usesCustomInsertionHook()) { 639 // Insert this instruction into the basic block using a target 640 // specific inserter which may returns a new basic block. 641 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM); 642 InsertPos = MBB->end(); 643 return; 644 } 645 646 MBB->insert(InsertPos, MI); 647 648 // Additional results must be an physical register def. 649 if (HasPhysRegOuts) { 650 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 651 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 652 if (Node->hasAnyUseOfValue(i)) 653 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 654 // If there are no uses, mark the register as dead now, so that 655 // MachineLICM/Sink can see that it's dead. Don't do this if the 656 // node has a Flag value, for the benefit of targets still using 657 // Flag for values in physregs. 658 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 659 MI->addRegisterDead(Reg, TRI); 660 } 661 } 662 663 // If the instruction has implicit defs and the node doesn't, mark the 664 // implicit def as dead. If the node has any flag outputs, we don't do this 665 // because we don't know what implicit defs are being used by flagged nodes. 666 if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 667 if (const unsigned *IDList = II.getImplicitDefs()) { 668 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 669 i != e; ++i) 670 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 671 } 672} 673 674/// EmitSpecialNode - Generate machine code for a target-independent node and 675/// needed dependencies. 676void InstrEmitter:: 677EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 678 DenseMap<SDValue, unsigned> &VRBaseMap) { 679 switch (Node->getOpcode()) { 680 default: 681#ifndef NDEBUG 682 Node->dump(); 683#endif 684 llvm_unreachable("This target-independent node should have been selected!"); 685 break; 686 case ISD::EntryToken: 687 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 688 break; 689 case ISD::MERGE_VALUES: 690 case ISD::TokenFactor: // fall thru 691 break; 692 case ISD::CopyToReg: { 693 unsigned SrcReg; 694 SDValue SrcVal = Node->getOperand(2); 695 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 696 SrcReg = R->getReg(); 697 else 698 SrcReg = getVR(SrcVal, VRBaseMap); 699 700 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 701 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 702 break; 703 704 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 705 // Get the register classes of the src/dst. 706 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 707 SrcTRC = MRI->getRegClass(SrcReg); 708 else 709 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 710 711 if (TargetRegisterInfo::isVirtualRegister(DestReg)) 712 DstTRC = MRI->getRegClass(DestReg); 713 else 714 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 715 Node->getOperand(1).getValueType()); 716 717 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 718 DstTRC, SrcTRC); 719 assert(Emitted && "Unable to issue a copy instruction!\n"); 720 (void) Emitted; 721 break; 722 } 723 case ISD::CopyFromReg: { 724 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 725 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 726 break; 727 } 728 case ISD::EH_LABEL: { 729 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 730 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 731 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 732 break; 733 } 734 735 case ISD::INLINEASM: { 736 unsigned NumOps = Node->getNumOperands(); 737 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 738 --NumOps; // Ignore the flag operand. 739 740 // Create the inline asm machine instruction. 741 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 742 TII->get(TargetOpcode::INLINEASM)); 743 744 // Add the asm string as an external symbol operand. 745 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 746 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 747 MI->addOperand(MachineOperand::CreateES(AsmStr)); 748 749 // Add all of the operand registers to the instruction. 750 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 751 unsigned Flags = 752 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 753 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 754 755 MI->addOperand(MachineOperand::CreateImm(Flags)); 756 ++i; // Skip the ID value. 757 758 switch (InlineAsm::getKind(Flags)) { 759 default: llvm_unreachable("Bad flags!"); 760 case InlineAsm::Kind_RegDef: 761 for (; NumVals; --NumVals, ++i) { 762 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 763 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 764 } 765 break; 766 case InlineAsm::Kind_RegDefEarlyClobber: 767 for (; NumVals; --NumVals, ++i) { 768 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 769 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 770 false, false, true)); 771 } 772 break; 773 case InlineAsm::Kind_RegUse: // Use of register. 774 case InlineAsm::Kind_Imm: // Immediate. 775 case InlineAsm::Kind_Mem: // Addressing mode. 776 // The addressing mode has been selected, just add all of the 777 // operands to the machine instruction. 778 for (; NumVals; --NumVals, ++i) 779 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 780 break; 781 } 782 } 783 784 // Get the mdnode from the asm if it exists and add it to the instruction. 785 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 786 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 787 if (MD) 788 MI->addOperand(MachineOperand::CreateMetadata(MD)); 789 790 MBB->insert(InsertPos, MI); 791 break; 792 } 793 } 794} 795 796/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 797/// at the given position in the given block. 798InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 799 MachineBasicBlock::iterator insertpos) 800 : MF(mbb->getParent()), 801 MRI(&MF->getRegInfo()), 802 TM(&MF->getTarget()), 803 TII(TM->getInstrInfo()), 804 TRI(TM->getRegisterInfo()), 805 TLI(TM->getTargetLowering()), 806 MBB(mbb), InsertPos(insertpos) { 807} 808