InstrEmitter.cpp revision 962021bc7f6721c20c7dfe8ca809e2d98b1c554a
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "SDNodeDbgValue.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetLowering.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33/// CountResults - The results of target nodes have register or immediate 34/// operands first, then an optional chain, and optional flag operands (which do 35/// not go into the resulting MachineInstr). 36unsigned InstrEmitter::CountResults(SDNode *Node) { 37 unsigned N = Node->getNumValues(); 38 while (N && Node->getValueType(N - 1) == MVT::Flag) 39 --N; 40 if (N && Node->getValueType(N - 1) == MVT::Other) 41 --N; // Skip over chain result. 42 return N; 43} 44 45/// CountOperands - The inputs to target nodes have any actual inputs first, 46/// followed by an optional chain operand, then an optional flag operand. 47/// Compute the number of actual operands that will go into the resulting 48/// MachineInstr. 49unsigned InstrEmitter::CountOperands(SDNode *Node) { 50 unsigned N = Node->getNumOperands(); 51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52 --N; 53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54 --N; // Ignore chain if it exists. 55 return N; 56} 57 58/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59/// implicit physical register output. 60void InstrEmitter:: 61EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63 unsigned VRBase = 0; 64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65 // Just use the input register directly! 66 SDValue Op(Node, ResNo); 67 if (IsClone) 68 VRBaseMap.erase(Op); 69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70 isNew = isNew; // Silence compiler warning. 71 assert(isNew && "Node emitted out of order - early"); 72 return; 73 } 74 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76 // the CopyToReg'd destination register instead of creating a new vreg. 77 bool MatchReg = true; 78 const TargetRegisterClass *UseRC = NULL; 79 if (!IsClone && !IsCloned) 80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81 UI != E; ++UI) { 82 SDNode *User = *UI; 83 bool Match = true; 84 if (User->getOpcode() == ISD::CopyToReg && 85 User->getOperand(2).getNode() == Node && 86 User->getOperand(2).getResNo() == ResNo) { 87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89 VRBase = DestReg; 90 Match = false; 91 } else if (DestReg != SrcReg) 92 Match = false; 93 } else { 94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95 SDValue Op = User->getOperand(i); 96 if (Op.getNode() != Node || Op.getResNo() != ResNo) 97 continue; 98 EVT VT = Node->getValueType(Op.getResNo()); 99 if (VT == MVT::Other || VT == MVT::Flag) 100 continue; 101 Match = false; 102 if (User->isMachineOpcode()) { 103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104 const TargetRegisterClass *RC = 0; 105 if (i+II.getNumDefs() < II.getNumOperands()) 106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107 if (!UseRC) 108 UseRC = RC; 109 else if (RC) { 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111 // If multiple uses expect disjoint register classes, we emit 112 // copies in AddRegisterOperand. 113 if (ComRC) 114 UseRC = ComRC; 115 } 116 } 117 } 118 } 119 MatchReg &= Match; 120 if (VRBase) 121 break; 122 } 123 124 EVT VT = Node->getValueType(ResNo); 125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 127 128 // Figure out the register class to create for the destreg. 129 if (VRBase) { 130 DstRC = MRI->getRegClass(VRBase); 131 } else if (UseRC) { 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133 DstRC = UseRC; 134 } else { 135 DstRC = TLI->getRegClassFor(VT); 136 } 137 138 // If all uses are reading from the src physical register and copying the 139 // register is either impossible or very expensive, then don't create a copy. 140 if (MatchReg && SrcRC->getCopyCost() < 0) { 141 VRBase = SrcReg; 142 } else { 143 // Create the reg, emit the copy. 144 VRBase = MRI->createVirtualRegister(DstRC); 145 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 146 DstRC, SrcRC); 147 148 assert(Emitted && "Unable to issue a copy instruction!\n"); 149 (void) Emitted; 150 } 151 152 SDValue Op(Node, ResNo); 153 if (IsClone) 154 VRBaseMap.erase(Op); 155 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 156 isNew = isNew; // Silence compiler warning. 157 assert(isNew && "Node emitted out of order - early"); 158} 159 160/// getDstOfCopyToRegUse - If the only use of the specified result number of 161/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163 unsigned ResNo) const { 164 if (!Node->hasOneUse()) 165 return 0; 166 167 SDNode *User = *Node->use_begin(); 168 if (User->getOpcode() == ISD::CopyToReg && 169 User->getOperand(2).getNode() == Node && 170 User->getOperand(2).getResNo() == ResNo) { 171 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 172 if (TargetRegisterInfo::isVirtualRegister(Reg)) 173 return Reg; 174 } 175 return 0; 176} 177 178void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179 const TargetInstrDesc &II, 180 bool IsClone, bool IsCloned, 181 DenseMap<SDValue, unsigned> &VRBaseMap) { 182 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 183 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 184 185 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 186 // If the specific node value is only used by a CopyToReg and the dest reg 187 // is a vreg in the same register class, use the CopyToReg'd destination 188 // register instead of creating a new vreg. 189 unsigned VRBase = 0; 190 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 191 if (II.OpInfo[i].isOptionalDef()) { 192 // Optional def must be a physical register. 193 unsigned NumResults = CountResults(Node); 194 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 195 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 196 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 197 } 198 199 if (!VRBase && !IsClone && !IsCloned) 200 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201 UI != E; ++UI) { 202 SDNode *User = *UI; 203 if (User->getOpcode() == ISD::CopyToReg && 204 User->getOperand(2).getNode() == Node && 205 User->getOperand(2).getResNo() == i) { 206 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209 if (RegRC == RC) { 210 VRBase = Reg; 211 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212 break; 213 } 214 } 215 } 216 } 217 218 // Create the result registers for this node and add the result regs to 219 // the machine instruction. 220 if (VRBase == 0) { 221 assert(RC && "Isn't a register operand!"); 222 VRBase = MRI->createVirtualRegister(RC); 223 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 224 } 225 226 SDValue Op(Node, i); 227 if (IsClone) 228 VRBaseMap.erase(Op); 229 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 230 isNew = isNew; // Silence compiler warning. 231 assert(isNew && "Node emitted out of order - early"); 232 } 233} 234 235/// getVR - Return the virtual register corresponding to the specified result 236/// of the specified node. 237unsigned InstrEmitter::getVR(SDValue Op, 238 DenseMap<SDValue, unsigned> &VRBaseMap) { 239 if (Op.isMachineOpcode() && 240 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 241 // Add an IMPLICIT_DEF instruction before every use. 242 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 243 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 244 // does not include operand register class info. 245 if (!VReg) { 246 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247 VReg = MRI->createVirtualRegister(RC); 248 } 249 BuildMI(MBB, Op.getDebugLoc(), 250 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 251 return VReg; 252 } 253 254 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 255 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 256 return I->second; 257} 258 259 260/// AddRegisterOperand - Add the specified register as an operand to the 261/// specified machine instr. Insert register copies if the register is 262/// not in the required register class. 263void 264InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265 unsigned IIOpNum, 266 const TargetInstrDesc *II, 267 DenseMap<SDValue, unsigned> &VRBaseMap, 268 bool IsDebug) { 269 assert(Op.getValueType() != MVT::Other && 270 Op.getValueType() != MVT::Flag && 271 "Chain and flag operands should occur at end of operand list!"); 272 // Get/emit the operand. 273 unsigned VReg = getVR(Op, VRBaseMap); 274 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 275 276 const TargetInstrDesc &TID = MI->getDesc(); 277 bool isOptDef = IIOpNum < TID.getNumOperands() && 278 TID.OpInfo[IIOpNum].isOptionalDef(); 279 280 // If the instruction requires a register in a different class, create 281 // a new virtual register and copy the value into it. 282 if (II) { 283 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 284 const TargetRegisterClass *DstRC = 0; 285 if (IIOpNum < II->getNumOperands()) 286 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 287 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 288 "Don't have operand info for this instruction!"); 289 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 290 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 291 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 292 DstRC, SrcRC); 293 assert(Emitted && "Unable to issue a copy instruction!\n"); 294 (void) Emitted; 295 VReg = NewVReg; 296 } 297 } 298 299 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 300 false/*isImp*/, false/*isKill*/, 301 false/*isDead*/, false/*isUndef*/, 302 false/*isEarlyClobber*/, 303 0/*SubReg*/, IsDebug)); 304} 305 306/// AddOperand - Add the specified operand to the specified machine instr. II 307/// specifies the instruction information for the node, and IIOpNum is the 308/// operand number (in the II) that we are adding. IIOpNum and II are used for 309/// assertions only. 310void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 311 unsigned IIOpNum, 312 const TargetInstrDesc *II, 313 DenseMap<SDValue, unsigned> &VRBaseMap, 314 bool IsDebug) { 315 if (Op.isMachineOpcode()) { 316 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 317 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 318 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 319 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 320 const ConstantFP *CFP = F->getConstantFPValue(); 321 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 322 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 323 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 324 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 325 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 326 TGA->getTargetFlags())); 327 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 328 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 329 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 330 MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 331 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 332 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 333 JT->getTargetFlags())); 334 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 335 int Offset = CP->getOffset(); 336 unsigned Align = CP->getAlignment(); 337 const Type *Type = CP->getType(); 338 // MachineConstantPool wants an explicit alignment. 339 if (Align == 0) { 340 Align = TM->getTargetData()->getPrefTypeAlignment(Type); 341 if (Align == 0) { 342 // Alignment of vector types. FIXME! 343 Align = TM->getTargetData()->getTypeAllocSize(Type); 344 } 345 } 346 347 unsigned Idx; 348 MachineConstantPool *MCP = MF->getConstantPool(); 349 if (CP->isMachineConstantPoolEntry()) 350 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 351 else 352 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 353 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 354 CP->getTargetFlags())); 355 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 356 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 357 ES->getTargetFlags())); 358 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 359 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 360 BA->getTargetFlags())); 361 } else { 362 assert(Op.getValueType() != MVT::Other && 363 Op.getValueType() != MVT::Flag && 364 "Chain and flag operands should occur at end of operand list!"); 365 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, IsDebug); 366 } 367} 368 369/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 370/// "SubIdx"'th sub-register class is the specified register class and whose 371/// type matches the specified type. 372static const TargetRegisterClass* 373getSuperRegisterRegClass(const TargetRegisterClass *TRC, 374 unsigned SubIdx, EVT VT) { 375 // Pick the register class of the superegister for this type 376 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 377 E = TRC->superregclasses_end(); I != E; ++I) 378 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 379 return *I; 380 assert(false && "Couldn't find the register class"); 381 return 0; 382} 383 384/// EmitSubregNode - Generate machine code for subreg nodes. 385/// 386void InstrEmitter::EmitSubregNode(SDNode *Node, 387 DenseMap<SDValue, unsigned> &VRBaseMap){ 388 unsigned VRBase = 0; 389 unsigned Opc = Node->getMachineOpcode(); 390 391 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 392 // the CopyToReg'd destination register instead of creating a new vreg. 393 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 394 UI != E; ++UI) { 395 SDNode *User = *UI; 396 if (User->getOpcode() == ISD::CopyToReg && 397 User->getOperand(2).getNode() == Node) { 398 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 399 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 400 VRBase = DestReg; 401 break; 402 } 403 } 404 } 405 406 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 407 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 408 409 // Create the extract_subreg machine instruction. 410 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 411 TII->get(TargetOpcode::EXTRACT_SUBREG)); 412 413 // Figure out the register class to create for the destreg. 414 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 415 const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 416 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 417 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 418 419 // Figure out the register class to create for the destreg. 420 // Note that if we're going to directly use an existing register, 421 // it must be precisely the required class, and not a subclass 422 // thereof. 423 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 424 // Create the reg 425 assert(SRC && "Couldn't find source register class"); 426 VRBase = MRI->createVirtualRegister(SRC); 427 } 428 429 // Add def, source, and subreg index 430 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 431 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap); 432 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 433 MBB->insert(InsertPos, MI); 434 } else if (Opc == TargetOpcode::INSERT_SUBREG || 435 Opc == TargetOpcode::SUBREG_TO_REG) { 436 SDValue N0 = Node->getOperand(0); 437 SDValue N1 = Node->getOperand(1); 438 SDValue N2 = Node->getOperand(2); 439 unsigned SubReg = getVR(N1, VRBaseMap); 440 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 441 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 442 const TargetRegisterClass *SRC = 443 getSuperRegisterRegClass(TRC, SubIdx, 444 Node->getValueType(0)); 445 446 // Figure out the register class to create for the destreg. 447 // Note that if we're going to directly use an existing register, 448 // it must be precisely the required class, and not a subclass 449 // thereof. 450 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 451 // Create the reg 452 assert(SRC && "Couldn't find source register class"); 453 VRBase = MRI->createVirtualRegister(SRC); 454 } 455 456 // Create the insert_subreg or subreg_to_reg machine instruction. 457 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 458 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 459 460 // If creating a subreg_to_reg, then the first input operand 461 // is an implicit value immediate, otherwise it's a register 462 if (Opc == TargetOpcode::SUBREG_TO_REG) { 463 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 464 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 465 } else 466 AddOperand(MI, N0, 0, 0, VRBaseMap); 467 // Add the subregster being inserted 468 AddOperand(MI, N1, 0, 0, VRBaseMap); 469 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 470 MBB->insert(InsertPos, MI); 471 } else 472 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 473 474 SDValue Op(Node, 0); 475 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 476 isNew = isNew; // Silence compiler warning. 477 assert(isNew && "Node emitted out of order - early"); 478} 479 480/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 481/// COPY_TO_REGCLASS is just a normal copy, except that the destination 482/// register is constrained to be in a particular register class. 483/// 484void 485InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 486 DenseMap<SDValue, unsigned> &VRBaseMap) { 487 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 488 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 489 490 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 491 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 492 493 // Create the new VReg in the destination class and emit a copy. 494 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 495 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 496 DstRC, SrcRC); 497 assert(Emitted && 498 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 499 (void) Emitted; 500 501 SDValue Op(Node, 0); 502 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 503 isNew = isNew; // Silence compiler warning. 504 assert(isNew && "Node emitted out of order - early"); 505} 506 507/// EmitDbgValue - Generate machine instruction for a dbg_value node. 508/// 509MachineInstr *InstrEmitter::EmitDbgValue(SDDbgValue *SD, 510 DenseMap<SDValue, unsigned> &VRBaseMap, 511 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) { 512 uint64_t Offset = SD->getOffset(); 513 MDNode* MDPtr = SD->getMDPtr(); 514 DebugLoc DL = SD->getDebugLoc(); 515 516 if (SD->getKind() == SDDbgValue::FRAMEIX) { 517 // Stack address; this needs to be lowered in target-dependent fashion. 518 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 519 unsigned FrameIx = SD->getFrameIx(); 520 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 521 } 522 // Otherwise, we're going to create an instruction here. 523 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 524 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 525 if (SD->getKind() == SDDbgValue::SDNODE) { 526 SDNode *Node = SD->getSDNode(); 527 SDValue Op = SDValue(Node, SD->getResNo()); 528 // It's possible we replaced this SDNode with other(s) and therefore 529 // didn't generate code for it. It's better to catch these cases where 530 // they happen and transfer the debug info, but trying to guarantee that 531 // in all cases would be very fragile; this is a safeguard for any 532 // that were missed. 533 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 534 if (I==VRBaseMap.end()) 535 MIB.addReg(0U); // undef 536 else 537 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 538 true /*IsDebug*/); 539 } else if (SD->getKind() == SDDbgValue::CONST) { 540 const Value *V = SD->getConst(); 541 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 542 MIB.addImm(CI->getSExtValue()); 543 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 544 MIB.addFPImm(CF); 545 } else { 546 // Could be an Undef. In any case insert an Undef so we can see what we 547 // dropped. 548 MIB.addReg(0U); 549 } 550 } else { 551 // Insert an Undef so we can see what we dropped. 552 MIB.addReg(0U); 553 } 554 555 MIB.addImm(Offset).addMetadata(MDPtr); 556 return &*MIB; 557} 558 559/// EmitMachineNode - Generate machine code for a target-specific node and 560/// needed dependencies. 561/// 562void InstrEmitter:: 563EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 564 DenseMap<SDValue, unsigned> &VRBaseMap, 565 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) { 566 unsigned Opc = Node->getMachineOpcode(); 567 568 // Handle subreg insert/extract specially 569 if (Opc == TargetOpcode::EXTRACT_SUBREG || 570 Opc == TargetOpcode::INSERT_SUBREG || 571 Opc == TargetOpcode::SUBREG_TO_REG) { 572 EmitSubregNode(Node, VRBaseMap); 573 return; 574 } 575 576 // Handle COPY_TO_REGCLASS specially. 577 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 578 EmitCopyToRegClassNode(Node, VRBaseMap); 579 return; 580 } 581 582 if (Opc == TargetOpcode::IMPLICIT_DEF) 583 // We want a unique VR for each IMPLICIT_DEF use. 584 return; 585 586 const TargetInstrDesc &II = TII->get(Opc); 587 unsigned NumResults = CountResults(Node); 588 unsigned NodeOperands = CountOperands(Node); 589 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 590#ifndef NDEBUG 591 unsigned NumMIOperands = NodeOperands + NumResults; 592 if (II.isVariadic()) 593 assert(NumMIOperands >= II.getNumOperands() && 594 "Too few operands for a variadic node!"); 595 else 596 assert(NumMIOperands >= II.getNumOperands() && 597 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 598 "#operands for dag node doesn't match .td file!"); 599#endif 600 601 // Create the new machine instruction. 602 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 603 604 // Add result register values for things that are defined by this 605 // instruction. 606 if (NumResults) 607 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 608 609 // Emit all of the actual operands of this instruction, adding them to the 610 // instruction as appropriate. 611 bool HasOptPRefs = II.getNumDefs() > NumResults; 612 assert((!HasOptPRefs || !HasPhysRegOuts) && 613 "Unable to cope with optional defs and phys regs defs!"); 614 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 615 for (unsigned i = NumSkip; i != NodeOperands; ++i) 616 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 617 VRBaseMap); 618 619 // Transfer all of the memory reference descriptions of this instruction. 620 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 621 cast<MachineSDNode>(Node)->memoperands_end()); 622 623 if (II.usesCustomInsertionHook()) { 624 // Insert this instruction into the basic block using a target 625 // specific inserter which may returns a new basic block. 626 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM); 627 InsertPos = MBB->end(); 628 return; 629 } 630 631 MBB->insert(InsertPos, MI); 632 633 // Additional results must be an physical register def. 634 if (HasPhysRegOuts) { 635 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 636 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 637 if (Node->hasAnyUseOfValue(i)) 638 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 639 // If there are no uses, mark the register as dead now, so that 640 // MachineLICM/Sink can see that it's dead. Don't do this if the 641 // node has a Flag value, for the benefit of targets still using 642 // Flag for values in physregs. 643 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 644 MI->addRegisterDead(Reg, TRI); 645 } 646 } 647 648 // If the instruction has implicit defs and the node doesn't, mark the 649 // implicit def as dead. If the node has any flag outputs, we don't do this 650 // because we don't know what implicit defs are being used by flagged nodes. 651 if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 652 if (const unsigned *IDList = II.getImplicitDefs()) { 653 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 654 i != e; ++i) 655 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 656 } 657} 658 659/// EmitSpecialNode - Generate machine code for a target-independent node and 660/// needed dependencies. 661void InstrEmitter:: 662EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 663 DenseMap<SDValue, unsigned> &VRBaseMap) { 664 switch (Node->getOpcode()) { 665 default: 666#ifndef NDEBUG 667 Node->dump(); 668#endif 669 llvm_unreachable("This target-independent node should have been selected!"); 670 break; 671 case ISD::EntryToken: 672 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 673 break; 674 case ISD::MERGE_VALUES: 675 case ISD::TokenFactor: // fall thru 676 break; 677 case ISD::CopyToReg: { 678 unsigned SrcReg; 679 SDValue SrcVal = Node->getOperand(2); 680 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 681 SrcReg = R->getReg(); 682 else 683 SrcReg = getVR(SrcVal, VRBaseMap); 684 685 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 686 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 687 break; 688 689 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 690 // Get the register classes of the src/dst. 691 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 692 SrcTRC = MRI->getRegClass(SrcReg); 693 else 694 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 695 696 if (TargetRegisterInfo::isVirtualRegister(DestReg)) 697 DstTRC = MRI->getRegClass(DestReg); 698 else 699 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 700 Node->getOperand(1).getValueType()); 701 702 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 703 DstTRC, SrcTRC); 704 assert(Emitted && "Unable to issue a copy instruction!\n"); 705 (void) Emitted; 706 break; 707 } 708 case ISD::CopyFromReg: { 709 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 710 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 711 break; 712 } 713 case ISD::EH_LABEL: { 714 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 715 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 716 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 717 break; 718 } 719 720 case ISD::INLINEASM: { 721 unsigned NumOps = Node->getNumOperands(); 722 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 723 --NumOps; // Ignore the flag operand. 724 725 // Create the inline asm machine instruction. 726 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 727 TII->get(TargetOpcode::INLINEASM)); 728 729 // Add the asm string as an external symbol operand. 730 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 731 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 732 MI->addOperand(MachineOperand::CreateES(AsmStr)); 733 734 // Add all of the operand registers to the instruction. 735 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 736 unsigned Flags = 737 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 738 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 739 740 MI->addOperand(MachineOperand::CreateImm(Flags)); 741 ++i; // Skip the ID value. 742 743 switch (InlineAsm::getKind(Flags)) { 744 default: llvm_unreachable("Bad flags!"); 745 case InlineAsm::Kind_RegDef: 746 for (; NumVals; --NumVals, ++i) { 747 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 748 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 749 } 750 break; 751 case InlineAsm::Kind_RegDefEarlyClobber: 752 for (; NumVals; --NumVals, ++i) { 753 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 754 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 755 false, false, true)); 756 } 757 break; 758 case InlineAsm::Kind_RegUse: // Use of register. 759 case InlineAsm::Kind_Imm: // Immediate. 760 case InlineAsm::Kind_Mem: // Addressing mode. 761 // The addressing mode has been selected, just add all of the 762 // operands to the machine instruction. 763 for (; NumVals; --NumVals, ++i) 764 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap); 765 break; 766 } 767 } 768 769 // Get the mdnode from the asm if it exists and add it to the instruction. 770 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 771 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 772 MI->addOperand(MachineOperand::CreateMetadata(MD)); 773 774 MBB->insert(InsertPos, MI); 775 break; 776 } 777 } 778} 779 780/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 781/// at the given position in the given block. 782InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 783 MachineBasicBlock::iterator insertpos) 784 : MF(mbb->getParent()), 785 MRI(&MF->getRegInfo()), 786 TM(&MF->getTarget()), 787 TII(TM->getInstrInfo()), 788 TRI(TM->getRegisterInfo()), 789 TLI(TM->getTargetLowering()), 790 MBB(mbb), InsertPos(insertpos) { 791} 792