InstrEmitter.cpp revision c36b7069b42bece963b7e6adf020353ce990ef76
1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "instr-emitter" 17#include "InstrEmitter.h" 18#include "SDNodeDbgValue.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetLowering.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/MathExtras.h" 31using namespace llvm; 32 33/// CountResults - The results of target nodes have register or immediate 34/// operands first, then an optional chain, and optional glue operands (which do 35/// not go into the resulting MachineInstr). 36unsigned InstrEmitter::CountResults(SDNode *Node) { 37 unsigned N = Node->getNumValues(); 38 while (N && Node->getValueType(N - 1) == MVT::Glue) 39 --N; 40 if (N && Node->getValueType(N - 1) == MVT::Other) 41 --N; // Skip over chain result. 42 return N; 43} 44 45/// CountOperands - The inputs to target nodes have any actual inputs first, 46/// followed by an optional chain operand, then an optional glue operand. 47/// Compute the number of actual operands that will go into the resulting 48/// MachineInstr. 49unsigned InstrEmitter::CountOperands(SDNode *Node) { 50 unsigned N = Node->getNumOperands(); 51 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 52 --N; 53 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54 --N; // Ignore chain if it exists. 55 return N; 56} 57 58/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59/// implicit physical register output. 60void InstrEmitter:: 61EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63 unsigned VRBase = 0; 64 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65 // Just use the input register directly! 66 SDValue Op(Node, ResNo); 67 if (IsClone) 68 VRBaseMap.erase(Op); 69 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70 (void)isNew; // Silence compiler warning. 71 assert(isNew && "Node emitted out of order - early"); 72 return; 73 } 74 75 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76 // the CopyToReg'd destination register instead of creating a new vreg. 77 bool MatchReg = true; 78 const TargetRegisterClass *UseRC = NULL; 79 if (!IsClone && !IsCloned) 80 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81 UI != E; ++UI) { 82 SDNode *User = *UI; 83 bool Match = true; 84 if (User->getOpcode() == ISD::CopyToReg && 85 User->getOperand(2).getNode() == Node && 86 User->getOperand(2).getResNo() == ResNo) { 87 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89 VRBase = DestReg; 90 Match = false; 91 } else if (DestReg != SrcReg) 92 Match = false; 93 } else { 94 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95 SDValue Op = User->getOperand(i); 96 if (Op.getNode() != Node || Op.getResNo() != ResNo) 97 continue; 98 EVT VT = Node->getValueType(Op.getResNo()); 99 if (VT == MVT::Other || VT == MVT::Glue) 100 continue; 101 Match = false; 102 if (User->isMachineOpcode()) { 103 const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104 const TargetRegisterClass *RC = 0; 105 if (i+II.getNumDefs() < II.getNumOperands()) 106 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107 if (!UseRC) 108 UseRC = RC; 109 else if (RC) { 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111 // If multiple uses expect disjoint register classes, we emit 112 // copies in AddRegisterOperand. 113 if (ComRC) 114 UseRC = ComRC; 115 } 116 } 117 } 118 } 119 MatchReg &= Match; 120 if (VRBase) 121 break; 122 } 123 124 EVT VT = Node->getValueType(ResNo); 125 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 127 128 // Figure out the register class to create for the destreg. 129 if (VRBase) { 130 DstRC = MRI->getRegClass(VRBase); 131 } else if (UseRC) { 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133 DstRC = UseRC; 134 } else { 135 DstRC = TLI->getRegClassFor(VT); 136 } 137 138 // If all uses are reading from the src physical register and copying the 139 // register is either impossible or very expensive, then don't create a copy. 140 if (MatchReg && SrcRC->getCopyCost() < 0) { 141 VRBase = SrcReg; 142 } else { 143 // Create the reg, emit the copy. 144 VRBase = MRI->createVirtualRegister(DstRC); 145 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 146 VRBase).addReg(SrcReg); 147 } 148 149 SDValue Op(Node, ResNo); 150 if (IsClone) 151 VRBaseMap.erase(Op); 152 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 153 (void)isNew; // Silence compiler warning. 154 assert(isNew && "Node emitted out of order - early"); 155} 156 157/// getDstOfCopyToRegUse - If the only use of the specified result number of 158/// node is a CopyToReg, return its destination register. Return 0 otherwise. 159unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 160 unsigned ResNo) const { 161 if (!Node->hasOneUse()) 162 return 0; 163 164 SDNode *User = *Node->use_begin(); 165 if (User->getOpcode() == ISD::CopyToReg && 166 User->getOperand(2).getNode() == Node && 167 User->getOperand(2).getResNo() == ResNo) { 168 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 169 if (TargetRegisterInfo::isVirtualRegister(Reg)) 170 return Reg; 171 } 172 return 0; 173} 174 175void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 176 const TargetInstrDesc &II, 177 bool IsClone, bool IsCloned, 178 DenseMap<SDValue, unsigned> &VRBaseMap) { 179 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 180 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 181 182 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 183 // If the specific node value is only used by a CopyToReg and the dest reg 184 // is a vreg in the same register class, use the CopyToReg'd destination 185 // register instead of creating a new vreg. 186 unsigned VRBase = 0; 187 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 188 if (II.OpInfo[i].isOptionalDef()) { 189 // Optional def must be a physical register. 190 unsigned NumResults = CountResults(Node); 191 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 192 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 193 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 194 } 195 196 if (!VRBase && !IsClone && !IsCloned) 197 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 198 UI != E; ++UI) { 199 SDNode *User = *UI; 200 if (User->getOpcode() == ISD::CopyToReg && 201 User->getOperand(2).getNode() == Node && 202 User->getOperand(2).getResNo() == i) { 203 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 204 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 205 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 206 if (RegRC == RC) { 207 VRBase = Reg; 208 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 209 break; 210 } 211 } 212 } 213 } 214 215 // Create the result registers for this node and add the result regs to 216 // the machine instruction. 217 if (VRBase == 0) { 218 assert(RC && "Isn't a register operand!"); 219 VRBase = MRI->createVirtualRegister(RC); 220 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 221 } 222 223 SDValue Op(Node, i); 224 if (IsClone) 225 VRBaseMap.erase(Op); 226 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 227 (void)isNew; // Silence compiler warning. 228 assert(isNew && "Node emitted out of order - early"); 229 } 230} 231 232/// getVR - Return the virtual register corresponding to the specified result 233/// of the specified node. 234unsigned InstrEmitter::getVR(SDValue Op, 235 DenseMap<SDValue, unsigned> &VRBaseMap) { 236 if (Op.isMachineOpcode() && 237 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 238 // Add an IMPLICIT_DEF instruction before every use. 239 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 240 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 241 // does not include operand register class info. 242 if (!VReg) { 243 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 244 VReg = MRI->createVirtualRegister(RC); 245 } 246 BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 247 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 248 return VReg; 249 } 250 251 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 252 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 253 return I->second; 254} 255 256 257/// AddRegisterOperand - Add the specified register as an operand to the 258/// specified machine instr. Insert register copies if the register is 259/// not in the required register class. 260void 261InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 262 unsigned IIOpNum, 263 const TargetInstrDesc *II, 264 DenseMap<SDValue, unsigned> &VRBaseMap, 265 bool IsDebug, bool IsClone, bool IsCloned) { 266 assert(Op.getValueType() != MVT::Other && 267 Op.getValueType() != MVT::Glue && 268 "Chain and glue operands should occur at end of operand list!"); 269 // Get/emit the operand. 270 unsigned VReg = getVR(Op, VRBaseMap); 271 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 272 273 const TargetInstrDesc &TID = MI->getDesc(); 274 bool isOptDef = IIOpNum < TID.getNumOperands() && 275 TID.OpInfo[IIOpNum].isOptionalDef(); 276 277 // If the instruction requires a register in a different class, create 278 // a new virtual register and copy the value into it. 279 if (II) { 280 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 281 const TargetRegisterClass *DstRC = 0; 282 if (IIOpNum < II->getNumOperands()) 283 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 284 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 285 "Don't have operand info for this instruction!"); 286 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 287 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 288 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 289 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 290 VReg = NewVReg; 291 } 292 } 293 294 // If this value has only one use, that use is a kill. This is a 295 // conservative approximation. InstrEmitter does trivial coalescing 296 // with CopyFromReg nodes, so don't emit kill flags for them. 297 // Avoid kill flags on Schedule cloned nodes, since there will be 298 // multiple uses. 299 // Tied operands are never killed, so we need to check that. And that 300 // means we need to determine the index of the operand. 301 bool isKill = Op.hasOneUse() && 302 Op.getNode()->getOpcode() != ISD::CopyFromReg && 303 !IsDebug && 304 !(IsClone || IsCloned); 305 if (isKill) { 306 unsigned Idx = MI->getNumOperands(); 307 while (Idx > 0 && 308 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 309 --Idx; 310 bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1; 311 if (isTied) 312 isKill = false; 313 } 314 315 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 316 false/*isImp*/, isKill, 317 false/*isDead*/, false/*isUndef*/, 318 false/*isEarlyClobber*/, 319 0/*SubReg*/, IsDebug)); 320} 321 322/// AddOperand - Add the specified operand to the specified machine instr. II 323/// specifies the instruction information for the node, and IIOpNum is the 324/// operand number (in the II) that we are adding. IIOpNum and II are used for 325/// assertions only. 326void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 327 unsigned IIOpNum, 328 const TargetInstrDesc *II, 329 DenseMap<SDValue, unsigned> &VRBaseMap, 330 bool IsDebug, bool IsClone, bool IsCloned) { 331 if (Op.isMachineOpcode()) { 332 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 333 IsDebug, IsClone, IsCloned); 334 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 335 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 336 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 337 const ConstantFP *CFP = F->getConstantFPValue(); 338 MI->addOperand(MachineOperand::CreateFPImm(CFP)); 339 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 340 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 341 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 342 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 343 TGA->getTargetFlags())); 344 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 345 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 346 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 347 MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 348 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 349 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 350 JT->getTargetFlags())); 351 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 352 int Offset = CP->getOffset(); 353 unsigned Align = CP->getAlignment(); 354 const Type *Type = CP->getType(); 355 // MachineConstantPool wants an explicit alignment. 356 if (Align == 0) { 357 Align = TM->getTargetData()->getPrefTypeAlignment(Type); 358 if (Align == 0) { 359 // Alignment of vector types. FIXME! 360 Align = TM->getTargetData()->getTypeAllocSize(Type); 361 } 362 } 363 364 unsigned Idx; 365 MachineConstantPool *MCP = MF->getConstantPool(); 366 if (CP->isMachineConstantPoolEntry()) 367 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 368 else 369 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 370 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 371 CP->getTargetFlags())); 372 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 373 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 374 ES->getTargetFlags())); 375 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 376 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 377 BA->getTargetFlags())); 378 } else { 379 assert(Op.getValueType() != MVT::Other && 380 Op.getValueType() != MVT::Glue && 381 "Chain and glue operands should occur at end of operand list!"); 382 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 383 IsDebug, IsClone, IsCloned); 384 } 385} 386 387/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 388/// "SubIdx"'th sub-register class is the specified register class and whose 389/// type matches the specified type. 390static const TargetRegisterClass* 391getSuperRegisterRegClass(const TargetRegisterClass *TRC, 392 unsigned SubIdx, EVT VT) { 393 // Pick the register class of the superegister for this type 394 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 395 E = TRC->superregclasses_end(); I != E; ++I) 396 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 397 return *I; 398 assert(false && "Couldn't find the register class"); 399 return 0; 400} 401 402/// EmitSubregNode - Generate machine code for subreg nodes. 403/// 404void InstrEmitter::EmitSubregNode(SDNode *Node, 405 DenseMap<SDValue, unsigned> &VRBaseMap, 406 bool IsClone, bool IsCloned) { 407 unsigned VRBase = 0; 408 unsigned Opc = Node->getMachineOpcode(); 409 410 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 411 // the CopyToReg'd destination register instead of creating a new vreg. 412 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 413 UI != E; ++UI) { 414 SDNode *User = *UI; 415 if (User->getOpcode() == ISD::CopyToReg && 416 User->getOperand(2).getNode() == Node) { 417 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 418 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 419 VRBase = DestReg; 420 break; 421 } 422 } 423 } 424 425 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 426 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub 427 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 428 429 // Figure out the register class to create for the destreg. 430 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 431 MachineInstr *DefMI = MRI->getVRegDef(VReg); 432 unsigned SrcReg, DstReg, DefSubIdx; 433 if (DefMI && 434 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 435 SubIdx == DefSubIdx) { 436 // Optimize these: 437 // r1025 = s/zext r1024, 4 438 // r1026 = extract_subreg r1025, 4 439 // to a copy 440 // r1026 = copy r1024 441 const TargetRegisterClass *TRC = MRI->getRegClass(SrcReg); 442 VRBase = MRI->createVirtualRegister(TRC); 443 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 444 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 445 } else { 446 const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 447 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 448 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 449 450 // Figure out the register class to create for the destreg. 451 // Note that if we're going to directly use an existing register, 452 // it must be precisely the required class, and not a subclass 453 // thereof. 454 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 455 // Create the reg 456 assert(SRC && "Couldn't find source register class"); 457 VRBase = MRI->createVirtualRegister(SRC); 458 } 459 460 // Create the extract_subreg machine instruction. 461 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 462 TII->get(TargetOpcode::COPY), VRBase); 463 464 // Add source, and subreg index 465 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false, 466 IsClone, IsCloned); 467 assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg())&& 468 "Cannot yet extract from physregs"); 469 MI->getOperand(1).setSubReg(SubIdx); 470 MBB->insert(InsertPos, MI); 471 } 472 } else if (Opc == TargetOpcode::INSERT_SUBREG || 473 Opc == TargetOpcode::SUBREG_TO_REG) { 474 SDValue N0 = Node->getOperand(0); 475 SDValue N1 = Node->getOperand(1); 476 SDValue N2 = Node->getOperand(2); 477 unsigned SubReg = getVR(N1, VRBaseMap); 478 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 479 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 480 const TargetRegisterClass *SRC = 481 getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0)); 482 483 // Figure out the register class to create for the destreg. 484 // Note that if we're going to directly use an existing register, 485 // it must be precisely the required class, and not a subclass 486 // thereof. 487 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 488 // Create the reg 489 assert(SRC && "Couldn't find source register class"); 490 VRBase = MRI->createVirtualRegister(SRC); 491 } 492 493 // Create the insert_subreg or subreg_to_reg machine instruction. 494 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 495 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 496 497 // If creating a subreg_to_reg, then the first input operand 498 // is an implicit value immediate, otherwise it's a register 499 if (Opc == TargetOpcode::SUBREG_TO_REG) { 500 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 501 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 502 } else 503 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 504 IsClone, IsCloned); 505 // Add the subregster being inserted 506 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 507 IsClone, IsCloned); 508 MI->addOperand(MachineOperand::CreateImm(SubIdx)); 509 MBB->insert(InsertPos, MI); 510 } else 511 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 512 513 SDValue Op(Node, 0); 514 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 515 (void)isNew; // Silence compiler warning. 516 assert(isNew && "Node emitted out of order - early"); 517} 518 519/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 520/// COPY_TO_REGCLASS is just a normal copy, except that the destination 521/// register is constrained to be in a particular register class. 522/// 523void 524InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 525 DenseMap<SDValue, unsigned> &VRBaseMap) { 526 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 527 528 // Create the new VReg in the destination class and emit a copy. 529 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 530 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 531 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 532 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 533 NewVReg).addReg(VReg); 534 535 SDValue Op(Node, 0); 536 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 537 (void)isNew; // Silence compiler warning. 538 assert(isNew && "Node emitted out of order - early"); 539} 540 541/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 542/// 543void InstrEmitter::EmitRegSequence(SDNode *Node, 544 DenseMap<SDValue, unsigned> &VRBaseMap, 545 bool IsClone, bool IsCloned) { 546 const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0)); 547 unsigned NewVReg = MRI->createVirtualRegister(RC); 548 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 549 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 550 unsigned NumOps = Node->getNumOperands(); 551 assert((NumOps & 1) == 0 && 552 "REG_SEQUENCE must have an even number of operands!"); 553 const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 554 for (unsigned i = 0; i != NumOps; ++i) { 555 SDValue Op = Node->getOperand(i); 556 if (i & 1) { 557 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 558 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 559 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 560 const TargetRegisterClass *SRC = 561 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 562 if (SRC && SRC != RC) { 563 MRI->setRegClass(NewVReg, SRC); 564 RC = SRC; 565 } 566 } 567 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 568 IsClone, IsCloned); 569 } 570 571 MBB->insert(InsertPos, MI); 572 SDValue Op(Node, 0); 573 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 574 (void)isNew; // Silence compiler warning. 575 assert(isNew && "Node emitted out of order - early"); 576} 577 578/// EmitDbgValue - Generate machine instruction for a dbg_value node. 579/// 580MachineInstr * 581InstrEmitter::EmitDbgValue(SDDbgValue *SD, 582 DenseMap<SDValue, unsigned> &VRBaseMap) { 583 uint64_t Offset = SD->getOffset(); 584 MDNode* MDPtr = SD->getMDPtr(); 585 DebugLoc DL = SD->getDebugLoc(); 586 587 if (SD->getKind() == SDDbgValue::FRAMEIX) { 588 // Stack address; this needs to be lowered in target-dependent fashion. 589 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 590 unsigned FrameIx = SD->getFrameIx(); 591 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 592 } 593 // Otherwise, we're going to create an instruction here. 594 const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 595 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 596 if (SD->getKind() == SDDbgValue::SDNODE) { 597 SDNode *Node = SD->getSDNode(); 598 SDValue Op = SDValue(Node, SD->getResNo()); 599 // It's possible we replaced this SDNode with other(s) and therefore 600 // didn't generate code for it. It's better to catch these cases where 601 // they happen and transfer the debug info, but trying to guarantee that 602 // in all cases would be very fragile; this is a safeguard for any 603 // that were missed. 604 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 605 if (I==VRBaseMap.end()) 606 MIB.addReg(0U); // undef 607 else 608 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 609 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 610 } else if (SD->getKind() == SDDbgValue::CONST) { 611 const Value *V = SD->getConst(); 612 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 613 // FIXME: SDDbgValue constants aren't updated with legalization, so it's 614 // possible to have i128 constants in them at this point. Dwarf writer 615 // does not handle i128 constants at the moment so, as a crude workaround, 616 // just drop the debug info if this happens. 617 if (!CI->getValue().isSignedIntN(64)) 618 MIB.addReg(0U); 619 else 620 MIB.addImm(CI->getSExtValue()); 621 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 622 MIB.addFPImm(CF); 623 } else { 624 // Could be an Undef. In any case insert an Undef so we can see what we 625 // dropped. 626 MIB.addReg(0U); 627 } 628 } else { 629 // Insert an Undef so we can see what we dropped. 630 MIB.addReg(0U); 631 } 632 633 MIB.addImm(Offset).addMetadata(MDPtr); 634 return &*MIB; 635} 636 637/// EmitMachineNode - Generate machine code for a target-specific node and 638/// needed dependencies. 639/// 640void InstrEmitter:: 641EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 642 DenseMap<SDValue, unsigned> &VRBaseMap) { 643 unsigned Opc = Node->getMachineOpcode(); 644 645 // Handle subreg insert/extract specially 646 if (Opc == TargetOpcode::EXTRACT_SUBREG || 647 Opc == TargetOpcode::INSERT_SUBREG || 648 Opc == TargetOpcode::SUBREG_TO_REG) { 649 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 650 return; 651 } 652 653 // Handle COPY_TO_REGCLASS specially. 654 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 655 EmitCopyToRegClassNode(Node, VRBaseMap); 656 return; 657 } 658 659 // Handle REG_SEQUENCE specially. 660 if (Opc == TargetOpcode::REG_SEQUENCE) { 661 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 662 return; 663 } 664 665 if (Opc == TargetOpcode::IMPLICIT_DEF) 666 // We want a unique VR for each IMPLICIT_DEF use. 667 return; 668 669 const TargetInstrDesc &II = TII->get(Opc); 670 unsigned NumResults = CountResults(Node); 671 unsigned NodeOperands = CountOperands(Node); 672 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 673#ifndef NDEBUG 674 unsigned NumMIOperands = NodeOperands + NumResults; 675 if (II.isVariadic()) 676 assert(NumMIOperands >= II.getNumOperands() && 677 "Too few operands for a variadic node!"); 678 else 679 assert(NumMIOperands >= II.getNumOperands() && 680 NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 681 "#operands for dag node doesn't match .td file!"); 682#endif 683 684 // Create the new machine instruction. 685 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 686 687 // The MachineInstr constructor adds implicit-def operands. Scan through 688 // these to determine which are dead. 689 if (MI->getNumOperands() != 0 && 690 Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 691 // First, collect all used registers. 692 SmallVector<unsigned, 8> UsedRegs; 693 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) 694 if (F->getOpcode() == ISD::CopyFromReg) 695 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 696 else { 697 // Collect declared implicit uses. 698 const TargetInstrDesc &TID = TII->get(F->getMachineOpcode()); 699 UsedRegs.append(TID.getImplicitUses(), 700 TID.getImplicitUses() + TID.getNumImplicitUses()); 701 // In addition to declared implicit uses, we must also check for 702 // direct RegisterSDNode operands. 703 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 704 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 705 unsigned Reg = R->getReg(); 706 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) 707 UsedRegs.push_back(Reg); 708 } 709 } 710 // Then mark unused registers as dead. 711 MI->setPhysRegsDeadExcept(UsedRegs, *TRI); 712 } 713 714 // Add result register values for things that are defined by this 715 // instruction. 716 if (NumResults) 717 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 718 719 // Emit all of the actual operands of this instruction, adding them to the 720 // instruction as appropriate. 721 bool HasOptPRefs = II.getNumDefs() > NumResults; 722 assert((!HasOptPRefs || !HasPhysRegOuts) && 723 "Unable to cope with optional defs and phys regs defs!"); 724 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 725 for (unsigned i = NumSkip; i != NodeOperands; ++i) 726 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 727 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 728 729 // Transfer all of the memory reference descriptions of this instruction. 730 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 731 cast<MachineSDNode>(Node)->memoperands_end()); 732 733 // Insert the instruction into position in the block. This needs to 734 // happen before any custom inserter hook is called so that the 735 // hook knows where in the block to insert the replacement code. 736 MBB->insert(InsertPos, MI); 737 738 // Additional results must be physical register defs. 739 if (HasPhysRegOuts) { 740 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 741 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 742 if (Node->hasAnyUseOfValue(i)) 743 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 744 // If there are no uses, mark the register as dead now, so that 745 // MachineLICM/Sink can see that it's dead. Don't do this if the 746 // node has a Glue value, for the benefit of targets still using 747 // Glue for values in physregs. 748 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue) 749 MI->addRegisterDead(Reg, TRI); 750 } 751 } 752 753 // If the instruction has implicit defs and the node doesn't, mark the 754 // implicit def as dead. If the node has any glue outputs, we don't do this 755 // because we don't know what implicit defs are being used by glued nodes. 756 if (Node->getValueType(Node->getNumValues()-1) != MVT::Glue) 757 if (const unsigned *IDList = II.getImplicitDefs()) { 758 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 759 i != e; ++i) 760 MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 761 } 762} 763 764/// EmitSpecialNode - Generate machine code for a target-independent node and 765/// needed dependencies. 766void InstrEmitter:: 767EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 768 DenseMap<SDValue, unsigned> &VRBaseMap) { 769 switch (Node->getOpcode()) { 770 default: 771#ifndef NDEBUG 772 Node->dump(); 773#endif 774 llvm_unreachable("This target-independent node should have been selected!"); 775 break; 776 case ISD::EntryToken: 777 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 778 break; 779 case ISD::MERGE_VALUES: 780 case ISD::TokenFactor: // fall thru 781 break; 782 case ISD::CopyToReg: { 783 unsigned SrcReg; 784 SDValue SrcVal = Node->getOperand(2); 785 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 786 SrcReg = R->getReg(); 787 else 788 SrcReg = getVR(SrcVal, VRBaseMap); 789 790 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 791 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 792 break; 793 794 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 795 DestReg).addReg(SrcReg); 796 break; 797 } 798 case ISD::CopyFromReg: { 799 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 800 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 801 break; 802 } 803 case ISD::EH_LABEL: { 804 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 805 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 806 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 807 break; 808 } 809 810 case ISD::INLINEASM: { 811 unsigned NumOps = Node->getNumOperands(); 812 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 813 --NumOps; // Ignore the glue operand. 814 815 // Create the inline asm machine instruction. 816 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 817 TII->get(TargetOpcode::INLINEASM)); 818 819 // Add the asm string as an external symbol operand. 820 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 821 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 822 MI->addOperand(MachineOperand::CreateES(AsmStr)); 823 824 // Add the HasSideEffect and isAlignStack bits. 825 int64_t ExtraInfo = 826 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 827 getZExtValue(); 828 MI->addOperand(MachineOperand::CreateImm(ExtraInfo)); 829 830 // Add all of the operand registers to the instruction. 831 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 832 unsigned Flags = 833 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 834 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 835 836 MI->addOperand(MachineOperand::CreateImm(Flags)); 837 ++i; // Skip the ID value. 838 839 switch (InlineAsm::getKind(Flags)) { 840 default: llvm_unreachable("Bad flags!"); 841 case InlineAsm::Kind_RegDef: 842 for (; NumVals; --NumVals, ++i) { 843 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 844 // FIXME: Add dead flags for physical and virtual registers defined. 845 // For now, mark physical register defs as implicit to help fast 846 // regalloc. This makes inline asm look a lot like calls. 847 MI->addOperand(MachineOperand::CreateReg(Reg, true, 848 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg))); 849 } 850 break; 851 case InlineAsm::Kind_RegDefEarlyClobber: 852 for (; NumVals; --NumVals, ++i) { 853 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 854 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true, 855 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg), 856 /*isKill=*/ false, 857 /*isDead=*/ false, 858 /*isUndef=*/false, 859 /*isEarlyClobber=*/ true)); 860 } 861 break; 862 case InlineAsm::Kind_RegUse: // Use of register. 863 case InlineAsm::Kind_Imm: // Immediate. 864 case InlineAsm::Kind_Mem: // Addressing mode. 865 // The addressing mode has been selected, just add all of the 866 // operands to the machine instruction. 867 for (; NumVals; --NumVals, ++i) 868 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap, 869 /*IsDebug=*/false, IsClone, IsCloned); 870 break; 871 } 872 } 873 874 // Get the mdnode from the asm if it exists and add it to the instruction. 875 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 876 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 877 if (MD) 878 MI->addOperand(MachineOperand::CreateMetadata(MD)); 879 880 MBB->insert(InsertPos, MI); 881 break; 882 } 883 } 884} 885 886/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 887/// at the given position in the given block. 888InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 889 MachineBasicBlock::iterator insertpos) 890 : MF(mbb->getParent()), 891 MRI(&MF->getRegInfo()), 892 TM(&MF->getTarget()), 893 TII(TM->getInstrInfo()), 894 TRI(TM->getRegisterInfo()), 895 TLI(TM->getTargetLowering()), 896 MBB(mbb), InsertPos(insertpos) { 897} 898