ARMISelLowering.cpp revision 0412957764de44f63657360a22ce5445a8c87628 
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMISelLowering.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/CallingConv.h"
24#include "llvm/Constants.h"
25#include "llvm/Function.h"
26#include "llvm/Instruction.h"
27#include "llvm/Intrinsics.h"
28#include "llvm/GlobalValue.h"
29#include "llvm/CodeGen/CallingConvLower.h"
30#include "llvm/CodeGen/MachineBasicBlock.h"
31#include "llvm/CodeGen/MachineFrameInfo.h"
32#include "llvm/CodeGen/MachineFunction.h"
33#include "llvm/CodeGen/MachineInstrBuilder.h"
34#include "llvm/CodeGen/MachineRegisterInfo.h"
35#include "llvm/CodeGen/PseudoSourceValue.h"
36#include "llvm/CodeGen/SelectionDAG.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/VectorExtras.h"
39#include "llvm/Support/MathExtras.h"
40using namespace llvm;
41
42static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
43                                   CCValAssign::LocInfo &LocInfo,
44                                   ISD::ArgFlagsTy &ArgFlags,
45                                   CCState &State);
46static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
47                                    CCValAssign::LocInfo &LocInfo,
48                                    ISD::ArgFlagsTy &ArgFlags,
49                                    CCState &State);
50static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
51                                      CCValAssign::LocInfo &LocInfo,
52                                      ISD::ArgFlagsTy &ArgFlags,
53                                      CCState &State);
54static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
55                                       CCValAssign::LocInfo &LocInfo,
56                                       ISD::ArgFlagsTy &ArgFlags,
57                                       CCState &State);
58
59void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
60                                       MVT PromotedBitwiseVT) {
61  if (VT != PromotedLdStVT) {
62    setOperationAction(ISD::LOAD, VT, Promote);
63    AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
64
65    setOperationAction(ISD::STORE, VT, Promote);
66    AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
67  }
68
69  MVT ElemTy = VT.getVectorElementType();
70  if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
71    setOperationAction(ISD::VSETCC, VT, Custom);
72  if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
73    setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
74  setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
75  setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
76  setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
77  setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
78  if (VT.isInteger()) {
79    setOperationAction(ISD::SHL, VT, Custom);
80    setOperationAction(ISD::SRA, VT, Custom);
81    setOperationAction(ISD::SRL, VT, Custom);
82  }
83
84  // Promote all bit-wise operations.
85  if (VT.isInteger() && VT != PromotedBitwiseVT) {
86    setOperationAction(ISD::AND, VT, Promote);
87    AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
88    setOperationAction(ISD::OR,  VT, Promote);
89    AddPromotedToType (ISD::OR,  VT, PromotedBitwiseVT);
90    setOperationAction(ISD::XOR, VT, Promote);
91    AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
92  }
93}
94
95void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
96  addRegisterClass(VT, ARM::DPRRegisterClass);
97  addTypeForNEON(VT, MVT::f64, MVT::v2i32);
98}
99
100void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
101  addRegisterClass(VT, ARM::QPRRegisterClass);
102  addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
103}
104
105ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
106    : TargetLowering(TM), ARMPCLabelIndex(0) {
107  Subtarget = &TM.getSubtarget<ARMSubtarget>();
108
109  if (Subtarget->isTargetDarwin()) {
110    // Uses VFP for Thumb libfuncs if available.
111    if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
112      // Single-precision floating-point arithmetic.
113      setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
114      setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
115      setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
116      setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
117
118      // Double-precision floating-point arithmetic.
119      setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
120      setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
121      setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
122      setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
123
124      // Single-precision comparisons.
125      setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
126      setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
127      setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
128      setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
129      setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
130      setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
131      setLibcallName(RTLIB::UO_F32,  "__unordsf2vfp");
132      setLibcallName(RTLIB::O_F32,   "__unordsf2vfp");
133
134      setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
135      setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
136      setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
137      setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
138      setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
139      setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
140      setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
141      setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
142
143      // Double-precision comparisons.
144      setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
145      setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
146      setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
147      setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
148      setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
149      setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
150      setLibcallName(RTLIB::UO_F64,  "__unorddf2vfp");
151      setLibcallName(RTLIB::O_F64,   "__unorddf2vfp");
152
153      setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
154      setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
155      setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
156      setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
157      setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
158      setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
159      setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
160      setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
161
162      // Floating-point to integer conversions.
163      // i64 conversions are done via library routines even when generating VFP
164      // instructions, so use the same ones.
165      setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
166      setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
167      setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
168      setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
169
170      // Conversions between floating types.
171      setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
172      setLibcallName(RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp");
173
174      // Integer to floating-point conversions.
175      // i64 conversions are done via library routines even when generating VFP
176      // instructions, so use the same ones.
177      // FIXME: There appears to be some naming inconsistency in ARM libgcc:
178      // e.g., __floatunsidf vs. __floatunssidfvfp.
179      setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
180      setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
181      setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
182      setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
183    }
184  }
185
186  // These libcalls are not available in 32-bit.
187  setLibcallName(RTLIB::SHL_I128, 0);
188  setLibcallName(RTLIB::SRL_I128, 0);
189  setLibcallName(RTLIB::SRA_I128, 0);
190
191  if (Subtarget->isThumb())
192    addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
193  else
194    addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
195  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
196    addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
197    addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
198
199    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
200  }
201
202  if (Subtarget->hasNEON()) {
203    addDRTypeForNEON(MVT::v2f32);
204    addDRTypeForNEON(MVT::v8i8);
205    addDRTypeForNEON(MVT::v4i16);
206    addDRTypeForNEON(MVT::v2i32);
207    addDRTypeForNEON(MVT::v1i64);
208
209    addQRTypeForNEON(MVT::v4f32);
210    addQRTypeForNEON(MVT::v2f64);
211    addQRTypeForNEON(MVT::v16i8);
212    addQRTypeForNEON(MVT::v8i16);
213    addQRTypeForNEON(MVT::v4i32);
214    addQRTypeForNEON(MVT::v2i64);
215
216    setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
217    setTargetDAGCombine(ISD::SHL);
218    setTargetDAGCombine(ISD::SRL);
219    setTargetDAGCombine(ISD::SRA);
220    setTargetDAGCombine(ISD::SIGN_EXTEND);
221    setTargetDAGCombine(ISD::ZERO_EXTEND);
222    setTargetDAGCombine(ISD::ANY_EXTEND);
223  }
224
225  computeRegisterProperties();
226
227  // ARM does not have f32 extending load.
228  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
229
230  // ARM does not have i1 sign extending load.
231  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232
233  // ARM supports all 4 flavors of integer indexed load / store.
234  for (unsigned im = (unsigned)ISD::PRE_INC;
235       im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
236    setIndexedLoadAction(im,  MVT::i1,  Legal);
237    setIndexedLoadAction(im,  MVT::i8,  Legal);
238    setIndexedLoadAction(im,  MVT::i16, Legal);
239    setIndexedLoadAction(im,  MVT::i32, Legal);
240    setIndexedStoreAction(im, MVT::i1,  Legal);
241    setIndexedStoreAction(im, MVT::i8,  Legal);
242    setIndexedStoreAction(im, MVT::i16, Legal);
243    setIndexedStoreAction(im, MVT::i32, Legal);
244  }
245
246  // i64 operation support.
247  if (Subtarget->isThumb()) {
248    setOperationAction(ISD::MUL,     MVT::i64, Expand);
249    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
250    setOperationAction(ISD::MULHS,   MVT::i32, Expand);
251    setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
252    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
253  } else {
254    setOperationAction(ISD::MUL,     MVT::i64, Expand);
255    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
256    if (!Subtarget->hasV6Ops())
257      setOperationAction(ISD::MULHS, MVT::i32, Expand);
258  }
259  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
260  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
261  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
262  setOperationAction(ISD::SRL,       MVT::i64, Custom);
263  setOperationAction(ISD::SRA,       MVT::i64, Custom);
264
265  // ARM does not have ROTL.
266  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
267  setOperationAction(ISD::CTTZ,  MVT::i32, Expand);
268  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
269  if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
270    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
271
272  // Only ARMv6 has BSWAP.
273  if (!Subtarget->hasV6Ops())
274    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
275
276  // These are expanded into libcalls.
277  setOperationAction(ISD::SDIV,  MVT::i32, Expand);
278  setOperationAction(ISD::UDIV,  MVT::i32, Expand);
279  setOperationAction(ISD::SREM,  MVT::i32, Expand);
280  setOperationAction(ISD::UREM,  MVT::i32, Expand);
281  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
282  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
283
284  // Support label based line numbers.
285  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
286  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
287
288  setOperationAction(ISD::RET,           MVT::Other, Custom);
289  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
290  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
291  setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
292  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
293
294  // Use the default implementation.
295  setOperationAction(ISD::VASTART,            MVT::Other, Custom);
296  setOperationAction(ISD::VAARG,              MVT::Other, Expand);
297  setOperationAction(ISD::VACOPY,             MVT::Other, Expand);
298  setOperationAction(ISD::VAEND,              MVT::Other, Expand);
299  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
300  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
301  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32,   Expand);
302  setOperationAction(ISD::MEMBARRIER,         MVT::Other, Expand);
303
304  if (!Subtarget->hasV6Ops()) {
305    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
306    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
307  }
308  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
309
310  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
311    // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
312    setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
313
314  // We want to custom lower some of our intrinsics.
315  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
316
317  setOperationAction(ISD::SETCC,     MVT::i32, Expand);
318  setOperationAction(ISD::SETCC,     MVT::f32, Expand);
319  setOperationAction(ISD::SETCC,     MVT::f64, Expand);
320  setOperationAction(ISD::SELECT,    MVT::i32, Expand);
321  setOperationAction(ISD::SELECT,    MVT::f32, Expand);
322  setOperationAction(ISD::SELECT,    MVT::f64, Expand);
323  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
324  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
325  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
326
327  setOperationAction(ISD::BRCOND,    MVT::Other, Expand);
328  setOperationAction(ISD::BR_CC,     MVT::i32,   Custom);
329  setOperationAction(ISD::BR_CC,     MVT::f32,   Custom);
330  setOperationAction(ISD::BR_CC,     MVT::f64,   Custom);
331  setOperationAction(ISD::BR_JT,     MVT::Other, Custom);
332
333  // We don't support sin/cos/fmod/copysign/pow
334  setOperationAction(ISD::FSIN,      MVT::f64, Expand);
335  setOperationAction(ISD::FSIN,      MVT::f32, Expand);
336  setOperationAction(ISD::FCOS,      MVT::f32, Expand);
337  setOperationAction(ISD::FCOS,      MVT::f64, Expand);
338  setOperationAction(ISD::FREM,      MVT::f64, Expand);
339  setOperationAction(ISD::FREM,      MVT::f32, Expand);
340  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
341    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
342    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
343  }
344  setOperationAction(ISD::FPOW,      MVT::f64, Expand);
345  setOperationAction(ISD::FPOW,      MVT::f32, Expand);
346
347  // int <-> fp are custom expanded into bit_convert + ARMISD ops.
348  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
349    setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
350    setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
351    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
352    setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
353  }
354
355  // We have target-specific dag combine patterns for the following nodes:
356  // ARMISD::FMRRD  - No need to call setTargetDAGCombine
357  setTargetDAGCombine(ISD::ADD);
358  setTargetDAGCombine(ISD::SUB);
359
360  setStackPointerRegisterToSaveRestore(ARM::SP);
361  setSchedulingPreference(SchedulingForRegPressure);
362  setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
363  setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
364
365  if (!Subtarget->isThumb()) {
366    // Use branch latency information to determine if-conversion limits.
367    // FIXME: If-converter should use instruction latency of the branch being
368    // eliminated to compute the threshold. For ARMv6, the branch "latency"
369    // varies depending on whether it's dynamically or statically predicted
370    // and on whether the destination is in the prefetch buffer.
371    const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
372    const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
373    unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass());
374    if (Latency > 1) {
375      setIfCvtBlockSizeLimit(Latency-1);
376      if (Latency > 2)
377        setIfCvtDupBlockSizeLimit(Latency-2);
378    } else {
379      setIfCvtBlockSizeLimit(10);
380      setIfCvtDupBlockSizeLimit(2);
381    }
382  }
383
384  maxStoresPerMemcpy = 1;   //// temporary - rewrite interface to use type
385  // Do not enable CodePlacementOpt for now: it currently runs after the
386  // ARMConstantIslandPass and messes up branch relaxation and placement
387  // of constant islands.
388  // benefitFromCodePlacementOpt = true;
389}
390
391const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
392  switch (Opcode) {
393  default: return 0;
394  case ARMISD::Wrapper:       return "ARMISD::Wrapper";
395  case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
396  case ARMISD::CALL:          return "ARMISD::CALL";
397  case ARMISD::CALL_PRED:     return "ARMISD::CALL_PRED";
398  case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
399  case ARMISD::tCALL:         return "ARMISD::tCALL";
400  case ARMISD::BRCOND:        return "ARMISD::BRCOND";
401  case ARMISD::BR_JT:         return "ARMISD::BR_JT";
402  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
403  case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
404  case ARMISD::CMP:           return "ARMISD::CMP";
405  case ARMISD::CMPZ:          return "ARMISD::CMPZ";
406  case ARMISD::CMPFP:         return "ARMISD::CMPFP";
407  case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
408  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
409  case ARMISD::CMOV:          return "ARMISD::CMOV";
410  case ARMISD::CNEG:          return "ARMISD::CNEG";
411
412  case ARMISD::FTOSI:         return "ARMISD::FTOSI";
413  case ARMISD::FTOUI:         return "ARMISD::FTOUI";
414  case ARMISD::SITOF:         return "ARMISD::SITOF";
415  case ARMISD::UITOF:         return "ARMISD::UITOF";
416
417  case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
418  case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
419  case ARMISD::RRX:           return "ARMISD::RRX";
420
421  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
422  case ARMISD::FMDRR:         return "ARMISD::FMDRR";
423
424  case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
425
426  case ARMISD::VCEQ:          return "ARMISD::VCEQ";
427  case ARMISD::VCGE:          return "ARMISD::VCGE";
428  case ARMISD::VCGEU:         return "ARMISD::VCGEU";
429  case ARMISD::VCGT:          return "ARMISD::VCGT";
430  case ARMISD::VCGTU:         return "ARMISD::VCGTU";
431  case ARMISD::VTST:          return "ARMISD::VTST";
432
433  case ARMISD::VSHL:          return "ARMISD::VSHL";
434  case ARMISD::VSHRs:         return "ARMISD::VSHRs";
435  case ARMISD::VSHRu:         return "ARMISD::VSHRu";
436  case ARMISD::VSHLLs:        return "ARMISD::VSHLLs";
437  case ARMISD::VSHLLu:        return "ARMISD::VSHLLu";
438  case ARMISD::VSHLLi:        return "ARMISD::VSHLLi";
439  case ARMISD::VSHRN:         return "ARMISD::VSHRN";
440  case ARMISD::VRSHRs:        return "ARMISD::VRSHRs";
441  case ARMISD::VRSHRu:        return "ARMISD::VRSHRu";
442  case ARMISD::VRSHRN:        return "ARMISD::VRSHRN";
443  case ARMISD::VQSHLs:        return "ARMISD::VQSHLs";
444  case ARMISD::VQSHLu:        return "ARMISD::VQSHLu";
445  case ARMISD::VQSHLsu:       return "ARMISD::VQSHLsu";
446  case ARMISD::VQSHRNs:       return "ARMISD::VQSHRNs";
447  case ARMISD::VQSHRNu:       return "ARMISD::VQSHRNu";
448  case ARMISD::VQSHRNsu:      return "ARMISD::VQSHRNsu";
449  case ARMISD::VQRSHRNs:      return "ARMISD::VQRSHRNs";
450  case ARMISD::VQRSHRNu:      return "ARMISD::VQRSHRNu";
451  case ARMISD::VQRSHRNsu:     return "ARMISD::VQRSHRNsu";
452  case ARMISD::VGETLANEu:     return "ARMISD::VGETLANEu";
453  case ARMISD::VGETLANEs:     return "ARMISD::VGETLANEs";
454  case ARMISD::VDUPLANEQ:     return "ARMISD::VDUPLANEQ";
455  }
456}
457
458/// getFunctionAlignment - Return the Log2 alignment of this function.
459unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
460  return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
461}
462
463//===----------------------------------------------------------------------===//
464// Lowering Code
465//===----------------------------------------------------------------------===//
466
467/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
468static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
469  switch (CC) {
470  default: assert(0 && "Unknown condition code!");
471  case ISD::SETNE:  return ARMCC::NE;
472  case ISD::SETEQ:  return ARMCC::EQ;
473  case ISD::SETGT:  return ARMCC::GT;
474  case ISD::SETGE:  return ARMCC::GE;
475  case ISD::SETLT:  return ARMCC::LT;
476  case ISD::SETLE:  return ARMCC::LE;
477  case ISD::SETUGT: return ARMCC::HI;
478  case ISD::SETUGE: return ARMCC::HS;
479  case ISD::SETULT: return ARMCC::LO;
480  case ISD::SETULE: return ARMCC::LS;
481  }
482}
483
484/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
485/// returns true if the operands should be inverted to form the proper
486/// comparison.
487static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
488                        ARMCC::CondCodes &CondCode2) {
489  bool Invert = false;
490  CondCode2 = ARMCC::AL;
491  switch (CC) {
492  default: assert(0 && "Unknown FP condition!");
493  case ISD::SETEQ:
494  case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
495  case ISD::SETGT:
496  case ISD::SETOGT: CondCode = ARMCC::GT; break;
497  case ISD::SETGE:
498  case ISD::SETOGE: CondCode = ARMCC::GE; break;
499  case ISD::SETOLT: CondCode = ARMCC::MI; break;
500  case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
501  case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
502  case ISD::SETO:   CondCode = ARMCC::VC; break;
503  case ISD::SETUO:  CondCode = ARMCC::VS; break;
504  case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
505  case ISD::SETUGT: CondCode = ARMCC::HI; break;
506  case ISD::SETUGE: CondCode = ARMCC::PL; break;
507  case ISD::SETLT:
508  case ISD::SETULT: CondCode = ARMCC::LT; break;
509  case ISD::SETLE:
510  case ISD::SETULE: CondCode = ARMCC::LE; break;
511  case ISD::SETNE:
512  case ISD::SETUNE: CondCode = ARMCC::NE; break;
513  }
514  return Invert;
515}
516
517//===----------------------------------------------------------------------===//
518//                      Calling Convention Implementation
519//
520//  The lower operations present on calling convention works on this order:
521//      LowerCALL (virt regs --> phys regs, virt regs --> stack)
522//      LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
523//      LowerRET (virt regs --> phys regs)
524//      LowerCALL (phys regs --> virt regs)
525//
526//===----------------------------------------------------------------------===//
527
528#include "ARMGenCallingConv.inc"
529
530// APCS f64 is in register pairs, possibly split to stack
531static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
532                          CCValAssign::LocInfo &LocInfo,
533                          CCState &State, bool CanFail) {
534  static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
535
536  // Try to get the first register.
537  if (unsigned Reg = State.AllocateReg(RegList, 4))
538    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
539  else {
540    // For the 2nd half of a v2f64, do not fail.
541    if (CanFail)
542      return false;
543
544    // Put the whole thing on the stack.
545    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
546                                           State.AllocateStack(8, 4),
547                                           LocVT, LocInfo));
548    return true;
549  }
550
551  // Try to get the second register.
552  if (unsigned Reg = State.AllocateReg(RegList, 4))
553    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
554  else
555    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
556                                           State.AllocateStack(4, 4),
557                                           LocVT, LocInfo));
558  return true;
559}
560
561static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
562                                   CCValAssign::LocInfo &LocInfo,
563                                   ISD::ArgFlagsTy &ArgFlags,
564                                   CCState &State) {
565  if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
566    return false;
567  if (LocVT == MVT::v2f64 &&
568      !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
569    return false;
570  return true;  // we handled it
571}
572
573// AAPCS f64 is in aligned register pairs
574static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
575                           CCValAssign::LocInfo &LocInfo,
576                           CCState &State, bool CanFail) {
577  static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
578  static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
579
580  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
581  if (Reg == 0) {
582    // For the 2nd half of a v2f64, do not just fail.
583    if (CanFail)
584      return false;
585
586    // Put the whole thing on the stack.
587    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
588                                           State.AllocateStack(8, 8),
589                                           LocVT, LocInfo));
590    return true;
591  }
592
593  unsigned i;
594  for (i = 0; i < 2; ++i)
595    if (HiRegList[i] == Reg)
596      break;
597
598  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
599  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
600                                         LocVT, LocInfo));
601  return true;
602}
603
604static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
605                                    CCValAssign::LocInfo &LocInfo,
606                                    ISD::ArgFlagsTy &ArgFlags,
607                                    CCState &State) {
608  if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
609    return false;
610  if (LocVT == MVT::v2f64 &&
611      !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
612    return false;
613  return true;  // we handled it
614}
615
616static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
617                         CCValAssign::LocInfo &LocInfo, CCState &State) {
618  static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
619  static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
620
621  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
622  if (Reg == 0)
623    return false; // we didn't handle it
624
625  unsigned i;
626  for (i = 0; i < 2; ++i)
627    if (HiRegList[i] == Reg)
628      break;
629
630  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
631  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
632                                         LocVT, LocInfo));
633  return true;
634}
635
636static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
637                                      CCValAssign::LocInfo &LocInfo,
638                                      ISD::ArgFlagsTy &ArgFlags,
639                                      CCState &State) {
640  if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
641    return false;
642  if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
643    return false;
644  return true;  // we handled it
645}
646
647static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
648                                       CCValAssign::LocInfo &LocInfo,
649                                       ISD::ArgFlagsTy &ArgFlags,
650                                       CCState &State) {
651  return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
652                                   State);
653}
654
655/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
656/// given CallingConvention value.
657CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
658                                                 bool Return) const {
659  switch (CC) {
660  default:
661   assert(0 && "Unsupported calling convention");
662  case CallingConv::C:
663  case CallingConv::Fast:
664   // Use target triple & subtarget features to do actual dispatch.
665   if (Subtarget->isAAPCS_ABI()) {
666     if (Subtarget->hasVFP2() &&
667         FloatABIType == FloatABI::Hard)
668       return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
669     else
670       return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
671   } else
672     return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
673  case CallingConv::ARM_AAPCS_VFP:
674   return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
675  case CallingConv::ARM_AAPCS:
676   return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
677  case CallingConv::ARM_APCS:
678   return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
679  }
680}
681
682/// LowerCallResult - Lower the result values of an ISD::CALL into the
683/// appropriate copies out of appropriate physical registers.  This assumes that
684/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
685/// being lowered.  The returns a SDNode with the same number of values as the
686/// ISD::CALL.
687SDNode *ARMTargetLowering::
688LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
689                unsigned CallingConv, SelectionDAG &DAG) {
690
691  DebugLoc dl = TheCall->getDebugLoc();
692  // Assign locations to each value returned by this call.
693  SmallVector<CCValAssign, 16> RVLocs;
694  bool isVarArg = TheCall->isVarArg();
695  CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
696  CCInfo.AnalyzeCallResult(TheCall,
697                           CCAssignFnForNode(CallingConv, /* Return*/ true));
698
699  SmallVector<SDValue, 8> ResultVals;
700
701  // Copy all of the result registers out of their specified physreg.
702  for (unsigned i = 0; i != RVLocs.size(); ++i) {
703    CCValAssign VA = RVLocs[i];
704
705    SDValue Val;
706    if (VA.needsCustom()) {
707      // Handle f64 or half of a v2f64.
708      SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
709                                      InFlag);
710      Chain = Lo.getValue(1);
711      InFlag = Lo.getValue(2);
712      VA = RVLocs[++i]; // skip ahead to next loc
713      SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
714                                      InFlag);
715      Chain = Hi.getValue(1);
716      InFlag = Hi.getValue(2);
717      Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
718
719      if (VA.getLocVT() == MVT::v2f64) {
720        SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
721        Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
722                          DAG.getConstant(0, MVT::i32));
723
724        VA = RVLocs[++i]; // skip ahead to next loc
725        Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
726        Chain = Lo.getValue(1);
727        InFlag = Lo.getValue(2);
728        VA = RVLocs[++i]; // skip ahead to next loc
729        Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
730        Chain = Hi.getValue(1);
731        InFlag = Hi.getValue(2);
732        Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
733        Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
734                          DAG.getConstant(1, MVT::i32));
735      }
736    } else {
737      Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
738                               InFlag);
739      Chain = Val.getValue(1);
740      InFlag = Val.getValue(2);
741    }
742
743    switch (VA.getLocInfo()) {
744    default: assert(0 && "Unknown loc info!");
745    case CCValAssign::Full: break;
746    case CCValAssign::BCvt:
747      Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
748      break;
749    }
750
751    ResultVals.push_back(Val);
752  }
753
754  // Merge everything together with a MERGE_VALUES node.
755  ResultVals.push_back(Chain);
756  return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
757                     &ResultVals[0], ResultVals.size()).getNode();
758}
759
760/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
761/// by "Src" to address "Dst" of size "Size".  Alignment information is
762/// specified by the specific parameter attribute.  The copy will be passed as
763/// a byval function parameter.
764/// Sometimes what we are copying is the end of a larger object, the part that
765/// does not fit in registers.
766static SDValue
767CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
768                          ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
769                          DebugLoc dl) {
770  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
771  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
772                       /*AlwaysInline=*/false, NULL, 0, NULL, 0);
773}
774
775/// LowerMemOpCallTo - Store the argument to the stack.
776SDValue
777ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
778                                    const SDValue &StackPtr,
779                                    const CCValAssign &VA, SDValue Chain,
780                                    SDValue Arg, ISD::ArgFlagsTy Flags) {
781  DebugLoc dl = TheCall->getDebugLoc();
782  unsigned LocMemOffset = VA.getLocMemOffset();
783  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
784  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
785  if (Flags.isByVal()) {
786    return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
787  }
788  return DAG.getStore(Chain, dl, Arg, PtrOff,
789                      PseudoSourceValue::getStack(), LocMemOffset);
790}
791
792void ARMTargetLowering::PassF64ArgInRegs(CallSDNode *TheCall, SelectionDAG &DAG,
793                                         SDValue Chain, SDValue &Arg,
794                                         RegsToPassVector &RegsToPass,
795                                         CCValAssign &VA, CCValAssign &NextVA,
796                                         SDValue &StackPtr,
797                                         SmallVector<SDValue, 8> &MemOpChains,
798                                         ISD::ArgFlagsTy Flags) {
799  DebugLoc dl = TheCall->getDebugLoc();
800
801  SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
802                              DAG.getVTList(MVT::i32, MVT::i32), Arg);
803  RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
804
805  if (NextVA.isRegLoc())
806    RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
807  else {
808    assert(NextVA.isMemLoc());
809    if (StackPtr.getNode() == 0)
810      StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
811
812    MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, NextVA,
813                                           Chain, fmrrd.getValue(1), Flags));
814  }
815}
816
817/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
818/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
819/// nodes.
820SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
821  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
822  MVT RetVT           = TheCall->getRetValType(0);
823  SDValue Chain       = TheCall->getChain();
824  unsigned CC         = TheCall->getCallingConv();
825  bool isVarArg       = TheCall->isVarArg();
826  SDValue Callee      = TheCall->getCallee();
827  DebugLoc dl         = TheCall->getDebugLoc();
828
829  // Analyze operands of the call, assigning locations to each operand.
830  SmallVector<CCValAssign, 16> ArgLocs;
831  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
832  CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC, /* Return*/ false));
833
834  // Get a count of how many bytes are to be pushed on the stack.
835  unsigned NumBytes = CCInfo.getNextStackOffset();
836
837  // Adjust the stack pointer for the new arguments...
838  // These operations are automatically eliminated by the prolog/epilog pass
839  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
840
841  SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
842
843  RegsToPassVector RegsToPass;
844  SmallVector<SDValue, 8> MemOpChains;
845
846  // Walk the register/memloc assignments, inserting copies/loads.  In the case
847  // of tail call optimization, arguments are handled later.
848  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
849       i != e;
850       ++i, ++realArgIdx) {
851    CCValAssign &VA = ArgLocs[i];
852    SDValue Arg = TheCall->getArg(realArgIdx);
853    ISD::ArgFlagsTy Flags = TheCall->getArgFlags(realArgIdx);
854
855    // Promote the value if needed.
856    switch (VA.getLocInfo()) {
857    default: assert(0 && "Unknown loc info!");
858    case CCValAssign::Full: break;
859    case CCValAssign::SExt:
860      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
861      break;
862    case CCValAssign::ZExt:
863      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
864      break;
865    case CCValAssign::AExt:
866      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
867      break;
868    case CCValAssign::BCvt:
869      Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
870      break;
871    }
872
873    // f64 and v2f64 are passed in i32 pairs and must be split into pieces
874    if (VA.needsCustom()) {
875      if (VA.getLocVT() == MVT::v2f64) {
876        SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
877                                  DAG.getConstant(0, MVT::i32));
878        SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
879                                  DAG.getConstant(1, MVT::i32));
880
881        PassF64ArgInRegs(TheCall, DAG, Chain, Op0, RegsToPass,
882                         VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
883
884        VA = ArgLocs[++i]; // skip ahead to next loc
885        if (VA.isRegLoc()) {
886          PassF64ArgInRegs(TheCall, DAG, Chain, Op1, RegsToPass,
887                           VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
888        } else {
889          assert(VA.isMemLoc());
890          if (StackPtr.getNode() == 0)
891            StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
892
893          MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
894                                                 Chain, Op1, Flags));
895        }
896      } else {
897        PassF64ArgInRegs(TheCall, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
898                         StackPtr, MemOpChains, Flags);
899      }
900    } else if (VA.isRegLoc()) {
901      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
902    } else {
903      assert(VA.isMemLoc());
904      if (StackPtr.getNode() == 0)
905        StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
906
907      MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
908                                             Chain, Arg, Flags));
909    }
910  }
911
912  if (!MemOpChains.empty())
913    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
914                        &MemOpChains[0], MemOpChains.size());
915
916  // Build a sequence of copy-to-reg nodes chained together with token chain
917  // and flag operands which copy the outgoing args into the appropriate regs.
918  SDValue InFlag;
919  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
920    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
921                             RegsToPass[i].second, InFlag);
922    InFlag = Chain.getValue(1);
923  }
924
925  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
926  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
927  // node so that legalize doesn't hack it.
928  bool isDirect = false;
929  bool isARMFunc = false;
930  bool isLocalARMFunc = false;
931  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
932    GlobalValue *GV = G->getGlobal();
933    isDirect = true;
934    bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
935                  GV->hasLinkOnceLinkage());
936    bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
937                   getTargetMachine().getRelocationModel() != Reloc::Static;
938    isARMFunc = !Subtarget->isThumb() || isStub;
939    // ARM call to a local ARM function is predicable.
940    isLocalARMFunc = !Subtarget->isThumb() && !isExt;
941    // tBX takes a register source operand.
942    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
943      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
944                                                           ARMCP::CPStub, 4);
945      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
946      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
947      Callee = DAG.getLoad(getPointerTy(), dl,
948                           DAG.getEntryNode(), CPAddr, NULL, 0);
949      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
950      Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
951                           getPointerTy(), Callee, PICLabel);
952   } else
953      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
954  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
955    isDirect = true;
956    bool isStub = Subtarget->isTargetDarwin() &&
957                  getTargetMachine().getRelocationModel() != Reloc::Static;
958    isARMFunc = !Subtarget->isThumb() || isStub;
959    // tBX takes a register source operand.
960    const char *Sym = S->getSymbol();
961    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
962      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
963                                                           ARMCP::CPStub, 4);
964      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
965      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
966      Callee = DAG.getLoad(getPointerTy(), dl,
967                           DAG.getEntryNode(), CPAddr, NULL, 0);
968      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
969      Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
970                           getPointerTy(), Callee, PICLabel);
971    } else
972      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
973  }
974
975  // FIXME: handle tail calls differently.
976  unsigned CallOpc;
977  if (Subtarget->isThumb()) {
978    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
979      CallOpc = ARMISD::CALL_NOLINK;
980    else
981      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
982  } else {
983    CallOpc = (isDirect || Subtarget->hasV5TOps())
984      ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
985      : ARMISD::CALL_NOLINK;
986  }
987  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
988    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
989    Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
990    InFlag = Chain.getValue(1);
991  }
992
993  std::vector<SDValue> Ops;
994  Ops.push_back(Chain);
995  Ops.push_back(Callee);
996
997  // Add argument registers to the end of the list so that they are known live
998  // into the call.
999  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1000    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1001                                  RegsToPass[i].second.getValueType()));
1002
1003  if (InFlag.getNode())
1004    Ops.push_back(InFlag);
1005  // Returns a chain and a flag for retval copy to use.
1006  Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1007                      &Ops[0], Ops.size());
1008  InFlag = Chain.getValue(1);
1009
1010  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1011                             DAG.getIntPtrConstant(0, true), InFlag);
1012  if (RetVT != MVT::Other)
1013    InFlag = Chain.getValue(1);
1014
1015  // Handle result values, copying them out of physregs into vregs that we
1016  // return.
1017  return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1018                                 Op.getResNo());
1019}
1020
1021SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1022  // The chain is always operand #0
1023  SDValue Chain = Op.getOperand(0);
1024  DebugLoc dl = Op.getDebugLoc();
1025
1026  // CCValAssign - represent the assignment of the return value to a location.
1027  SmallVector<CCValAssign, 16> RVLocs;
1028  unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
1029  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1030
1031  // CCState - Info about the registers and stack slots.
1032  CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
1033
1034  // Analyze return values of ISD::RET.
1035  CCInfo.AnalyzeReturn(Op.getNode(), CCAssignFnForNode(CC, /* Return */ true));
1036
1037  // If this is the first return lowered for this function, add
1038  // the regs to the liveout set for the function.
1039  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1040    for (unsigned i = 0; i != RVLocs.size(); ++i)
1041      if (RVLocs[i].isRegLoc())
1042        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1043  }
1044
1045  SDValue Flag;
1046
1047  // Copy the result values into the output registers.
1048  for (unsigned i = 0, realRVLocIdx = 0;
1049       i != RVLocs.size();
1050       ++i, ++realRVLocIdx) {
1051    CCValAssign &VA = RVLocs[i];
1052    assert(VA.isRegLoc() && "Can only return in registers!");
1053
1054    // ISD::RET => ret chain, (regnum1,val1), ...
1055    // So i*2+1 index only the regnums
1056    SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
1057
1058    switch (VA.getLocInfo()) {
1059    default: assert(0 && "Unknown loc info!");
1060    case CCValAssign::Full: break;
1061    case CCValAssign::BCvt:
1062      Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1063      break;
1064    }
1065
1066    if (VA.needsCustom()) {
1067      if (VA.getLocVT() == MVT::v2f64) {
1068        // Extract the first half and return it in two registers.
1069        SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1070                                   DAG.getConstant(0, MVT::i32));
1071        SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1072                                       DAG.getVTList(MVT::i32, MVT::i32), Half);
1073
1074        Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1075        Flag = Chain.getValue(1);
1076        VA = RVLocs[++i]; // skip ahead to next loc
1077        Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1078                                 HalfGPRs.getValue(1), Flag);
1079        Flag = Chain.getValue(1);
1080        VA = RVLocs[++i]; // skip ahead to next loc
1081
1082        // Extract the 2nd half and fall through to handle it as an f64 value.
1083        Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1084                          DAG.getConstant(1, MVT::i32));
1085      }
1086      // Legalize ret f64 -> ret 2 x i32.  We always have fmrrd if f64 is
1087      // available.
1088      SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1089                                  DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1090      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1091      Flag = Chain.getValue(1);
1092      VA = RVLocs[++i]; // skip ahead to next loc
1093      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1094                               Flag);
1095    } else
1096      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1097
1098    // Guarantee that all emitted copies are
1099    // stuck together, avoiding something bad.
1100    Flag = Chain.getValue(1);
1101  }
1102
1103  SDValue result;
1104  if (Flag.getNode())
1105    result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1106  else // Return Void
1107    result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1108
1109  return result;
1110}
1111
1112// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1113// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
1114// one of the above mentioned nodes. It has to be wrapped because otherwise
1115// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1116// be used to form addressing mode. These wrapped nodes will be selected
1117// into MOVi.
1118static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1119  MVT PtrVT = Op.getValueType();
1120  // FIXME there is no actual debug info here
1121  DebugLoc dl = Op.getDebugLoc();
1122  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1123  SDValue Res;
1124  if (CP->isMachineConstantPoolEntry())
1125    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1126                                    CP->getAlignment());
1127  else
1128    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1129                                    CP->getAlignment());
1130  return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1131}
1132
1133// Lower ISD::GlobalTLSAddress using the "general dynamic" model
1134SDValue
1135ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1136                                                 SelectionDAG &DAG) {
1137  DebugLoc dl = GA->getDebugLoc();
1138  MVT PtrVT = getPointerTy();
1139  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1140  ARMConstantPoolValue *CPV =
1141    new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1142                             PCAdj, "tlsgd", true);
1143  SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1144  Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1145  Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1146  SDValue Chain = Argument.getValue(1);
1147
1148  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1149  Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1150
1151  // call __tls_get_addr.
1152  ArgListTy Args;
1153  ArgListEntry Entry;
1154  Entry.Node = Argument;
1155  Entry.Ty = (const Type *) Type::Int32Ty;
1156  Args.push_back(Entry);
1157  // FIXME: is there useful debug info available here?
1158  std::pair<SDValue, SDValue> CallResult =
1159    LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
1160                CallingConv::C, false,
1161                DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1162  return CallResult.first;
1163}
1164
1165// Lower ISD::GlobalTLSAddress using the "initial exec" or
1166// "local exec" model.
1167SDValue
1168ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1169                                        SelectionDAG &DAG) {
1170  GlobalValue *GV = GA->getGlobal();
1171  DebugLoc dl = GA->getDebugLoc();
1172  SDValue Offset;
1173  SDValue Chain = DAG.getEntryNode();
1174  MVT PtrVT = getPointerTy();
1175  // Get the Thread Pointer
1176  SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1177
1178  if (GV->isDeclaration()){
1179    // initial exec model
1180    unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1181    ARMConstantPoolValue *CPV =
1182      new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1183                               PCAdj, "gottpoff", true);
1184    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1185    Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1186    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1187    Chain = Offset.getValue(1);
1188
1189    SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1190    Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1191
1192    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1193  } else {
1194    // local exec model
1195    ARMConstantPoolValue *CPV =
1196      new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1197    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1198    Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1199    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1200  }
1201
1202  // The address of the thread local variable is the add of the thread
1203  // pointer with the offset of the variable.
1204  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1205}
1206
1207SDValue
1208ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1209  // TODO: implement the "local dynamic" model
1210  assert(Subtarget->isTargetELF() &&
1211         "TLS not implemented for non-ELF targets");
1212  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1213  // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1214  // otherwise use the "Local Exec" TLS Model
1215  if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1216    return LowerToTLSGeneralDynamicModel(GA, DAG);
1217  else
1218    return LowerToTLSExecModels(GA, DAG);
1219}
1220
1221SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1222                                                 SelectionDAG &DAG) {
1223  MVT PtrVT = getPointerTy();
1224  DebugLoc dl = Op.getDebugLoc();
1225  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1226  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1227  if (RelocM == Reloc::PIC_) {
1228    bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1229    ARMConstantPoolValue *CPV =
1230      new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1231    SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1232    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1233    SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1234                                 CPAddr, NULL, 0);
1235    SDValue Chain = Result.getValue(1);
1236    SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1237    Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1238    if (!UseGOTOFF)
1239      Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1240    return Result;
1241  } else {
1242    SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1243    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1244    return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1245  }
1246}
1247
1248/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1249/// even in non-static mode.
1250static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1251  // If symbol visibility is hidden, the extra load is not needed if
1252  // the symbol is definitely defined in the current translation unit.
1253  bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
1254  if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1255    return false;
1256  return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1257}
1258
1259SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1260                                                    SelectionDAG &DAG) {
1261  MVT PtrVT = getPointerTy();
1262  DebugLoc dl = Op.getDebugLoc();
1263  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1264  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1265  bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1266  SDValue CPAddr;
1267  if (RelocM == Reloc::Static)
1268    CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1269  else {
1270    unsigned PCAdj = (RelocM != Reloc::PIC_)
1271      ? 0 : (Subtarget->isThumb() ? 4 : 8);
1272    ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1273      : ARMCP::CPValue;
1274    ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1275                                                         Kind, PCAdj);
1276    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1277  }
1278  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1279
1280  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1281  SDValue Chain = Result.getValue(1);
1282
1283  if (RelocM == Reloc::PIC_) {
1284    SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1285    Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1286  }
1287  if (IsIndirect)
1288    Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1289
1290  return Result;
1291}
1292
1293SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1294                                                    SelectionDAG &DAG){
1295  assert(Subtarget->isTargetELF() &&
1296         "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1297  MVT PtrVT = getPointerTy();
1298  DebugLoc dl = Op.getDebugLoc();
1299  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1300  ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1301                                                       ARMPCLabelIndex,
1302                                                       ARMCP::CPValue, PCAdj);
1303  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1304  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1305  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1306  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1307  return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1308}
1309
1310SDValue
1311ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1312  MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1313  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1314  DebugLoc dl = Op.getDebugLoc();
1315  switch (IntNo) {
1316  default: return SDValue();    // Don't custom lower most intrinsics.
1317  case Intrinsic::arm_thread_pointer:
1318      return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1319  case Intrinsic::eh_sjlj_setjmp:
1320      SDValue Res = DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32,
1321                         Op.getOperand(1));
1322      return Res;
1323  }
1324}
1325
1326static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1327                            unsigned VarArgsFrameIndex) {
1328  // vastart just stores the address of the VarArgsFrameIndex slot into the
1329  // memory location argument.
1330  DebugLoc dl = Op.getDebugLoc();
1331  MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1332  SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1333  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1334  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1335}
1336
1337SDValue
1338ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1339                                        SDValue &Root, SelectionDAG &DAG,
1340                                        DebugLoc dl) {
1341  MachineFunction &MF = DAG.getMachineFunction();
1342  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1343
1344  TargetRegisterClass *RC;
1345  if (AFI->isThumbFunction())
1346    RC = ARM::tGPRRegisterClass;
1347  else
1348    RC = ARM::GPRRegisterClass;
1349
1350  // Transform the arguments stored in physical registers into virtual ones.
1351  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1352  SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1353
1354  SDValue ArgValue2;
1355  if (NextVA.isMemLoc()) {
1356    unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1357    MachineFrameInfo *MFI = MF.getFrameInfo();
1358    int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1359
1360    // Create load node to retrieve arguments from the stack.
1361    SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1362    ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1363  } else {
1364    Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1365    ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1366  }
1367
1368  return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1369}
1370
1371SDValue
1372ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1373  MachineFunction &MF = DAG.getMachineFunction();
1374  MachineFrameInfo *MFI = MF.getFrameInfo();
1375
1376  SDValue Root = Op.getOperand(0);
1377  DebugLoc dl = Op.getDebugLoc();
1378  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1379  unsigned CC = MF.getFunction()->getCallingConv();
1380  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1381
1382  // Assign locations to all of the incoming arguments.
1383  SmallVector<CCValAssign, 16> ArgLocs;
1384  CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1385  CCInfo.AnalyzeFormalArguments(Op.getNode(),
1386                                CCAssignFnForNode(CC, /* Return*/ false));
1387
1388  SmallVector<SDValue, 16> ArgValues;
1389
1390  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1391    CCValAssign &VA = ArgLocs[i];
1392
1393    // Arguments stored in registers.
1394    if (VA.isRegLoc()) {
1395      MVT RegVT = VA.getLocVT();
1396
1397      SDValue ArgValue;
1398      if (VA.needsCustom()) {
1399        // f64 and vector types are split up into multiple registers or
1400        // combinations of registers and stack slots.
1401        RegVT = MVT::i32;
1402
1403        if (VA.getLocVT() == MVT::v2f64) {
1404          SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1405                                                   Root, DAG, dl);
1406          VA = ArgLocs[++i]; // skip ahead to next loc
1407          SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1408                                                   Root, DAG, dl);
1409          ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1410          ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1411                                 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1412          ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1413                                 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1414        } else
1415          ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Root, DAG, dl);
1416
1417      } else {
1418        TargetRegisterClass *RC;
1419        if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32)
1420          RC = ARM::SPRRegisterClass;
1421        else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)
1422          RC = ARM::DPRRegisterClass;
1423        else if (AFI->isThumbFunction())
1424          RC = ARM::tGPRRegisterClass;
1425        else
1426          RC = ARM::GPRRegisterClass;
1427
1428        assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
1429                (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)) &&
1430               "RegVT not supported by FORMAL_ARGUMENTS Lowering");
1431
1432        // Transform the arguments in physical registers into virtual ones.
1433        unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1434        ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1435      }
1436
1437      // If this is an 8 or 16-bit value, it is really passed promoted
1438      // to 32 bits.  Insert an assert[sz]ext to capture this, then
1439      // truncate to the right size.
1440      switch (VA.getLocInfo()) {
1441      default: assert(0 && "Unknown loc info!");
1442      case CCValAssign::Full: break;
1443      case CCValAssign::BCvt:
1444        ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1445        break;
1446      case CCValAssign::SExt:
1447        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1448                               DAG.getValueType(VA.getValVT()));
1449        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1450        break;
1451      case CCValAssign::ZExt:
1452        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1453                               DAG.getValueType(VA.getValVT()));
1454        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1455        break;
1456      }
1457
1458      ArgValues.push_back(ArgValue);
1459
1460    } else { // VA.isRegLoc()
1461
1462      // sanity check
1463      assert(VA.isMemLoc());
1464      assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1465
1466      unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1467      int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1468
1469      // Create load nodes to retrieve arguments from the stack.
1470      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1471      ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1472    }
1473  }
1474
1475  // varargs
1476  if (isVarArg) {
1477    static const unsigned GPRArgRegs[] = {
1478      ARM::R0, ARM::R1, ARM::R2, ARM::R3
1479    };
1480
1481    unsigned NumGPRs = CCInfo.getFirstUnallocated
1482      (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1483
1484    unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1485    unsigned VARegSize = (4 - NumGPRs) * 4;
1486    unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1487    unsigned ArgOffset = 0;
1488    if (VARegSaveSize) {
1489      // If this function is vararg, store any remaining integer argument regs
1490      // to their spots on the stack so that they may be loaded by deferencing
1491      // the result of va_next.
1492      AFI->setVarArgsRegSaveSize(VARegSaveSize);
1493      ArgOffset = CCInfo.getNextStackOffset();
1494      VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1495                                                 VARegSaveSize - VARegSize);
1496      SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1497
1498      SmallVector<SDValue, 4> MemOps;
1499      for (; NumGPRs < 4; ++NumGPRs) {
1500        TargetRegisterClass *RC;
1501        if (AFI->isThumbFunction())
1502          RC = ARM::tGPRRegisterClass;
1503        else
1504          RC = ARM::GPRRegisterClass;
1505
1506        unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1507        SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1508        SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1509        MemOps.push_back(Store);
1510        FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1511                          DAG.getConstant(4, getPointerTy()));
1512      }
1513      if (!MemOps.empty())
1514        Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1515                           &MemOps[0], MemOps.size());
1516    } else
1517      // This will point to the next argument passed via stack.
1518      VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1519  }
1520
1521  ArgValues.push_back(Root);
1522
1523  // Return the new list of results.
1524  return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1525                     &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1526}
1527
1528/// isFloatingPointZero - Return true if this is +0.0.
1529static bool isFloatingPointZero(SDValue Op) {
1530  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1531    return CFP->getValueAPF().isPosZero();
1532  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1533    // Maybe this has already been legalized into the constant pool?
1534    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1535      SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1536      if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1537        if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1538          return CFP->getValueAPF().isPosZero();
1539    }
1540  }
1541  return false;
1542}
1543
1544static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1545  return ( isThumb && (C & ~255U) == 0) ||
1546         (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1547}
1548
1549/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1550/// the given operands.
1551static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1552                         SDValue &ARMCC, SelectionDAG &DAG, bool isThumb,
1553                         DebugLoc dl) {
1554  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1555    unsigned C = RHSC->getZExtValue();
1556    if (!isLegalCmpImmediate(C, isThumb)) {
1557      // Constant does not fit, try adjusting it by one?
1558      switch (CC) {
1559      default: break;
1560      case ISD::SETLT:
1561      case ISD::SETGE:
1562        if (isLegalCmpImmediate(C-1, isThumb)) {
1563          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1564          RHS = DAG.getConstant(C-1, MVT::i32);
1565        }
1566        break;
1567      case ISD::SETULT:
1568      case ISD::SETUGE:
1569        if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1570          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1571          RHS = DAG.getConstant(C-1, MVT::i32);
1572        }
1573        break;
1574      case ISD::SETLE:
1575      case ISD::SETGT:
1576        if (isLegalCmpImmediate(C+1, isThumb)) {
1577          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1578          RHS = DAG.getConstant(C+1, MVT::i32);
1579        }
1580        break;
1581      case ISD::SETULE:
1582      case ISD::SETUGT:
1583        if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1584          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1585          RHS = DAG.getConstant(C+1, MVT::i32);
1586        }
1587        break;
1588      }
1589    }
1590  }
1591
1592  ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1593  ARMISD::NodeType CompareType;
1594  switch (CondCode) {
1595  default:
1596    CompareType = ARMISD::CMP;
1597    break;
1598  case ARMCC::EQ:
1599  case ARMCC::NE:
1600    // Uses only Z Flag
1601    CompareType = ARMISD::CMPZ;
1602    break;
1603  }
1604  ARMCC = DAG.getConstant(CondCode, MVT::i32);
1605  return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1606}
1607
1608/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1609static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1610                         DebugLoc dl) {
1611  SDValue Cmp;
1612  if (!isFloatingPointZero(RHS))
1613    Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1614  else
1615    Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1616  return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1617}
1618
1619static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1620                              const ARMSubtarget *ST) {
1621  MVT VT = Op.getValueType();
1622  SDValue LHS = Op.getOperand(0);
1623  SDValue RHS = Op.getOperand(1);
1624  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1625  SDValue TrueVal = Op.getOperand(2);
1626  SDValue FalseVal = Op.getOperand(3);
1627  DebugLoc dl = Op.getDebugLoc();
1628
1629  if (LHS.getValueType() == MVT::i32) {
1630    SDValue ARMCC;
1631    SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1632    SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1633    return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1634  }
1635
1636  ARMCC::CondCodes CondCode, CondCode2;
1637  if (FPCCToARMCC(CC, CondCode, CondCode2))
1638    std::swap(TrueVal, FalseVal);
1639
1640  SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1641  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1642  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1643  SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1644                                 ARMCC, CCR, Cmp);
1645  if (CondCode2 != ARMCC::AL) {
1646    SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1647    // FIXME: Needs another CMP because flag can have but one use.
1648    SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1649    Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1650                         Result, TrueVal, ARMCC2, CCR, Cmp2);
1651  }
1652  return Result;
1653}
1654
1655static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1656                          const ARMSubtarget *ST) {
1657  SDValue  Chain = Op.getOperand(0);
1658  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1659  SDValue    LHS = Op.getOperand(2);
1660  SDValue    RHS = Op.getOperand(3);
1661  SDValue   Dest = Op.getOperand(4);
1662  DebugLoc dl = Op.getDebugLoc();
1663
1664  if (LHS.getValueType() == MVT::i32) {
1665    SDValue ARMCC;
1666    SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1667    SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1668    return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1669                       Chain, Dest, ARMCC, CCR,Cmp);
1670  }
1671
1672  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1673  ARMCC::CondCodes CondCode, CondCode2;
1674  if (FPCCToARMCC(CC, CondCode, CondCode2))
1675    // Swap the LHS/RHS of the comparison if needed.
1676    std::swap(LHS, RHS);
1677
1678  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1679  SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1680  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1681  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1682  SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1683  SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1684  if (CondCode2 != ARMCC::AL) {
1685    ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1686    SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1687    Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1688  }
1689  return Res;
1690}
1691
1692SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1693  SDValue Chain = Op.getOperand(0);
1694  SDValue Table = Op.getOperand(1);
1695  SDValue Index = Op.getOperand(2);
1696  DebugLoc dl = Op.getDebugLoc();
1697
1698  MVT PTy = getPointerTy();
1699  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1700  ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1701  SDValue UId =  DAG.getConstant(AFI->createJumpTableUId(), PTy);
1702  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1703  Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1704  Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1705  SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1706  bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1707  Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl,
1708                     Chain, Addr, NULL, 0);
1709  Chain = Addr.getValue(1);
1710  if (isPIC)
1711    Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1712  return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1713}
1714
1715static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1716  DebugLoc dl = Op.getDebugLoc();
1717  unsigned Opc =
1718    Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1719  Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1720  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1721}
1722
1723static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1724  MVT VT = Op.getValueType();
1725  DebugLoc dl = Op.getDebugLoc();
1726  unsigned Opc =
1727    Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1728
1729  Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1730  return DAG.getNode(Opc, dl, VT, Op);
1731}
1732
1733static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1734  // Implement fcopysign with a fabs and a conditional fneg.
1735  SDValue Tmp0 = Op.getOperand(0);
1736  SDValue Tmp1 = Op.getOperand(1);
1737  DebugLoc dl = Op.getDebugLoc();
1738  MVT VT = Op.getValueType();
1739  MVT SrcVT = Tmp1.getValueType();
1740  SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1741  SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1742  SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1743  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1744  return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1745}
1746
1747SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1748  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1749  MFI->setFrameAddressIsTaken(true);
1750  MVT VT = Op.getValueType();
1751  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
1752  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1753  unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1754    ? ARM::R7 : ARM::R11;
1755  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1756  while (Depth--)
1757    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1758  return FrameAddr;
1759}
1760
1761SDValue
1762ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1763                                           SDValue Chain,
1764                                           SDValue Dst, SDValue Src,
1765                                           SDValue Size, unsigned Align,
1766                                           bool AlwaysInline,
1767                                         const Value *DstSV, uint64_t DstSVOff,
1768                                         const Value *SrcSV, uint64_t SrcSVOff){
1769  // Do repeated 4-byte loads and stores. To be improved.
1770  // This requires 4-byte alignment.
1771  if ((Align & 3) != 0)
1772    return SDValue();
1773  // This requires the copy size to be a constant, preferrably
1774  // within a subtarget-specific limit.
1775  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1776  if (!ConstantSize)
1777    return SDValue();
1778  uint64_t SizeVal = ConstantSize->getZExtValue();
1779  if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1780    return SDValue();
1781
1782  unsigned BytesLeft = SizeVal & 3;
1783  unsigned NumMemOps = SizeVal >> 2;
1784  unsigned EmittedNumMemOps = 0;
1785  MVT VT = MVT::i32;
1786  unsigned VTSize = 4;
1787  unsigned i = 0;
1788  const unsigned MAX_LOADS_IN_LDM = 6;
1789  SDValue TFOps[MAX_LOADS_IN_LDM];
1790  SDValue Loads[MAX_LOADS_IN_LDM];
1791  uint64_t SrcOff = 0, DstOff = 0;
1792
1793  // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1794  // same number of stores.  The loads and stores will get combined into
1795  // ldm/stm later on.
1796  while (EmittedNumMemOps < NumMemOps) {
1797    for (i = 0;
1798         i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1799      Loads[i] = DAG.getLoad(VT, dl, Chain,
1800                             DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1801                                         DAG.getConstant(SrcOff, MVT::i32)),
1802                             SrcSV, SrcSVOff + SrcOff);
1803      TFOps[i] = Loads[i].getValue(1);
1804      SrcOff += VTSize;
1805    }
1806    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1807
1808    for (i = 0;
1809         i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1810      TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1811                           DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1812                                       DAG.getConstant(DstOff, MVT::i32)),
1813                           DstSV, DstSVOff + DstOff);
1814      DstOff += VTSize;
1815    }
1816    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1817
1818    EmittedNumMemOps += i;
1819  }
1820
1821  if (BytesLeft == 0)
1822    return Chain;
1823
1824  // Issue loads / stores for the trailing (1 - 3) bytes.
1825  unsigned BytesLeftSave = BytesLeft;
1826  i = 0;
1827  while (BytesLeft) {
1828    if (BytesLeft >= 2) {
1829      VT = MVT::i16;
1830      VTSize = 2;
1831    } else {
1832      VT = MVT::i8;
1833      VTSize = 1;
1834    }
1835
1836    Loads[i] = DAG.getLoad(VT, dl, Chain,
1837                           DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1838                                       DAG.getConstant(SrcOff, MVT::i32)),
1839                           SrcSV, SrcSVOff + SrcOff);
1840    TFOps[i] = Loads[i].getValue(1);
1841    ++i;
1842    SrcOff += VTSize;
1843    BytesLeft -= VTSize;
1844  }
1845  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1846
1847  i = 0;
1848  BytesLeft = BytesLeftSave;
1849  while (BytesLeft) {
1850    if (BytesLeft >= 2) {
1851      VT = MVT::i16;
1852      VTSize = 2;
1853    } else {
1854      VT = MVT::i8;
1855      VTSize = 1;
1856    }
1857
1858    TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1859                            DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1860                                        DAG.getConstant(DstOff, MVT::i32)),
1861                            DstSV, DstSVOff + DstOff);
1862    ++i;
1863    DstOff += VTSize;
1864    BytesLeft -= VTSize;
1865  }
1866  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1867}
1868
1869static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1870  SDValue Op = N->getOperand(0);
1871  DebugLoc dl = N->getDebugLoc();
1872  if (N->getValueType(0) == MVT::f64) {
1873    // Turn i64->f64 into FMDRR.
1874    SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1875                             DAG.getConstant(0, MVT::i32));
1876    SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1877                             DAG.getConstant(1, MVT::i32));
1878    return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
1879  }
1880
1881  // Turn f64->i64 into FMRRD.
1882  SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
1883                            DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
1884
1885  // Merge the pieces into a single i64 value.
1886  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
1887}
1888
1889/// getZeroVector - Returns a vector of specified type with all zero elements.
1890///
1891static SDValue getZeroVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
1892  assert(VT.isVector() && "Expected a vector type");
1893
1894  // Zero vectors are used to represent vector negation and in those cases
1895  // will be implemented with the NEON VNEG instruction.  However, VNEG does
1896  // not support i64 elements, so sometimes the zero vectors will need to be
1897  // explicitly constructed.  For those cases, and potentially other uses in
1898  // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
1899  // to their dest type.  This ensures they get CSE'd.
1900  SDValue Vec;
1901  SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
1902  if (VT.getSizeInBits() == 64)
1903    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
1904  else
1905    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
1906
1907  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
1908}
1909
1910/// getOnesVector - Returns a vector of specified type with all bits set.
1911///
1912static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
1913  assert(VT.isVector() && "Expected a vector type");
1914
1915  // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
1916  // type.  This ensures they get CSE'd.
1917  SDValue Vec;
1918  SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
1919  if (VT.getSizeInBits() == 64)
1920    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
1921  else
1922    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
1923
1924  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
1925}
1926
1927static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
1928                          const ARMSubtarget *ST) {
1929  MVT VT = N->getValueType(0);
1930  DebugLoc dl = N->getDebugLoc();
1931
1932  // Lower vector shifts on NEON to use VSHL.
1933  if (VT.isVector()) {
1934    assert(ST->hasNEON() && "unexpected vector shift");
1935
1936    // Left shifts translate directly to the vshiftu intrinsic.
1937    if (N->getOpcode() == ISD::SHL)
1938      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
1939                         DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
1940                         N->getOperand(0), N->getOperand(1));
1941
1942    assert((N->getOpcode() == ISD::SRA ||
1943            N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
1944
1945    // NEON uses the same intrinsics for both left and right shifts.  For
1946    // right shifts, the shift amounts are negative, so negate the vector of
1947    // shift amounts.
1948    MVT ShiftVT = N->getOperand(1).getValueType();
1949    SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
1950                                       getZeroVector(ShiftVT, DAG, dl),
1951                                       N->getOperand(1));
1952    Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
1953                               Intrinsic::arm_neon_vshifts :
1954                               Intrinsic::arm_neon_vshiftu);
1955    return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
1956                       DAG.getConstant(vshiftInt, MVT::i32),
1957                       N->getOperand(0), NegatedCount);
1958  }
1959
1960  assert(VT == MVT::i64 &&
1961         (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1962         "Unknown shift to lower!");
1963
1964  // We only lower SRA, SRL of 1 here, all others use generic lowering.
1965  if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1966      cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
1967    return SDValue();
1968
1969  // If we are in thumb mode, we don't have RRX.
1970  if (ST->isThumb()) return SDValue();
1971
1972  // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
1973  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1974                             DAG.getConstant(0, MVT::i32));
1975  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1976                             DAG.getConstant(1, MVT::i32));
1977
1978  // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1979  // captures the result into a carry flag.
1980  unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1981  Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1982
1983  // The low part is an ARMISD::RRX operand, which shifts the carry in.
1984  Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
1985
1986  // Merge the pieces into a single i64 value.
1987 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1988}
1989
1990static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
1991  SDValue TmpOp0, TmpOp1;
1992  bool Invert = false;
1993  bool Swap = false;
1994  unsigned Opc = 0;
1995
1996  SDValue Op0 = Op.getOperand(0);
1997  SDValue Op1 = Op.getOperand(1);
1998  SDValue CC = Op.getOperand(2);
1999  MVT VT = Op.getValueType();
2000  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2001  DebugLoc dl = Op.getDebugLoc();
2002
2003  if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2004    switch (SetCCOpcode) {
2005    default: assert(0 && "Illegal FP comparison"); break;
2006    case ISD::SETUNE:
2007    case ISD::SETNE:  Invert = true; // Fallthrough
2008    case ISD::SETOEQ:
2009    case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
2010    case ISD::SETOLT:
2011    case ISD::SETLT: Swap = true; // Fallthrough
2012    case ISD::SETOGT:
2013    case ISD::SETGT:  Opc = ARMISD::VCGT; break;
2014    case ISD::SETOLE:
2015    case ISD::SETLE:  Swap = true; // Fallthrough
2016    case ISD::SETOGE:
2017    case ISD::SETGE: Opc = ARMISD::VCGE; break;
2018    case ISD::SETUGE: Swap = true; // Fallthrough
2019    case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2020    case ISD::SETUGT: Swap = true; // Fallthrough
2021    case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2022    case ISD::SETUEQ: Invert = true; // Fallthrough
2023    case ISD::SETONE:
2024      // Expand this to (OLT | OGT).
2025      TmpOp0 = Op0;
2026      TmpOp1 = Op1;
2027      Opc = ISD::OR;
2028      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2029      Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2030      break;
2031    case ISD::SETUO: Invert = true; // Fallthrough
2032    case ISD::SETO:
2033      // Expand this to (OLT | OGE).
2034      TmpOp0 = Op0;
2035      TmpOp1 = Op1;
2036      Opc = ISD::OR;
2037      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2038      Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2039      break;
2040    }
2041  } else {
2042    // Integer comparisons.
2043    switch (SetCCOpcode) {
2044    default: assert(0 && "Illegal integer comparison"); break;
2045    case ISD::SETNE:  Invert = true;
2046    case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
2047    case ISD::SETLT:  Swap = true;
2048    case ISD::SETGT:  Opc = ARMISD::VCGT; break;
2049    case ISD::SETLE:  Swap = true;
2050    case ISD::SETGE:  Opc = ARMISD::VCGE; break;
2051    case ISD::SETULT: Swap = true;
2052    case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2053    case ISD::SETULE: Swap = true;
2054    case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2055    }
2056
2057    // Detect VTST (Vector Test Bits) = vicmp ne (and (op0, op1), zero).
2058    if (Opc == ARMISD::VCEQ) {
2059
2060      SDValue AndOp;
2061      if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2062        AndOp = Op0;
2063      else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2064        AndOp = Op1;
2065
2066      // Ignore bitconvert.
2067      if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2068        AndOp = AndOp.getOperand(0);
2069
2070      if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2071        Opc = ARMISD::VTST;
2072        Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2073        Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2074        Invert = !Invert;
2075      }
2076    }
2077  }
2078
2079  if (Swap)
2080    std::swap(Op0, Op1);
2081
2082  SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2083
2084  if (Invert)
2085    Result = DAG.getNOT(dl, Result, VT);
2086
2087  return Result;
2088}
2089
2090/// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2091/// VMOV instruction, and if so, return the constant being splatted.
2092static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2093                           unsigned SplatBitSize, SelectionDAG &DAG) {
2094  switch (SplatBitSize) {
2095  case 8:
2096    // Any 1-byte value is OK.
2097    assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2098    return DAG.getTargetConstant(SplatBits, MVT::i8);
2099
2100  case 16:
2101    // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2102    if ((SplatBits & ~0xff) == 0 ||
2103        (SplatBits & ~0xff00) == 0)
2104      return DAG.getTargetConstant(SplatBits, MVT::i16);
2105    break;
2106
2107  case 32:
2108    // NEON's 32-bit VMOV supports splat values where:
2109    // * only one byte is nonzero, or
2110    // * the least significant byte is 0xff and the second byte is nonzero, or
2111    // * the least significant 2 bytes are 0xff and the third is nonzero.
2112    if ((SplatBits & ~0xff) == 0 ||
2113        (SplatBits & ~0xff00) == 0 ||
2114        (SplatBits & ~0xff0000) == 0 ||
2115        (SplatBits & ~0xff000000) == 0)
2116      return DAG.getTargetConstant(SplatBits, MVT::i32);
2117
2118    if ((SplatBits & ~0xffff) == 0 &&
2119        ((SplatBits | SplatUndef) & 0xff) == 0xff)
2120      return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2121
2122    if ((SplatBits & ~0xffffff) == 0 &&
2123        ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2124      return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2125
2126    // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2127    // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2128    // VMOV.I32.  A (very) minor optimization would be to replicate the value
2129    // and fall through here to test for a valid 64-bit splat.  But, then the
2130    // caller would also need to check and handle the change in size.
2131    break;
2132
2133  case 64: {
2134    // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2135    uint64_t BitMask = 0xff;
2136    uint64_t Val = 0;
2137    for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2138      if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2139        Val |= BitMask;
2140      else if ((SplatBits & BitMask) != 0)
2141        return SDValue();
2142      BitMask <<= 8;
2143    }
2144    return DAG.getTargetConstant(Val, MVT::i64);
2145  }
2146
2147  default:
2148    assert(0 && "unexpected size for isVMOVSplat");
2149    break;
2150  }
2151
2152  return SDValue();
2153}
2154
2155/// getVMOVImm - If this is a build_vector of constants which can be
2156/// formed by using a VMOV instruction of the specified element size,
2157/// return the constant being splatted.  The ByteSize field indicates the
2158/// number of bytes of each element [1248].
2159SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2160  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2161  APInt SplatBits, SplatUndef;
2162  unsigned SplatBitSize;
2163  bool HasAnyUndefs;
2164  if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2165                                      HasAnyUndefs, ByteSize * 8))
2166    return SDValue();
2167
2168  if (SplatBitSize > ByteSize * 8)
2169    return SDValue();
2170
2171  return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2172                     SplatBitSize, DAG);
2173}
2174
2175static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2176  // Canonicalize all-zeros and all-ones vectors.
2177  ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode());
2178  if (ConstVal->isNullValue())
2179    return getZeroVector(VT, DAG, dl);
2180  if (ConstVal->isAllOnesValue())
2181    return getOnesVector(VT, DAG, dl);
2182
2183  MVT CanonicalVT;
2184  if (VT.is64BitVector()) {
2185    switch (Val.getValueType().getSizeInBits()) {
2186    case 8:  CanonicalVT = MVT::v8i8; break;
2187    case 16: CanonicalVT = MVT::v4i16; break;
2188    case 32: CanonicalVT = MVT::v2i32; break;
2189    case 64: CanonicalVT = MVT::v1i64; break;
2190    default: assert(0 && "unexpected splat element type"); break;
2191    }
2192  } else {
2193    assert(VT.is128BitVector() && "unknown splat vector size");
2194    switch (Val.getValueType().getSizeInBits()) {
2195    case 8:  CanonicalVT = MVT::v16i8; break;
2196    case 16: CanonicalVT = MVT::v8i16; break;
2197    case 32: CanonicalVT = MVT::v4i32; break;
2198    case 64: CanonicalVT = MVT::v2i64; break;
2199    default: assert(0 && "unexpected splat element type"); break;
2200    }
2201  }
2202
2203  // Build a canonical splat for this value.
2204  SmallVector<SDValue, 8> Ops;
2205  Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2206  SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2207                            Ops.size());
2208  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2209}
2210
2211// If this is a case we can't handle, return null and let the default
2212// expansion code take care of it.
2213static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2214  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2215  assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
2216  DebugLoc dl = Op.getDebugLoc();
2217
2218  APInt SplatBits, SplatUndef;
2219  unsigned SplatBitSize;
2220  bool HasAnyUndefs;
2221  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2222    SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2223                              SplatUndef.getZExtValue(), SplatBitSize, DAG);
2224    if (Val.getNode())
2225      return BuildSplat(Val, Op.getValueType(), DAG, dl);
2226  }
2227
2228  return SDValue();
2229}
2230
2231static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2232  return Op;
2233}
2234
2235static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
2236  return Op;
2237}
2238
2239static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2240  MVT VT = Op.getValueType();
2241  DebugLoc dl = Op.getDebugLoc();
2242  assert((VT == MVT::i8 || VT == MVT::i16) &&
2243         "unexpected type for custom-lowering vector extract");
2244  SDValue Vec = Op.getOperand(0);
2245  SDValue Lane = Op.getOperand(1);
2246  Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2247  Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2248  return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2249}
2250
2251static SDValue LowerCONCAT_VECTORS(SDValue Op) {
2252  if (Op.getValueType().is128BitVector() && Op.getNumOperands() == 2)
2253    return Op;
2254  return SDValue();
2255}
2256
2257SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2258  switch (Op.getOpcode()) {
2259  default: assert(0 && "Don't know how to custom lower this!"); abort();
2260  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
2261  case ISD::GlobalAddress:
2262    return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2263      LowerGlobalAddressELF(Op, DAG);
2264  case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
2265  case ISD::CALL:          return LowerCALL(Op, DAG);
2266  case ISD::RET:           return LowerRET(Op, DAG);
2267  case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG, Subtarget);
2268  case ISD::BR_CC:         return LowerBR_CC(Op, DAG, Subtarget);
2269  case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
2270  case ISD::VASTART:       return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2271  case ISD::SINT_TO_FP:
2272  case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
2273  case ISD::FP_TO_SINT:
2274  case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
2275  case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
2276  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
2277  case ISD::RETURNADDR:    break;
2278  case ISD::FRAMEADDR:     return LowerFRAMEADDR(Op, DAG);
2279  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2280  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2281  case ISD::BIT_CONVERT:   return ExpandBIT_CONVERT(Op.getNode(), DAG);
2282  case ISD::SHL:
2283  case ISD::SRL:
2284  case ISD::SRA:           return LowerShift(Op.getNode(), DAG, Subtarget);
2285  case ISD::VSETCC:        return LowerVSETCC(Op, DAG);
2286  case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG);
2287  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2288  case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2289  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2290  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op);
2291  }
2292  return SDValue();
2293}
2294
2295/// ReplaceNodeResults - Replace the results of node with an illegal result
2296/// type with new values built out of custom code.
2297void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2298                                           SmallVectorImpl<SDValue>&Results,
2299                                           SelectionDAG &DAG) {
2300  switch (N->getOpcode()) {
2301  default:
2302    assert(0 && "Don't know how to custom expand this!");
2303    return;
2304  case ISD::BIT_CONVERT:
2305    Results.push_back(ExpandBIT_CONVERT(N, DAG));
2306    return;
2307  case ISD::SRL:
2308  case ISD::SRA: {
2309    SDValue Res = LowerShift(N, DAG, Subtarget);
2310    if (Res.getNode())
2311      Results.push_back(Res);
2312    return;
2313  }
2314  }
2315}
2316
2317//===----------------------------------------------------------------------===//
2318//                           ARM Scheduler Hooks
2319//===----------------------------------------------------------------------===//
2320
2321MachineBasicBlock *
2322ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2323                                               MachineBasicBlock *BB) const {
2324  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2325  DebugLoc dl = MI->getDebugLoc();
2326  switch (MI->getOpcode()) {
2327  default: assert(false && "Unexpected instr type to insert");
2328  case ARM::tMOVCCr: {
2329    // To "insert" a SELECT_CC instruction, we actually have to insert the
2330    // diamond control-flow pattern.  The incoming instruction knows the
2331    // destination vreg to set, the condition code register to branch on, the
2332    // true/false values to select between, and a branch opcode to use.
2333    const BasicBlock *LLVM_BB = BB->getBasicBlock();
2334    MachineFunction::iterator It = BB;
2335    ++It;
2336
2337    //  thisMBB:
2338    //  ...
2339    //   TrueVal = ...
2340    //   cmpTY ccX, r1, r2
2341    //   bCC copy1MBB
2342    //   fallthrough --> copy0MBB
2343    MachineBasicBlock *thisMBB  = BB;
2344    MachineFunction *F = BB->getParent();
2345    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2346    MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
2347    BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2348      .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2349    F->insert(It, copy0MBB);
2350    F->insert(It, sinkMBB);
2351    // Update machine-CFG edges by first adding all successors of the current
2352    // block to the new block which will contain the Phi node for the select.
2353    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2354        e = BB->succ_end(); i != e; ++i)
2355      sinkMBB->addSuccessor(*i);
2356    // Next, remove all successors of the current block, and add the true
2357    // and fallthrough blocks as its successors.
2358    while(!BB->succ_empty())
2359      BB->removeSuccessor(BB->succ_begin());
2360    BB->addSuccessor(copy0MBB);
2361    BB->addSuccessor(sinkMBB);
2362
2363    //  copy0MBB:
2364    //   %FalseValue = ...
2365    //   # fallthrough to sinkMBB
2366    BB = copy0MBB;
2367
2368    // Update machine-CFG edges
2369    BB->addSuccessor(sinkMBB);
2370
2371    //  sinkMBB:
2372    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2373    //  ...
2374    BB = sinkMBB;
2375    BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2376      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2377      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2378
2379    F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
2380    return BB;
2381  }
2382  }
2383}
2384
2385//===----------------------------------------------------------------------===//
2386//                           ARM Optimization Hooks
2387//===----------------------------------------------------------------------===//
2388
2389static
2390SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2391                            TargetLowering::DAGCombinerInfo &DCI) {
2392  SelectionDAG &DAG = DCI.DAG;
2393  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2394  MVT VT = N->getValueType(0);
2395  unsigned Opc = N->getOpcode();
2396  bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2397  SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2398  SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2399  ISD::CondCode CC = ISD::SETCC_INVALID;
2400
2401  if (isSlctCC) {
2402    CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2403  } else {
2404    SDValue CCOp = Slct.getOperand(0);
2405    if (CCOp.getOpcode() == ISD::SETCC)
2406      CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2407  }
2408
2409  bool DoXform = false;
2410  bool InvCC = false;
2411  assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2412          "Bad input!");
2413
2414  if (LHS.getOpcode() == ISD::Constant &&
2415      cast<ConstantSDNode>(LHS)->isNullValue()) {
2416    DoXform = true;
2417  } else if (CC != ISD::SETCC_INVALID &&
2418             RHS.getOpcode() == ISD::Constant &&
2419             cast<ConstantSDNode>(RHS)->isNullValue()) {
2420    std::swap(LHS, RHS);
2421    SDValue Op0 = Slct.getOperand(0);
2422    MVT OpVT = isSlctCC ? Op0.getValueType() :
2423                          Op0.getOperand(0).getValueType();
2424    bool isInt = OpVT.isInteger();
2425    CC = ISD::getSetCCInverse(CC, isInt);
2426
2427    if (!TLI.isCondCodeLegal(CC, OpVT))
2428      return SDValue();         // Inverse operator isn't legal.
2429
2430    DoXform = true;
2431    InvCC = true;
2432  }
2433
2434  if (DoXform) {
2435    SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2436    if (isSlctCC)
2437      return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2438                             Slct.getOperand(0), Slct.getOperand(1), CC);
2439    SDValue CCOp = Slct.getOperand(0);
2440    if (InvCC)
2441      CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2442                          CCOp.getOperand(0), CCOp.getOperand(1), CC);
2443    return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2444                       CCOp, OtherOp, Result);
2445  }
2446  return SDValue();
2447}
2448
2449/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2450static SDValue PerformADDCombine(SDNode *N,
2451                                 TargetLowering::DAGCombinerInfo &DCI) {
2452  // added by evan in r37685 with no testcase.
2453  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2454
2455  // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
2456  if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
2457    SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
2458    if (Result.getNode()) return Result;
2459  }
2460  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2461    SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2462    if (Result.getNode()) return Result;
2463  }
2464
2465  return SDValue();
2466}
2467
2468/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
2469static SDValue PerformSUBCombine(SDNode *N,
2470                                 TargetLowering::DAGCombinerInfo &DCI) {
2471  // added by evan in r37685 with no testcase.
2472  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2473
2474  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
2475  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2476    SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2477    if (Result.getNode()) return Result;
2478  }
2479
2480  return SDValue();
2481}
2482
2483
2484/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
2485static SDValue PerformFMRRDCombine(SDNode *N,
2486                                   TargetLowering::DAGCombinerInfo &DCI) {
2487  // fmrrd(fmdrr x, y) -> x,y
2488  SDValue InDouble = N->getOperand(0);
2489  if (InDouble.getOpcode() == ARMISD::FMDRR)
2490    return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
2491  return SDValue();
2492}
2493
2494/// getVShiftImm - Check if this is a valid build_vector for the immediate
2495/// operand of a vector shift operation, where all the elements of the
2496/// build_vector must have the same constant integer value.
2497static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
2498  // Ignore bit_converts.
2499  while (Op.getOpcode() == ISD::BIT_CONVERT)
2500    Op = Op.getOperand(0);
2501  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2502  APInt SplatBits, SplatUndef;
2503  unsigned SplatBitSize;
2504  bool HasAnyUndefs;
2505  if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2506                                      HasAnyUndefs, ElementBits) ||
2507      SplatBitSize > ElementBits)
2508    return false;
2509  Cnt = SplatBits.getSExtValue();
2510  return true;
2511}
2512
2513/// isVShiftLImm - Check if this is a valid build_vector for the immediate
2514/// operand of a vector shift left operation.  That value must be in the range:
2515///   0 <= Value < ElementBits for a left shift; or
2516///   0 <= Value <= ElementBits for a long left shift.
2517static bool isVShiftLImm(SDValue Op, MVT VT, bool isLong, int64_t &Cnt) {
2518  assert(VT.isVector() && "vector shift count is not a vector type");
2519  unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2520  if (! getVShiftImm(Op, ElementBits, Cnt))
2521    return false;
2522  return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
2523}
2524
2525/// isVShiftRImm - Check if this is a valid build_vector for the immediate
2526/// operand of a vector shift right operation.  For a shift opcode, the value
2527/// is positive, but for an intrinsic the value count must be negative. The
2528/// absolute value must be in the range:
2529///   1 <= |Value| <= ElementBits for a right shift; or
2530///   1 <= |Value| <= ElementBits/2 for a narrow right shift.
2531static bool isVShiftRImm(SDValue Op, MVT VT, bool isNarrow, bool isIntrinsic,
2532                         int64_t &Cnt) {
2533  assert(VT.isVector() && "vector shift count is not a vector type");
2534  unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2535  if (! getVShiftImm(Op, ElementBits, Cnt))
2536    return false;
2537  if (isIntrinsic)
2538    Cnt = -Cnt;
2539  return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
2540}
2541
2542/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
2543static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
2544  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2545  switch (IntNo) {
2546  default:
2547    // Don't do anything for most intrinsics.
2548    break;
2549
2550  // Vector shifts: check for immediate versions and lower them.
2551  // Note: This is done during DAG combining instead of DAG legalizing because
2552  // the build_vectors for 64-bit vector element shift counts are generally
2553  // not legal, and it is hard to see their values after they get legalized to
2554  // loads from a constant pool.
2555  case Intrinsic::arm_neon_vshifts:
2556  case Intrinsic::arm_neon_vshiftu:
2557  case Intrinsic::arm_neon_vshiftls:
2558  case Intrinsic::arm_neon_vshiftlu:
2559  case Intrinsic::arm_neon_vshiftn:
2560  case Intrinsic::arm_neon_vrshifts:
2561  case Intrinsic::arm_neon_vrshiftu:
2562  case Intrinsic::arm_neon_vrshiftn:
2563  case Intrinsic::arm_neon_vqshifts:
2564  case Intrinsic::arm_neon_vqshiftu:
2565  case Intrinsic::arm_neon_vqshiftsu:
2566  case Intrinsic::arm_neon_vqshiftns:
2567  case Intrinsic::arm_neon_vqshiftnu:
2568  case Intrinsic::arm_neon_vqshiftnsu:
2569  case Intrinsic::arm_neon_vqrshiftns:
2570  case Intrinsic::arm_neon_vqrshiftnu:
2571  case Intrinsic::arm_neon_vqrshiftnsu: {
2572    MVT VT = N->getOperand(1).getValueType();
2573    int64_t Cnt;
2574    unsigned VShiftOpc = 0;
2575
2576    switch (IntNo) {
2577    case Intrinsic::arm_neon_vshifts:
2578    case Intrinsic::arm_neon_vshiftu:
2579      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
2580        VShiftOpc = ARMISD::VSHL;
2581        break;
2582      }
2583      if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
2584        VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
2585                     ARMISD::VSHRs : ARMISD::VSHRu);
2586        break;
2587      }
2588      return SDValue();
2589
2590    case Intrinsic::arm_neon_vshiftls:
2591    case Intrinsic::arm_neon_vshiftlu:
2592      if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
2593        break;
2594      assert(0 && "invalid shift count for vshll intrinsic");
2595      abort();
2596
2597    case Intrinsic::arm_neon_vrshifts:
2598    case Intrinsic::arm_neon_vrshiftu:
2599      if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
2600        break;
2601      return SDValue();
2602
2603    case Intrinsic::arm_neon_vqshifts:
2604    case Intrinsic::arm_neon_vqshiftu:
2605      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2606        break;
2607      return SDValue();
2608
2609    case Intrinsic::arm_neon_vqshiftsu:
2610      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2611        break;
2612      assert(0 && "invalid shift count for vqshlu intrinsic");
2613      abort();
2614
2615    case Intrinsic::arm_neon_vshiftn:
2616    case Intrinsic::arm_neon_vrshiftn:
2617    case Intrinsic::arm_neon_vqshiftns:
2618    case Intrinsic::arm_neon_vqshiftnu:
2619    case Intrinsic::arm_neon_vqshiftnsu:
2620    case Intrinsic::arm_neon_vqrshiftns:
2621    case Intrinsic::arm_neon_vqrshiftnu:
2622    case Intrinsic::arm_neon_vqrshiftnsu:
2623      // Narrowing shifts require an immediate right shift.
2624      if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
2625        break;
2626      assert(0 && "invalid shift count for narrowing vector shift intrinsic");
2627      abort();
2628
2629    default:
2630      assert(0 && "unhandled vector shift");
2631    }
2632
2633    switch (IntNo) {
2634    case Intrinsic::arm_neon_vshifts:
2635    case Intrinsic::arm_neon_vshiftu:
2636      // Opcode already set above.
2637      break;
2638    case Intrinsic::arm_neon_vshiftls:
2639    case Intrinsic::arm_neon_vshiftlu:
2640      if (Cnt == VT.getVectorElementType().getSizeInBits())
2641        VShiftOpc = ARMISD::VSHLLi;
2642      else
2643        VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
2644                     ARMISD::VSHLLs : ARMISD::VSHLLu);
2645      break;
2646    case Intrinsic::arm_neon_vshiftn:
2647      VShiftOpc = ARMISD::VSHRN; break;
2648    case Intrinsic::arm_neon_vrshifts:
2649      VShiftOpc = ARMISD::VRSHRs; break;
2650    case Intrinsic::arm_neon_vrshiftu:
2651      VShiftOpc = ARMISD::VRSHRu; break;
2652    case Intrinsic::arm_neon_vrshiftn:
2653      VShiftOpc = ARMISD::VRSHRN; break;
2654    case Intrinsic::arm_neon_vqshifts:
2655      VShiftOpc = ARMISD::VQSHLs; break;
2656    case Intrinsic::arm_neon_vqshiftu:
2657      VShiftOpc = ARMISD::VQSHLu; break;
2658    case Intrinsic::arm_neon_vqshiftsu:
2659      VShiftOpc = ARMISD::VQSHLsu; break;
2660    case Intrinsic::arm_neon_vqshiftns:
2661      VShiftOpc = ARMISD::VQSHRNs; break;
2662    case Intrinsic::arm_neon_vqshiftnu:
2663      VShiftOpc = ARMISD::VQSHRNu; break;
2664    case Intrinsic::arm_neon_vqshiftnsu:
2665      VShiftOpc = ARMISD::VQSHRNsu; break;
2666    case Intrinsic::arm_neon_vqrshiftns:
2667      VShiftOpc = ARMISD::VQRSHRNs; break;
2668    case Intrinsic::arm_neon_vqrshiftnu:
2669      VShiftOpc = ARMISD::VQRSHRNu; break;
2670    case Intrinsic::arm_neon_vqrshiftnsu:
2671      VShiftOpc = ARMISD::VQRSHRNsu; break;
2672    }
2673
2674    return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2675                       N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
2676  }
2677
2678  case Intrinsic::arm_neon_vshiftins: {
2679    MVT VT = N->getOperand(1).getValueType();
2680    int64_t Cnt;
2681    unsigned VShiftOpc = 0;
2682
2683    if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
2684      VShiftOpc = ARMISD::VSLI;
2685    else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
2686      VShiftOpc = ARMISD::VSRI;
2687    else {
2688      assert(0 && "invalid shift count for vsli/vsri intrinsic");
2689      abort();
2690    }
2691
2692    return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2693                       N->getOperand(1), N->getOperand(2),
2694                       DAG.getConstant(Cnt, MVT::i32));
2695  }
2696
2697  case Intrinsic::arm_neon_vqrshifts:
2698  case Intrinsic::arm_neon_vqrshiftu:
2699    // No immediate versions of these to check for.
2700    break;
2701  }
2702
2703  return SDValue();
2704}
2705
2706/// PerformShiftCombine - Checks for immediate versions of vector shifts and
2707/// lowers them.  As with the vector shift intrinsics, this is done during DAG
2708/// combining instead of DAG legalizing because the build_vectors for 64-bit
2709/// vector element shift counts are generally not legal, and it is hard to see
2710/// their values after they get legalized to loads from a constant pool.
2711static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
2712                                   const ARMSubtarget *ST) {
2713  MVT VT = N->getValueType(0);
2714
2715  // Nothing to be done for scalar shifts.
2716  if (! VT.isVector())
2717    return SDValue();
2718
2719  assert(ST->hasNEON() && "unexpected vector shift");
2720  int64_t Cnt;
2721
2722  switch (N->getOpcode()) {
2723  default: assert(0 && "unexpected shift opcode");
2724
2725  case ISD::SHL:
2726    if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
2727      return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
2728                         DAG.getConstant(Cnt, MVT::i32));
2729    break;
2730
2731  case ISD::SRA:
2732  case ISD::SRL:
2733    if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
2734      unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
2735                            ARMISD::VSHRs : ARMISD::VSHRu);
2736      return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
2737                         DAG.getConstant(Cnt, MVT::i32));
2738    }
2739  }
2740  return SDValue();
2741}
2742
2743/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
2744/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
2745static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
2746                                    const ARMSubtarget *ST) {
2747  SDValue N0 = N->getOperand(0);
2748
2749  // Check for sign- and zero-extensions of vector extract operations of 8-
2750  // and 16-bit vector elements.  NEON supports these directly.  They are
2751  // handled during DAG combining because type legalization will promote them
2752  // to 32-bit types and it is messy to recognize the operations after that.
2753  if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
2754    SDValue Vec = N0.getOperand(0);
2755    SDValue Lane = N0.getOperand(1);
2756    MVT VT = N->getValueType(0);
2757    MVT EltVT = N0.getValueType();
2758    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2759
2760    if (VT == MVT::i32 &&
2761        (EltVT == MVT::i8 || EltVT == MVT::i16) &&
2762        TLI.isTypeLegal(Vec.getValueType())) {
2763
2764      unsigned Opc = 0;
2765      switch (N->getOpcode()) {
2766      default: assert(0 && "unexpected opcode");
2767      case ISD::SIGN_EXTEND:
2768        Opc = ARMISD::VGETLANEs;
2769        break;
2770      case ISD::ZERO_EXTEND:
2771      case ISD::ANY_EXTEND:
2772        Opc = ARMISD::VGETLANEu;
2773        break;
2774      }
2775      return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
2776    }
2777  }
2778
2779  return SDValue();
2780}
2781
2782SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
2783                                             DAGCombinerInfo &DCI) const {
2784  switch (N->getOpcode()) {
2785  default: break;
2786  case ISD::ADD:      return PerformADDCombine(N, DCI);
2787  case ISD::SUB:      return PerformSUBCombine(N, DCI);
2788  case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
2789  case ISD::INTRINSIC_WO_CHAIN:
2790    return PerformIntrinsicCombine(N, DCI.DAG);
2791  case ISD::SHL:
2792  case ISD::SRA:
2793  case ISD::SRL:
2794    return PerformShiftCombine(N, DCI.DAG, Subtarget);
2795  case ISD::SIGN_EXTEND:
2796  case ISD::ZERO_EXTEND:
2797  case ISD::ANY_EXTEND:
2798    return PerformExtendCombine(N, DCI.DAG, Subtarget);
2799  }
2800  return SDValue();
2801}
2802
2803/// isLegalAddressImmediate - Return true if the integer value can be used
2804/// as the offset of the target addressing mode for load / store of the
2805/// given type.
2806static bool isLegalAddressImmediate(int64_t V, MVT VT,
2807                                    const ARMSubtarget *Subtarget) {
2808  if (V == 0)
2809    return true;
2810
2811  if (!VT.isSimple())
2812    return false;
2813
2814  if (Subtarget->isThumb()) {
2815    if (V < 0)
2816      return false;
2817
2818    unsigned Scale = 1;
2819    switch (VT.getSimpleVT()) {
2820    default: return false;
2821    case MVT::i1:
2822    case MVT::i8:
2823      // Scale == 1;
2824      break;
2825    case MVT::i16:
2826      // Scale == 2;
2827      Scale = 2;
2828      break;
2829    case MVT::i32:
2830      // Scale == 4;
2831      Scale = 4;
2832      break;
2833    }
2834
2835    if ((V & (Scale - 1)) != 0)
2836      return false;
2837    V /= Scale;
2838    return V == (V & ((1LL << 5) - 1));
2839  }
2840
2841  if (V < 0)
2842    V = - V;
2843  switch (VT.getSimpleVT()) {
2844  default: return false;
2845  case MVT::i1:
2846  case MVT::i8:
2847  case MVT::i32:
2848    // +- imm12
2849    return V == (V & ((1LL << 12) - 1));
2850  case MVT::i16:
2851    // +- imm8
2852    return V == (V & ((1LL << 8) - 1));
2853  case MVT::f32:
2854  case MVT::f64:
2855    if (!Subtarget->hasVFP2())
2856      return false;
2857    if ((V & 3) != 0)
2858      return false;
2859    V >>= 2;
2860    return V == (V & ((1LL << 8) - 1));
2861  }
2862}
2863
2864/// isLegalAddressingMode - Return true if the addressing mode represented
2865/// by AM is legal for this target, for a load/store of the specified type.
2866bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
2867                                              const Type *Ty) const {
2868  MVT VT = getValueType(Ty, true);
2869  if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
2870    return false;
2871
2872  // Can never fold addr of global into load/store.
2873  if (AM.BaseGV)
2874    return false;
2875
2876  switch (AM.Scale) {
2877  case 0:  // no scale reg, must be "r+i" or "r", or "i".
2878    break;
2879  case 1:
2880    if (Subtarget->isThumb())
2881      return false;
2882    // FALL THROUGH.
2883  default:
2884    // ARM doesn't support any R+R*scale+imm addr modes.
2885    if (AM.BaseOffs)
2886      return false;
2887
2888    if (!VT.isSimple())
2889      return false;
2890
2891    int Scale = AM.Scale;
2892    switch (VT.getSimpleVT()) {
2893    default: return false;
2894    case MVT::i1:
2895    case MVT::i8:
2896    case MVT::i32:
2897    case MVT::i64:
2898      // This assumes i64 is legalized to a pair of i32. If not (i.e.
2899      // ldrd / strd are used, then its address mode is same as i16.
2900      // r + r
2901      if (Scale < 0) Scale = -Scale;
2902      if (Scale == 1)
2903        return true;
2904      // r + r << imm
2905      return isPowerOf2_32(Scale & ~1);
2906    case MVT::i16:
2907      // r + r
2908      if (((unsigned)AM.HasBaseReg + Scale) <= 2)
2909        return true;
2910      return false;
2911
2912    case MVT::isVoid:
2913      // Note, we allow "void" uses (basically, uses that aren't loads or
2914      // stores), because arm allows folding a scale into many arithmetic
2915      // operations.  This should be made more precise and revisited later.
2916
2917      // Allow r << imm, but the imm has to be a multiple of two.
2918      if (AM.Scale & 1) return false;
2919      return isPowerOf2_32(AM.Scale);
2920    }
2921    break;
2922  }
2923  return true;
2924}
2925
2926static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
2927                                   bool isSEXTLoad, SDValue &Base,
2928                                   SDValue &Offset, bool &isInc,
2929                                   SelectionDAG &DAG) {
2930  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
2931    return false;
2932
2933  if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
2934    // AddressingMode 3
2935    Base = Ptr->getOperand(0);
2936    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
2937      int RHSC = (int)RHS->getZExtValue();
2938      if (RHSC < 0 && RHSC > -256) {
2939        isInc = false;
2940        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
2941        return true;
2942      }
2943    }
2944    isInc = (Ptr->getOpcode() == ISD::ADD);
2945    Offset = Ptr->getOperand(1);
2946    return true;
2947  } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
2948    // AddressingMode 2
2949    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
2950      int RHSC = (int)RHS->getZExtValue();
2951      if (RHSC < 0 && RHSC > -0x1000) {
2952        isInc = false;
2953        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
2954        Base = Ptr->getOperand(0);
2955        return true;
2956      }
2957    }
2958
2959    if (Ptr->getOpcode() == ISD::ADD) {
2960      isInc = true;
2961      ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
2962      if (ShOpcVal != ARM_AM::no_shift) {
2963        Base = Ptr->getOperand(1);
2964        Offset = Ptr->getOperand(0);
2965      } else {
2966        Base = Ptr->getOperand(0);
2967        Offset = Ptr->getOperand(1);
2968      }
2969      return true;
2970    }
2971
2972    isInc = (Ptr->getOpcode() == ISD::ADD);
2973    Base = Ptr->getOperand(0);
2974    Offset = Ptr->getOperand(1);
2975    return true;
2976  }
2977
2978  // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
2979  return false;
2980}
2981
2982/// getPreIndexedAddressParts - returns true by value, base pointer and
2983/// offset pointer and addressing mode by reference if the node's address
2984/// can be legally represented as pre-indexed load / store address.
2985bool
2986ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2987                                             SDValue &Offset,
2988                                             ISD::MemIndexedMode &AM,
2989                                             SelectionDAG &DAG) const {
2990  if (Subtarget->isThumb())
2991    return false;
2992
2993  MVT VT;
2994  SDValue Ptr;
2995  bool isSEXTLoad = false;
2996  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2997    Ptr = LD->getBasePtr();
2998    VT  = LD->getMemoryVT();
2999    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3000  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3001    Ptr = ST->getBasePtr();
3002    VT  = ST->getMemoryVT();
3003  } else
3004    return false;
3005
3006  bool isInc;
3007  bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3008                                        Offset, isInc, DAG);
3009  if (isLegal) {
3010    AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3011    return true;
3012  }
3013  return false;
3014}
3015
3016/// getPostIndexedAddressParts - returns true by value, base pointer and
3017/// offset pointer and addressing mode by reference if this node can be
3018/// combined with a load / store to form a post-indexed load / store.
3019bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3020                                                   SDValue &Base,
3021                                                   SDValue &Offset,
3022                                                   ISD::MemIndexedMode &AM,
3023                                                   SelectionDAG &DAG) const {
3024  if (Subtarget->isThumb())
3025    return false;
3026
3027  MVT VT;
3028  SDValue Ptr;
3029  bool isSEXTLoad = false;
3030  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3031    VT  = LD->getMemoryVT();
3032    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3033  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3034    VT  = ST->getMemoryVT();
3035  } else
3036    return false;
3037
3038  bool isInc;
3039  bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3040                                        isInc, DAG);
3041  if (isLegal) {
3042    AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3043    return true;
3044  }
3045  return false;
3046}
3047
3048void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3049                                                       const APInt &Mask,
3050                                                       APInt &KnownZero,
3051                                                       APInt &KnownOne,
3052                                                       const SelectionDAG &DAG,
3053                                                       unsigned Depth) const {
3054  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3055  switch (Op.getOpcode()) {
3056  default: break;
3057  case ARMISD::CMOV: {
3058    // Bits are known zero/one if known on the LHS and RHS.
3059    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3060    if (KnownZero == 0 && KnownOne == 0) return;
3061
3062    APInt KnownZeroRHS, KnownOneRHS;
3063    DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3064                          KnownZeroRHS, KnownOneRHS, Depth+1);
3065    KnownZero &= KnownZeroRHS;
3066    KnownOne  &= KnownOneRHS;
3067    return;
3068  }
3069  }
3070}
3071
3072//===----------------------------------------------------------------------===//
3073//                           ARM Inline Assembly Support
3074//===----------------------------------------------------------------------===//
3075
3076/// getConstraintType - Given a constraint letter, return the type of
3077/// constraint it is for this target.
3078ARMTargetLowering::ConstraintType
3079ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3080  if (Constraint.size() == 1) {
3081    switch (Constraint[0]) {
3082    default:  break;
3083    case 'l': return C_RegisterClass;
3084    case 'w': return C_RegisterClass;
3085    }
3086  }
3087  return TargetLowering::getConstraintType(Constraint);
3088}
3089
3090std::pair<unsigned, const TargetRegisterClass*>
3091ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3092                                                MVT VT) const {
3093  if (Constraint.size() == 1) {
3094    // GCC RS6000 Constraint Letters
3095    switch (Constraint[0]) {
3096    case 'l':
3097      if (Subtarget->isThumb())
3098        return std::make_pair(0U, ARM::tGPRRegisterClass);
3099      else
3100        return std::make_pair(0U, ARM::GPRRegisterClass);
3101    case 'r':
3102      return std::make_pair(0U, ARM::GPRRegisterClass);
3103    case 'w':
3104      if (VT == MVT::f32)
3105        return std::make_pair(0U, ARM::SPRRegisterClass);
3106      if (VT == MVT::f64)
3107        return std::make_pair(0U, ARM::DPRRegisterClass);
3108      break;
3109    }
3110  }
3111  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3112}
3113
3114std::vector<unsigned> ARMTargetLowering::
3115getRegClassForInlineAsmConstraint(const std::string &Constraint,
3116                                  MVT VT) const {
3117  if (Constraint.size() != 1)
3118    return std::vector<unsigned>();
3119
3120  switch (Constraint[0]) {      // GCC ARM Constraint Letters
3121  default: break;
3122  case 'l':
3123    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3124                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3125                                 0);
3126  case 'r':
3127    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3128                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3129                                 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3130                                 ARM::R12, ARM::LR, 0);
3131  case 'w':
3132    if (VT == MVT::f32)
3133      return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3134                                   ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3135                                   ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3136                                   ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3137                                   ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3138                                   ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3139                                   ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3140                                   ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3141    if (VT == MVT::f64)
3142      return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3143                                   ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3144                                   ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3145                                   ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3146      break;
3147  }
3148
3149  return std::vector<unsigned>();
3150}
3151
3152/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3153/// vector.  If it is invalid, don't add anything to Ops.
3154void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3155                                                     char Constraint,
3156                                                     bool hasMemory,
3157                                                     std::vector<SDValue>&Ops,
3158                                                     SelectionDAG &DAG) const {
3159  SDValue Result(0, 0);
3160
3161  switch (Constraint) {
3162  default: break;
3163  case 'I': case 'J': case 'K': case 'L':
3164  case 'M': case 'N': case 'O':
3165    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3166    if (!C)
3167      return;
3168
3169    int64_t CVal64 = C->getSExtValue();
3170    int CVal = (int) CVal64;
3171    // None of these constraints allow values larger than 32 bits.  Check
3172    // that the value fits in an int.
3173    if (CVal != CVal64)
3174      return;
3175
3176    switch (Constraint) {
3177      case 'I':
3178        if (Subtarget->isThumb()) {
3179          // This must be a constant between 0 and 255, for ADD immediates.
3180          if (CVal >= 0 && CVal <= 255)
3181            break;
3182        } else {
3183          // A constant that can be used as an immediate value in a
3184          // data-processing instruction.
3185          if (ARM_AM::getSOImmVal(CVal) != -1)
3186            break;
3187        }
3188        return;
3189
3190      case 'J':
3191        if (Subtarget->isThumb()) {
3192          // This must be a constant between -255 and -1, for negated ADD
3193          // immediates. This can be used in GCC with an "n" modifier that
3194          // prints the negated value, for use with SUB instructions. It is
3195          // not useful otherwise but is implemented for compatibility.
3196          if (CVal >= -255 && CVal <= -1)
3197            break;
3198        } else {
3199          // This must be a constant between -4095 and 4095. It is not clear
3200          // what this constraint is intended for. Implemented for
3201          // compatibility with GCC.
3202          if (CVal >= -4095 && CVal <= 4095)
3203            break;
3204        }
3205        return;
3206
3207      case 'K':
3208        if (Subtarget->isThumb()) {
3209          // A 32-bit value where only one byte has a nonzero value. Exclude
3210          // zero to match GCC. This constraint is used by GCC internally for
3211          // constants that can be loaded with a move/shift combination.
3212          // It is not useful otherwise but is implemented for compatibility.
3213          if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3214            break;
3215        } else {
3216          // A constant whose bitwise inverse can be used as an immediate
3217          // value in a data-processing instruction. This can be used in GCC
3218          // with a "B" modifier that prints the inverted value, for use with
3219          // BIC and MVN instructions. It is not useful otherwise but is
3220          // implemented for compatibility.
3221          if (ARM_AM::getSOImmVal(~CVal) != -1)
3222            break;
3223        }
3224        return;
3225
3226      case 'L':
3227        if (Subtarget->isThumb()) {
3228          // This must be a constant between -7 and 7,
3229          // for 3-operand ADD/SUB immediate instructions.
3230          if (CVal >= -7 && CVal < 7)
3231            break;
3232        } else {
3233          // A constant whose negation can be used as an immediate value in a
3234          // data-processing instruction. This can be used in GCC with an "n"
3235          // modifier that prints the negated value, for use with SUB
3236          // instructions. It is not useful otherwise but is implemented for
3237          // compatibility.
3238          if (ARM_AM::getSOImmVal(-CVal) != -1)
3239            break;
3240        }
3241        return;
3242
3243      case 'M':
3244        if (Subtarget->isThumb()) {
3245          // This must be a multiple of 4 between 0 and 1020, for
3246          // ADD sp + immediate.
3247          if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3248            break;
3249        } else {
3250          // A power of two or a constant between 0 and 32.  This is used in
3251          // GCC for the shift amount on shifted register operands, but it is
3252          // useful in general for any shift amounts.
3253          if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3254            break;
3255        }
3256        return;
3257
3258      case 'N':
3259        if (Subtarget->isThumb()) {
3260          // This must be a constant between 0 and 31, for shift amounts.
3261          if (CVal >= 0 && CVal <= 31)
3262            break;
3263        }
3264        return;
3265
3266      case 'O':
3267        if (Subtarget->isThumb()) {
3268          // This must be a multiple of 4 between -508 and 508, for
3269          // ADD/SUB sp = sp + immediate.
3270          if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3271            break;
3272        }
3273        return;
3274    }
3275    Result = DAG.getTargetConstant(CVal, Op.getValueType());
3276    break;
3277  }
3278
3279  if (Result.getNode()) {
3280    Ops.push_back(Result);
3281    return;
3282  }
3283  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
3284                                                      Ops, DAG);
3285}
3286