ARMISelLowering.cpp revision 126d90770bdb17e6925b2fe26de99aa079b7b9b3 
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMISelLowering.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/CallingConv.h"
24#include "llvm/Constants.h"
25#include "llvm/Instruction.h"
26#include "llvm/Intrinsics.h"
27#include "llvm/GlobalValue.h"
28#include "llvm/CodeGen/MachineBasicBlock.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/SelectionDAG.h"
34#include "llvm/Target/TargetOptions.h"
35#include "llvm/ADT/VectorExtras.h"
36#include "llvm/Support/MathExtras.h"
37using namespace llvm;
38
39ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
40    : TargetLowering(TM), ARMPCLabelIndex(0) {
41  Subtarget = &TM.getSubtarget<ARMSubtarget>();
42
43  if (Subtarget->isTargetDarwin()) {
44    // Don't have these.
45    setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
46    setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
47
48    // Uses VFP for Thumb libfuncs if available.
49    if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
50      // Single-precision floating-point arithmetic.
51      setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
52      setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
53      setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
54      setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
55
56      // Double-precision floating-point arithmetic.
57      setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
58      setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
59      setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
60      setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
61
62      // Single-precision comparisons.
63      setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
64      setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
65      setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
66      setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
67      setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
68      setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
69      setLibcallName(RTLIB::UO_F32,  "__unordsf2vfp");
70      setLibcallName(RTLIB::O_F32,   "__unordsf2vfp");
71
72      setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
73      setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
74      setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
75      setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
76      setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
77      setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
78      setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
79      setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
80
81      // Double-precision comparisons.
82      setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
83      setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
84      setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
85      setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
86      setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
87      setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
88      setLibcallName(RTLIB::UO_F64,  "__unorddf2vfp");
89      setLibcallName(RTLIB::O_F64,   "__unorddf2vfp");
90
91      setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
92      setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
93      setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
94      setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
95      setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
96      setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
97      setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
98      setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
99
100      // Floating-point to integer conversions.
101      // i64 conversions are done via library routines even when generating VFP
102      // instructions, so use the same ones.
103      setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
104      setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
105      setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
106      setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
107
108      // Conversions between floating types.
109      setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
110      setLibcallName(RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp");
111
112      // Integer to floating-point conversions.
113      // i64 conversions are done via library routines even when generating VFP
114      // instructions, so use the same ones.
115      // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
116      // __floatunsidf vs. __floatunssidfvfp.
117      setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
118      setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
119      setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
120      setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
121    }
122  }
123
124  addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
125  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
126    addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
127    addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
128
129    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
130  }
131  computeRegisterProperties();
132
133  // ARM does not have f32 extending load.
134  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
135
136  // ARM does not have i1 sign extending load.
137  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
138
139  // ARM supports all 4 flavors of integer indexed load / store.
140  for (unsigned im = (unsigned)ISD::PRE_INC;
141       im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
142    setIndexedLoadAction(im,  MVT::i1,  Legal);
143    setIndexedLoadAction(im,  MVT::i8,  Legal);
144    setIndexedLoadAction(im,  MVT::i16, Legal);
145    setIndexedLoadAction(im,  MVT::i32, Legal);
146    setIndexedStoreAction(im, MVT::i1,  Legal);
147    setIndexedStoreAction(im, MVT::i8,  Legal);
148    setIndexedStoreAction(im, MVT::i16, Legal);
149    setIndexedStoreAction(im, MVT::i32, Legal);
150  }
151
152  // i64 operation support.
153  if (Subtarget->isThumb()) {
154    setOperationAction(ISD::MUL,     MVT::i64, Expand);
155    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
156    setOperationAction(ISD::MULHS,   MVT::i32, Expand);
157    setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
158    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
159  } else {
160    setOperationAction(ISD::MUL,     MVT::i64, Expand);
161    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
162    if (!Subtarget->hasV6Ops())
163      setOperationAction(ISD::MULHS, MVT::i32, Expand);
164  }
165  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
166  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
167  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
168  setOperationAction(ISD::SRL,       MVT::i64, Custom);
169  setOperationAction(ISD::SRA,       MVT::i64, Custom);
170
171  // ARM does not have ROTL.
172  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
173  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
174  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
175  if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
176    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
177
178  // Only ARMv6 has BSWAP.
179  if (!Subtarget->hasV6Ops())
180    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
181
182  // These are expanded into libcalls.
183  setOperationAction(ISD::SDIV,  MVT::i32, Expand);
184  setOperationAction(ISD::UDIV,  MVT::i32, Expand);
185  setOperationAction(ISD::SREM,  MVT::i32, Expand);
186  setOperationAction(ISD::UREM,  MVT::i32, Expand);
187  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
188  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
189
190  // Support label based line numbers.
191  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
192  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
193
194  setOperationAction(ISD::RET,           MVT::Other, Custom);
195  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
196  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
197  setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
198  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
199
200  // Use the default implementation.
201  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
202  setOperationAction(ISD::VAARG             , MVT::Other, Expand);
203  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
204  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
205  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
206  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
207  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
208  setOperationAction(ISD::MEMBARRIER        , MVT::Other, Expand);
209
210  if (!Subtarget->hasV6Ops()) {
211    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
212    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
213  }
214  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
215
216  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
217    // Turn f64->i64 into FMRRD iff target supports vfp2.
218    setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
219
220  // We want to custom lower some of our intrinsics.
221  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
222
223  setOperationAction(ISD::SETCC    , MVT::i32, Expand);
224  setOperationAction(ISD::SETCC    , MVT::f32, Expand);
225  setOperationAction(ISD::SETCC    , MVT::f64, Expand);
226  setOperationAction(ISD::SELECT   , MVT::i32, Expand);
227  setOperationAction(ISD::SELECT   , MVT::f32, Expand);
228  setOperationAction(ISD::SELECT   , MVT::f64, Expand);
229  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
230  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
231  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
232
233  setOperationAction(ISD::BRCOND   , MVT::Other, Expand);
234  setOperationAction(ISD::BR_CC    , MVT::i32,   Custom);
235  setOperationAction(ISD::BR_CC    , MVT::f32,   Custom);
236  setOperationAction(ISD::BR_CC    , MVT::f64,   Custom);
237  setOperationAction(ISD::BR_JT    , MVT::Other, Custom);
238
239  // We don't support sin/cos/fmod/copysign/pow
240  setOperationAction(ISD::FSIN     , MVT::f64, Expand);
241  setOperationAction(ISD::FSIN     , MVT::f32, Expand);
242  setOperationAction(ISD::FCOS     , MVT::f32, Expand);
243  setOperationAction(ISD::FCOS     , MVT::f64, Expand);
244  setOperationAction(ISD::FREM     , MVT::f64, Expand);
245  setOperationAction(ISD::FREM     , MVT::f32, Expand);
246  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
247    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
248    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
249  }
250  setOperationAction(ISD::FPOW     , MVT::f64, Expand);
251  setOperationAction(ISD::FPOW     , MVT::f32, Expand);
252
253  // int <-> fp are custom expanded into bit_convert + ARMISD ops.
254  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
255    setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
256    setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
257    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
258    setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
259  }
260
261  // We have target-specific dag combine patterns for the following nodes:
262  // ARMISD::FMRRD  - No need to call setTargetDAGCombine
263
264  setStackPointerRegisterToSaveRestore(ARM::SP);
265  setSchedulingPreference(SchedulingForRegPressure);
266  setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
267  setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
268
269  maxStoresPerMemcpy = 1;   //// temporary - rewrite interface to use type
270}
271
272
273const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
274  switch (Opcode) {
275  default: return 0;
276  case ARMISD::Wrapper:       return "ARMISD::Wrapper";
277  case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
278  case ARMISD::CALL:          return "ARMISD::CALL";
279  case ARMISD::CALL_PRED:     return "ARMISD::CALL_PRED";
280  case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
281  case ARMISD::tCALL:         return "ARMISD::tCALL";
282  case ARMISD::BRCOND:        return "ARMISD::BRCOND";
283  case ARMISD::BR_JT:         return "ARMISD::BR_JT";
284  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
285  case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
286  case ARMISD::CMP:           return "ARMISD::CMP";
287  case ARMISD::CMPNZ:         return "ARMISD::CMPNZ";
288  case ARMISD::CMPFP:         return "ARMISD::CMPFP";
289  case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
290  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
291  case ARMISD::CMOV:          return "ARMISD::CMOV";
292  case ARMISD::CNEG:          return "ARMISD::CNEG";
293
294  case ARMISD::FTOSI:         return "ARMISD::FTOSI";
295  case ARMISD::FTOUI:         return "ARMISD::FTOUI";
296  case ARMISD::SITOF:         return "ARMISD::SITOF";
297  case ARMISD::UITOF:         return "ARMISD::UITOF";
298
299  case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
300  case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
301  case ARMISD::RRX:           return "ARMISD::RRX";
302
303  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
304  case ARMISD::FMDRR:         return "ARMISD::FMDRR";
305
306  case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
307  }
308}
309
310//===----------------------------------------------------------------------===//
311// Lowering Code
312//===----------------------------------------------------------------------===//
313
314
315/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
316static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
317  switch (CC) {
318  default: assert(0 && "Unknown condition code!");
319  case ISD::SETNE:  return ARMCC::NE;
320  case ISD::SETEQ:  return ARMCC::EQ;
321  case ISD::SETGT:  return ARMCC::GT;
322  case ISD::SETGE:  return ARMCC::GE;
323  case ISD::SETLT:  return ARMCC::LT;
324  case ISD::SETLE:  return ARMCC::LE;
325  case ISD::SETUGT: return ARMCC::HI;
326  case ISD::SETUGE: return ARMCC::HS;
327  case ISD::SETULT: return ARMCC::LO;
328  case ISD::SETULE: return ARMCC::LS;
329  }
330}
331
332/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
333/// returns true if the operands should be inverted to form the proper
334/// comparison.
335static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
336                        ARMCC::CondCodes &CondCode2) {
337  bool Invert = false;
338  CondCode2 = ARMCC::AL;
339  switch (CC) {
340  default: assert(0 && "Unknown FP condition!");
341  case ISD::SETEQ:
342  case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
343  case ISD::SETGT:
344  case ISD::SETOGT: CondCode = ARMCC::GT; break;
345  case ISD::SETGE:
346  case ISD::SETOGE: CondCode = ARMCC::GE; break;
347  case ISD::SETOLT: CondCode = ARMCC::MI; break;
348  case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
349  case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
350  case ISD::SETO:   CondCode = ARMCC::VC; break;
351  case ISD::SETUO:  CondCode = ARMCC::VS; break;
352  case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
353  case ISD::SETUGT: CondCode = ARMCC::HI; break;
354  case ISD::SETUGE: CondCode = ARMCC::PL; break;
355  case ISD::SETLT:
356  case ISD::SETULT: CondCode = ARMCC::LT; break;
357  case ISD::SETLE:
358  case ISD::SETULE: CondCode = ARMCC::LE; break;
359  case ISD::SETNE:
360  case ISD::SETUNE: CondCode = ARMCC::NE; break;
361  }
362  return Invert;
363}
364
365static void
366HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
367                  unsigned StackOffset, unsigned &NeededGPRs,
368                  unsigned &NeededStackSize, unsigned &GPRPad,
369                  unsigned &StackPad, ISD::ArgFlagsTy Flags) {
370  NeededStackSize = 0;
371  NeededGPRs = 0;
372  StackPad = 0;
373  GPRPad = 0;
374  unsigned align = Flags.getOrigAlign();
375  GPRPad = NumGPRs % ((align + 3)/4);
376  StackPad = StackOffset % align;
377  unsigned firstGPR = NumGPRs + GPRPad;
378  switch (ObjectVT.getSimpleVT()) {
379  default: assert(0 && "Unhandled argument type!");
380  case MVT::i32:
381  case MVT::f32:
382    if (firstGPR < 4)
383      NeededGPRs = 1;
384    else
385      NeededStackSize = 4;
386    break;
387  case MVT::i64:
388  case MVT::f64:
389    if (firstGPR < 3)
390      NeededGPRs = 2;
391    else if (firstGPR == 3) {
392      NeededGPRs = 1;
393      NeededStackSize = 4;
394    } else
395      NeededStackSize = 8;
396  }
397}
398
399/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
400/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
401/// nodes.
402SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
403  MVT RetVT= Op.Val->getValueType(0);
404  SDOperand Chain    = Op.getOperand(0);
405  unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
406  assert((CallConv == CallingConv::C ||
407          CallConv == CallingConv::Fast) && "unknown calling convention");
408  SDOperand Callee   = Op.getOperand(4);
409  unsigned NumOps    = (Op.getNumOperands() - 5) / 2;
410  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
411  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
412
413  // Count how many bytes are to be pushed on the stack.
414  unsigned NumBytes = 0;
415
416  // Add up all the space actually used.
417  for (unsigned i = 0; i < NumOps; ++i) {
418    unsigned ObjSize;
419    unsigned ObjGPRs;
420    unsigned StackPad;
421    unsigned GPRPad;
422    MVT ObjectVT = Op.getOperand(5+2*i).getValueType();
423    ISD::ArgFlagsTy Flags =
424      cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
425    HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
426                      GPRPad, StackPad, Flags);
427    NumBytes += ObjSize + StackPad;
428    NumGPRs += ObjGPRs + GPRPad;
429  }
430
431  // Adjust the stack pointer for the new arguments...
432  // These operations are automatically eliminated by the prolog/epilog pass
433  Chain = DAG.getCALLSEQ_START(Chain,
434                               DAG.getConstant(NumBytes, MVT::i32));
435
436  SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
437
438  static const unsigned GPRArgRegs[] = {
439    ARM::R0, ARM::R1, ARM::R2, ARM::R3
440  };
441
442  NumGPRs = 0;
443  std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
444  std::vector<SDOperand> MemOpChains;
445  for (unsigned i = 0; i != NumOps; ++i) {
446    SDOperand Arg = Op.getOperand(5+2*i);
447    ISD::ArgFlagsTy Flags =
448      cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
449    MVT ArgVT = Arg.getValueType();
450
451    unsigned ObjSize;
452    unsigned ObjGPRs;
453    unsigned GPRPad;
454    unsigned StackPad;
455    HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
456                      ObjSize, GPRPad, StackPad, Flags);
457    NumGPRs += GPRPad;
458    ArgOffset += StackPad;
459    if (ObjGPRs > 0) {
460      switch (ArgVT.getSimpleVT()) {
461      default: assert(0 && "Unexpected ValueType for argument!");
462      case MVT::i32:
463        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
464        break;
465      case MVT::f32:
466        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
467                                 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
468        break;
469      case MVT::i64: {
470        SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
471                                   DAG.getConstant(0, getPointerTy()));
472        SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
473                                   DAG.getConstant(1, getPointerTy()));
474        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
475        if (ObjGPRs == 2)
476          RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
477        else {
478          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
479          PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
480          MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
481        }
482        break;
483      }
484      case MVT::f64: {
485        SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
486                                    DAG.getVTList(MVT::i32, MVT::i32),
487                                    &Arg, 1);
488        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
489        if (ObjGPRs == 2)
490          RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
491                                              Cvt.getValue(1)));
492        else {
493          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
494          PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
495          MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
496                                             NULL, 0));
497        }
498        break;
499      }
500      }
501    } else {
502      assert(ObjSize != 0);
503      SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
504      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
505      MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
506    }
507
508    NumGPRs += ObjGPRs;
509    ArgOffset += ObjSize;
510  }
511
512  if (!MemOpChains.empty())
513    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
514                        &MemOpChains[0], MemOpChains.size());
515
516  // Build a sequence of copy-to-reg nodes chained together with token chain
517  // and flag operands which copy the outgoing args into the appropriate regs.
518  SDOperand InFlag;
519  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
520    Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
521                             InFlag);
522    InFlag = Chain.getValue(1);
523  }
524
525  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
526  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
527  // node so that legalize doesn't hack it.
528  bool isDirect = false;
529  bool isARMFunc = false;
530  bool isLocalARMFunc = false;
531  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
532    GlobalValue *GV = G->getGlobal();
533    isDirect = true;
534    bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
535                  GV->hasLinkOnceLinkage());
536    bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
537                   getTargetMachine().getRelocationModel() != Reloc::Static;
538    isARMFunc = !Subtarget->isThumb() || isStub;
539    // ARM call to a local ARM function is predicable.
540    isLocalARMFunc = !Subtarget->isThumb() && !isExt;
541    // tBX takes a register source operand.
542    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
543      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
544                                                           ARMCP::CPStub, 4);
545      SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
546      CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
547      Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
548      SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
549      Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
550   } else
551      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
552  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
553    isDirect = true;
554    bool isStub = Subtarget->isTargetDarwin() &&
555                  getTargetMachine().getRelocationModel() != Reloc::Static;
556    isARMFunc = !Subtarget->isThumb() || isStub;
557    // tBX takes a register source operand.
558    const char *Sym = S->getSymbol();
559    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
560      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
561                                                           ARMCP::CPStub, 4);
562      SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
563      CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
564      Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
565      SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
566      Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
567    } else
568      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
569  }
570
571  // FIXME: handle tail calls differently.
572  unsigned CallOpc;
573  if (Subtarget->isThumb()) {
574    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
575      CallOpc = ARMISD::CALL_NOLINK;
576    else
577      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
578  } else {
579    CallOpc = (isDirect || Subtarget->hasV5TOps())
580      ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
581      : ARMISD::CALL_NOLINK;
582  }
583  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
584    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
585    Chain = DAG.getCopyToReg(Chain, ARM::LR,
586                             DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
587    InFlag = Chain.getValue(1);
588  }
589
590  std::vector<SDOperand> Ops;
591  Ops.push_back(Chain);
592  Ops.push_back(Callee);
593
594  // Add argument registers to the end of the list so that they are known live
595  // into the call.
596  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
597    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
598                                  RegsToPass[i].second.getValueType()));
599
600  if (InFlag.Val)
601    Ops.push_back(InFlag);
602  // Returns a chain and a flag for retval copy to use.
603  Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
604                      &Ops[0], Ops.size());
605  InFlag = Chain.getValue(1);
606
607  Chain = DAG.getCALLSEQ_END(Chain,
608                             DAG.getConstant(NumBytes, MVT::i32),
609                             DAG.getConstant(0, MVT::i32),
610                             InFlag);
611  if (RetVT != MVT::Other)
612    InFlag = Chain.getValue(1);
613
614  std::vector<SDOperand> ResultVals;
615
616  // If the call has results, copy the values out of the ret val registers.
617  switch (RetVT.getSimpleVT()) {
618  default: assert(0 && "Unexpected ret value!");
619  case MVT::Other:
620    break;
621  case MVT::i32:
622    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
623    ResultVals.push_back(Chain.getValue(0));
624    if (Op.Val->getValueType(1) == MVT::i32) {
625      // Returns a i64 value.
626      Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
627                                 Chain.getValue(2)).getValue(1);
628      ResultVals.push_back(Chain.getValue(0));
629    }
630    break;
631  case MVT::f32:
632    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
633    ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
634                                     Chain.getValue(0)));
635    break;
636  case MVT::f64: {
637    SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
638    SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
639    ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
640    break;
641  }
642  }
643
644  if (ResultVals.empty())
645    return Chain;
646
647  ResultVals.push_back(Chain);
648  SDOperand Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
649  return Res.getValue(Op.ResNo);
650}
651
652static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
653  SDOperand Copy;
654  SDOperand Chain = Op.getOperand(0);
655  switch(Op.getNumOperands()) {
656  default:
657    assert(0 && "Do not know how to return this many arguments!");
658    abort();
659  case 1: {
660    SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
661    return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
662  }
663  case 3:
664    Op = Op.getOperand(1);
665    if (Op.getValueType() == MVT::f32) {
666      Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
667    } else if (Op.getValueType() == MVT::f64) {
668      // Legalize ret f64 -> ret 2 x i32.  We always have fmrrd if f64 is
669      // available.
670      Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
671      SDOperand Sign = DAG.getConstant(0, MVT::i32);
672      return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
673                         Op.getValue(1), Sign);
674    }
675    Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
676    if (DAG.getMachineFunction().getRegInfo().liveout_empty())
677      DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
678    break;
679  case 5:
680    Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
681    Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
682    // If we haven't noted the R0+R1 are live out, do so now.
683    if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
684      DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
685      DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
686    }
687    break;
688  }
689
690  //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
691  return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
692}
693
694// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
695// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
696// one of the above mentioned nodes. It has to be wrapped because otherwise
697// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
698// be used to form addressing mode. These wrapped nodes will be selected
699// into MOVi.
700static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
701  MVT PtrVT = Op.getValueType();
702  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
703  SDOperand Res;
704  if (CP->isMachineConstantPoolEntry())
705    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
706                                    CP->getAlignment());
707  else
708    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
709                                    CP->getAlignment());
710  return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
711}
712
713// Lower ISD::GlobalTLSAddress using the "general dynamic" model
714SDOperand
715ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
716                                                 SelectionDAG &DAG) {
717  MVT PtrVT = getPointerTy();
718  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
719  ARMConstantPoolValue *CPV =
720    new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
721                             PCAdj, "tlsgd", true);
722  SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
723  Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
724  Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
725  SDOperand Chain = Argument.getValue(1);
726
727  SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
728  Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
729
730  // call __tls_get_addr.
731  ArgListTy Args;
732  ArgListEntry Entry;
733  Entry.Node = Argument;
734  Entry.Ty = (const Type *) Type::Int32Ty;
735  Args.push_back(Entry);
736  std::pair<SDOperand, SDOperand> CallResult =
737    LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false,
738                CallingConv::C, false,
739                DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
740  return CallResult.first;
741}
742
743// Lower ISD::GlobalTLSAddress using the "initial exec" or
744// "local exec" model.
745SDOperand
746ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
747                                            SelectionDAG &DAG) {
748  GlobalValue *GV = GA->getGlobal();
749  SDOperand Offset;
750  SDOperand Chain = DAG.getEntryNode();
751  MVT PtrVT = getPointerTy();
752  // Get the Thread Pointer
753  SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
754
755  if (GV->isDeclaration()){
756    // initial exec model
757    unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
758    ARMConstantPoolValue *CPV =
759      new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
760                               PCAdj, "gottpoff", true);
761    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
762    Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
763    Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
764    Chain = Offset.getValue(1);
765
766    SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
767    Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
768
769    Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
770  } else {
771    // local exec model
772    ARMConstantPoolValue *CPV =
773      new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
774    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
775    Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
776    Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
777  }
778
779  // The address of the thread local variable is the add of the thread
780  // pointer with the offset of the variable.
781  return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
782}
783
784SDOperand
785ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
786  // TODO: implement the "local dynamic" model
787  assert(Subtarget->isTargetELF() &&
788         "TLS not implemented for non-ELF targets");
789  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
790  // If the relocation model is PIC, use the "General Dynamic" TLS Model,
791  // otherwise use the "Local Exec" TLS Model
792  if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
793    return LowerToTLSGeneralDynamicModel(GA, DAG);
794  else
795    return LowerToTLSExecModels(GA, DAG);
796}
797
798SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
799                                                   SelectionDAG &DAG) {
800  MVT PtrVT = getPointerTy();
801  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
802  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
803  if (RelocM == Reloc::PIC_) {
804    bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
805    ARMConstantPoolValue *CPV =
806      new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
807    SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
808    CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
809    SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
810    SDOperand Chain = Result.getValue(1);
811    SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
812    Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
813    if (!UseGOTOFF)
814      Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
815    return Result;
816  } else {
817    SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
818    CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
819    return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
820  }
821}
822
823/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
824/// even in non-static mode.
825static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
826  return RelocM != Reloc::Static &&
827    (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
828     (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
829}
830
831SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
832                                                      SelectionDAG &DAG) {
833  MVT PtrVT = getPointerTy();
834  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
835  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
836  bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
837  SDOperand CPAddr;
838  if (RelocM == Reloc::Static)
839    CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
840  else {
841    unsigned PCAdj = (RelocM != Reloc::PIC_)
842      ? 0 : (Subtarget->isThumb() ? 4 : 8);
843    ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
844      : ARMCP::CPValue;
845    ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
846                                                         Kind, PCAdj);
847    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
848  }
849  CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
850
851  SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
852  SDOperand Chain = Result.getValue(1);
853
854  if (RelocM == Reloc::PIC_) {
855    SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
856    Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
857  }
858  if (IsIndirect)
859    Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
860
861  return Result;
862}
863
864SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
865                                                      SelectionDAG &DAG){
866  assert(Subtarget->isTargetELF() &&
867         "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
868  MVT PtrVT = getPointerTy();
869  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
870  ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
871                                                       ARMPCLabelIndex,
872                                                       ARMCP::CPValue, PCAdj);
873  SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
874  CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
875  SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
876  SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
877  return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
878}
879
880static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
881  MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
882  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
883  switch (IntNo) {
884  default: return SDOperand();    // Don't custom lower most intrinsics.
885  case Intrinsic::arm_thread_pointer:
886      return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
887  }
888}
889
890static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
891                              unsigned VarArgsFrameIndex) {
892  // vastart just stores the address of the VarArgsFrameIndex slot into the
893  // memory location argument.
894  MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
895  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
896  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
897  return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
898}
899
900static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
901                                      unsigned ArgNo, unsigned &NumGPRs,
902                                      unsigned &ArgOffset) {
903  MachineFunction &MF = DAG.getMachineFunction();
904  MVT ObjectVT = Op.getValue(ArgNo).getValueType();
905  SDOperand Root = Op.getOperand(0);
906  std::vector<SDOperand> ArgValues;
907  MachineRegisterInfo &RegInfo = MF.getRegInfo();
908
909  static const unsigned GPRArgRegs[] = {
910    ARM::R0, ARM::R1, ARM::R2, ARM::R3
911  };
912
913  unsigned ObjSize;
914  unsigned ObjGPRs;
915  unsigned GPRPad;
916  unsigned StackPad;
917  ISD::ArgFlagsTy Flags =
918    cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo + 3))->getArgFlags();
919  HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
920                    ObjSize, GPRPad, StackPad, Flags);
921  NumGPRs += GPRPad;
922  ArgOffset += StackPad;
923
924  SDOperand ArgValue;
925  if (ObjGPRs == 1) {
926    unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
927    RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
928    ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
929    if (ObjectVT == MVT::f32)
930      ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
931  } else if (ObjGPRs == 2) {
932    unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
933    RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
934    ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
935
936    VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
937    RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
938    SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
939
940    assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
941    ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
942  }
943  NumGPRs += ObjGPRs;
944
945  if (ObjSize) {
946    MachineFrameInfo *MFI = MF.getFrameInfo();
947    int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
948    SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
949    if (ObjGPRs == 0)
950      ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
951    else {
952      SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
953      assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
954      ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
955    }
956
957    ArgOffset += ObjSize;   // Move on to the next argument.
958  }
959
960  return ArgValue;
961}
962
963SDOperand
964ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
965  std::vector<SDOperand> ArgValues;
966  SDOperand Root = Op.getOperand(0);
967  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
968  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
969
970  unsigned NumArgs = Op.Val->getNumValues()-1;
971  for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
972    ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
973                                             NumGPRs, ArgOffset));
974
975  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
976  if (isVarArg) {
977    static const unsigned GPRArgRegs[] = {
978      ARM::R0, ARM::R1, ARM::R2, ARM::R3
979    };
980
981    MachineFunction &MF = DAG.getMachineFunction();
982    MachineRegisterInfo &RegInfo = MF.getRegInfo();
983    MachineFrameInfo *MFI = MF.getFrameInfo();
984    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
985    unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
986    unsigned VARegSize = (4 - NumGPRs) * 4;
987    unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
988    if (VARegSaveSize) {
989      // If this function is vararg, store any remaining integer argument regs
990      // to their spots on the stack so that they may be loaded by deferencing
991      // the result of va_next.
992      AFI->setVarArgsRegSaveSize(VARegSaveSize);
993      VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
994                                                 VARegSaveSize - VARegSize);
995      SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
996
997      SmallVector<SDOperand, 4> MemOps;
998      for (; NumGPRs < 4; ++NumGPRs) {
999        unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
1000        RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1001        SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1002        SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1003        MemOps.push_back(Store);
1004        FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1005                          DAG.getConstant(4, getPointerTy()));
1006      }
1007      if (!MemOps.empty())
1008        Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1009                           &MemOps[0], MemOps.size());
1010    } else
1011      // This will point to the next argument passed via stack.
1012      VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1013  }
1014
1015  ArgValues.push_back(Root);
1016
1017  // Return the new list of results.
1018  return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
1019                            ArgValues.size());
1020}
1021
1022/// isFloatingPointZero - Return true if this is +0.0.
1023static bool isFloatingPointZero(SDOperand Op) {
1024  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1025    return CFP->getValueAPF().isPosZero();
1026  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
1027    // Maybe this has already been legalized into the constant pool?
1028    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1029      SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
1030      if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1031        if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1032          return CFP->getValueAPF().isPosZero();
1033    }
1034  }
1035  return false;
1036}
1037
1038static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1039  return ( isThumb && (C & ~255U) == 0) ||
1040         (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1041}
1042
1043/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1044/// the given operands.
1045static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
1046                           SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
1047  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
1048    unsigned C = RHSC->getValue();
1049    if (!isLegalCmpImmediate(C, isThumb)) {
1050      // Constant does not fit, try adjusting it by one?
1051      switch (CC) {
1052      default: break;
1053      case ISD::SETLT:
1054      case ISD::SETGE:
1055        if (isLegalCmpImmediate(C-1, isThumb)) {
1056          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1057          RHS = DAG.getConstant(C-1, MVT::i32);
1058        }
1059        break;
1060      case ISD::SETULT:
1061      case ISD::SETUGE:
1062        if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1063          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1064          RHS = DAG.getConstant(C-1, MVT::i32);
1065        }
1066        break;
1067      case ISD::SETLE:
1068      case ISD::SETGT:
1069        if (isLegalCmpImmediate(C+1, isThumb)) {
1070          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1071          RHS = DAG.getConstant(C+1, MVT::i32);
1072        }
1073        break;
1074      case ISD::SETULE:
1075      case ISD::SETUGT:
1076        if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1077          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1078          RHS = DAG.getConstant(C+1, MVT::i32);
1079        }
1080        break;
1081      }
1082    }
1083  }
1084
1085  ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1086  ARMISD::NodeType CompareType;
1087  switch (CondCode) {
1088  default:
1089    CompareType = ARMISD::CMP;
1090    break;
1091  case ARMCC::EQ:
1092  case ARMCC::NE:
1093  case ARMCC::MI:
1094  case ARMCC::PL:
1095    // Uses only N and Z Flags
1096    CompareType = ARMISD::CMPNZ;
1097    break;
1098  }
1099  ARMCC = DAG.getConstant(CondCode, MVT::i32);
1100  return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1101}
1102
1103/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1104static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
1105  SDOperand Cmp;
1106  if (!isFloatingPointZero(RHS))
1107    Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1108  else
1109    Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1110  return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1111}
1112
1113static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
1114                                const ARMSubtarget *ST) {
1115  MVT VT = Op.getValueType();
1116  SDOperand LHS = Op.getOperand(0);
1117  SDOperand RHS = Op.getOperand(1);
1118  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1119  SDOperand TrueVal = Op.getOperand(2);
1120  SDOperand FalseVal = Op.getOperand(3);
1121
1122  if (LHS.getValueType() == MVT::i32) {
1123    SDOperand ARMCC;
1124    SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1125    SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1126    return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
1127  }
1128
1129  ARMCC::CondCodes CondCode, CondCode2;
1130  if (FPCCToARMCC(CC, CondCode, CondCode2))
1131    std::swap(TrueVal, FalseVal);
1132
1133  SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1134  SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1135  SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1136  SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1137                                 ARMCC, CCR, Cmp);
1138  if (CondCode2 != ARMCC::AL) {
1139    SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1140    // FIXME: Needs another CMP because flag can have but one use.
1141    SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
1142    Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
1143  }
1144  return Result;
1145}
1146
1147static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
1148                            const ARMSubtarget *ST) {
1149  SDOperand  Chain = Op.getOperand(0);
1150  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1151  SDOperand    LHS = Op.getOperand(2);
1152  SDOperand    RHS = Op.getOperand(3);
1153  SDOperand   Dest = Op.getOperand(4);
1154
1155  if (LHS.getValueType() == MVT::i32) {
1156    SDOperand ARMCC;
1157    SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1158    SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1159    return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
1160  }
1161
1162  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1163  ARMCC::CondCodes CondCode, CondCode2;
1164  if (FPCCToARMCC(CC, CondCode, CondCode2))
1165    // Swap the LHS/RHS of the comparison if needed.
1166    std::swap(LHS, RHS);
1167
1168  SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1169  SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1170  SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1171  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1172  SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1173  SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1174  if (CondCode2 != ARMCC::AL) {
1175    ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1176    SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1177    Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1178  }
1179  return Res;
1180}
1181
1182SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1183  SDOperand Chain = Op.getOperand(0);
1184  SDOperand Table = Op.getOperand(1);
1185  SDOperand Index = Op.getOperand(2);
1186
1187  MVT PTy = getPointerTy();
1188  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1189  ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1190  SDOperand UId =  DAG.getConstant(AFI->createJumpTableUId(), PTy);
1191  SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1192  Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1193  Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1194  SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1195  bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1196  Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy,
1197                     Chain, Addr, NULL, 0);
1198  Chain = Addr.getValue(1);
1199  if (isPIC)
1200    Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1201  return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1202}
1203
1204static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1205  unsigned Opc =
1206    Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1207  Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1208  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1209}
1210
1211static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1212  MVT VT = Op.getValueType();
1213  unsigned Opc =
1214    Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1215
1216  Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1217  return DAG.getNode(Opc, VT, Op);
1218}
1219
1220static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1221  // Implement fcopysign with a fabs and a conditional fneg.
1222  SDOperand Tmp0 = Op.getOperand(0);
1223  SDOperand Tmp1 = Op.getOperand(1);
1224  MVT VT = Op.getValueType();
1225  MVT SrcVT = Tmp1.getValueType();
1226  SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1227  SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1228  SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1229  SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1230  return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1231}
1232
1233SDOperand
1234ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
1235                                           SDOperand Chain,
1236                                           SDOperand Dst, SDOperand Src,
1237                                           SDOperand Size, unsigned Align,
1238                                           bool AlwaysInline,
1239                                         const Value *DstSV, uint64_t DstSVOff,
1240                                         const Value *SrcSV, uint64_t SrcSVOff){
1241  // Do repeated 4-byte loads and stores. To be improved.
1242  // This requires 4-byte alignment.
1243  if ((Align & 3) != 0)
1244    return SDOperand();
1245  // This requires the copy size to be a constant, preferrably
1246  // within a subtarget-specific limit.
1247  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1248  if (!ConstantSize)
1249    return SDOperand();
1250  uint64_t SizeVal = ConstantSize->getValue();
1251  if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1252    return SDOperand();
1253
1254  unsigned BytesLeft = SizeVal & 3;
1255  unsigned NumMemOps = SizeVal >> 2;
1256  unsigned EmittedNumMemOps = 0;
1257  MVT VT = MVT::i32;
1258  unsigned VTSize = 4;
1259  unsigned i = 0;
1260  const unsigned MAX_LOADS_IN_LDM = 6;
1261  SDOperand TFOps[MAX_LOADS_IN_LDM];
1262  SDOperand Loads[MAX_LOADS_IN_LDM];
1263  uint64_t SrcOff = 0, DstOff = 0;
1264
1265  // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1266  // same number of stores.  The loads and stores will get combined into
1267  // ldm/stm later on.
1268  while (EmittedNumMemOps < NumMemOps) {
1269    for (i = 0;
1270         i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1271      Loads[i] = DAG.getLoad(VT, Chain,
1272                             DAG.getNode(ISD::ADD, MVT::i32, Src,
1273                                         DAG.getConstant(SrcOff, MVT::i32)),
1274                             SrcSV, SrcSVOff + SrcOff);
1275      TFOps[i] = Loads[i].getValue(1);
1276      SrcOff += VTSize;
1277    }
1278    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1279
1280    for (i = 0;
1281         i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1282      TFOps[i] = DAG.getStore(Chain, Loads[i],
1283                           DAG.getNode(ISD::ADD, MVT::i32, Dst,
1284                                       DAG.getConstant(DstOff, MVT::i32)),
1285                           DstSV, DstSVOff + DstOff);
1286      DstOff += VTSize;
1287    }
1288    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1289
1290    EmittedNumMemOps += i;
1291  }
1292
1293  if (BytesLeft == 0)
1294    return Chain;
1295
1296  // Issue loads / stores for the trailing (1 - 3) bytes.
1297  unsigned BytesLeftSave = BytesLeft;
1298  i = 0;
1299  while (BytesLeft) {
1300    if (BytesLeft >= 2) {
1301      VT = MVT::i16;
1302      VTSize = 2;
1303    } else {
1304      VT = MVT::i8;
1305      VTSize = 1;
1306    }
1307
1308    Loads[i] = DAG.getLoad(VT, Chain,
1309                           DAG.getNode(ISD::ADD, MVT::i32, Src,
1310                                       DAG.getConstant(SrcOff, MVT::i32)),
1311                           SrcSV, SrcSVOff + SrcOff);
1312    TFOps[i] = Loads[i].getValue(1);
1313    ++i;
1314    SrcOff += VTSize;
1315    BytesLeft -= VTSize;
1316  }
1317  Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1318
1319  i = 0;
1320  BytesLeft = BytesLeftSave;
1321  while (BytesLeft) {
1322    if (BytesLeft >= 2) {
1323      VT = MVT::i16;
1324      VTSize = 2;
1325    } else {
1326      VT = MVT::i8;
1327      VTSize = 1;
1328    }
1329
1330    TFOps[i] = DAG.getStore(Chain, Loads[i],
1331                            DAG.getNode(ISD::ADD, MVT::i32, Dst,
1332                                        DAG.getConstant(DstOff, MVT::i32)),
1333                            DstSV, DstSVOff + DstOff);
1334    ++i;
1335    DstOff += VTSize;
1336    BytesLeft -= VTSize;
1337  }
1338  return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1339}
1340
1341static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1342  // Turn f64->i64 into FMRRD.
1343  assert(N->getValueType(0) == MVT::i64 &&
1344         N->getOperand(0).getValueType() == MVT::f64);
1345
1346  SDOperand Op = N->getOperand(0);
1347  SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1348                              &Op, 1);
1349
1350  // Merge the pieces into a single i64 value.
1351  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val;
1352}
1353
1354static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1355  assert(N->getValueType(0) == MVT::i64 &&
1356         (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1357         "Unknown shift to lower!");
1358
1359  // We only lower SRA, SRL of 1 here, all others use generic lowering.
1360  if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1361      cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1)
1362    return 0;
1363
1364  // If we are in thumb mode, we don't have RRX.
1365  if (ST->isThumb()) return 0;
1366
1367  // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
1368  SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1369                             DAG.getConstant(0, MVT::i32));
1370  SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1371                             DAG.getConstant(1, MVT::i32));
1372
1373  // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1374  // captures the result into a carry flag.
1375  unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1376  Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1377
1378  // The low part is an ARMISD::RRX operand, which shifts the carry in.
1379  Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1380
1381  // Merge the pieces into a single i64 value.
1382 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
1383}
1384
1385
1386SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1387  switch (Op.getOpcode()) {
1388  default: assert(0 && "Don't know how to custom lower this!"); abort();
1389  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
1390  case ISD::GlobalAddress:
1391    return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1392      LowerGlobalAddressELF(Op, DAG);
1393  case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
1394  case ISD::CALL:          return LowerCALL(Op, DAG);
1395  case ISD::RET:           return LowerRET(Op, DAG);
1396  case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG, Subtarget);
1397  case ISD::BR_CC:         return LowerBR_CC(Op, DAG, Subtarget);
1398  case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
1399  case ISD::VASTART:       return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1400  case ISD::SINT_TO_FP:
1401  case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
1402  case ISD::FP_TO_SINT:
1403  case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
1404  case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
1405  case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1406  case ISD::RETURNADDR:    break;
1407  case ISD::FRAMEADDR:     break;
1408  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1409  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1410
1411
1412  // FIXME: Remove these when LegalizeDAGTypes lands.
1413  case ISD::BIT_CONVERT:   return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0);
1414  case ISD::SRL:
1415  case ISD::SRA:           return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0);
1416  }
1417  return SDOperand();
1418}
1419
1420
1421/// ReplaceNodeResults - Provide custom lowering hooks for nodes with illegal
1422/// result types.
1423SDNode *ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
1424  switch (N->getOpcode()) {
1425  default: assert(0 && "Don't know how to custom expand this!"); abort();
1426  case ISD::BIT_CONVERT:   return ExpandBIT_CONVERT(N, DAG);
1427  case ISD::SRL:
1428  case ISD::SRA:           return ExpandSRx(N, DAG, Subtarget);
1429  }
1430}
1431
1432
1433//===----------------------------------------------------------------------===//
1434//                           ARM Scheduler Hooks
1435//===----------------------------------------------------------------------===//
1436
1437MachineBasicBlock *
1438ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1439                                           MachineBasicBlock *BB) {
1440  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1441  switch (MI->getOpcode()) {
1442  default: assert(false && "Unexpected instr type to insert");
1443  case ARM::tMOVCCr: {
1444    // To "insert" a SELECT_CC instruction, we actually have to insert the
1445    // diamond control-flow pattern.  The incoming instruction knows the
1446    // destination vreg to set, the condition code register to branch on, the
1447    // true/false values to select between, and a branch opcode to use.
1448    const BasicBlock *LLVM_BB = BB->getBasicBlock();
1449    ilist<MachineBasicBlock>::iterator It = BB;
1450    ++It;
1451
1452    //  thisMBB:
1453    //  ...
1454    //   TrueVal = ...
1455    //   cmpTY ccX, r1, r2
1456    //   bCC copy1MBB
1457    //   fallthrough --> copy0MBB
1458    MachineBasicBlock *thisMBB  = BB;
1459    MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1460    MachineBasicBlock *sinkMBB  = new MachineBasicBlock(LLVM_BB);
1461    BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1462      .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1463    MachineFunction *F = BB->getParent();
1464    F->getBasicBlockList().insert(It, copy0MBB);
1465    F->getBasicBlockList().insert(It, sinkMBB);
1466    // Update machine-CFG edges by first adding all successors of the current
1467    // block to the new block which will contain the Phi node for the select.
1468    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1469        e = BB->succ_end(); i != e; ++i)
1470      sinkMBB->addSuccessor(*i);
1471    // Next, remove all successors of the current block, and add the true
1472    // and fallthrough blocks as its successors.
1473    while(!BB->succ_empty())
1474      BB->removeSuccessor(BB->succ_begin());
1475    BB->addSuccessor(copy0MBB);
1476    BB->addSuccessor(sinkMBB);
1477
1478    //  copy0MBB:
1479    //   %FalseValue = ...
1480    //   # fallthrough to sinkMBB
1481    BB = copy0MBB;
1482
1483    // Update machine-CFG edges
1484    BB->addSuccessor(sinkMBB);
1485
1486    //  sinkMBB:
1487    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1488    //  ...
1489    BB = sinkMBB;
1490    BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1491      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1492      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1493
1494    delete MI;   // The pseudo instruction is gone now.
1495    return BB;
1496  }
1497  }
1498}
1499
1500//===----------------------------------------------------------------------===//
1501//                           ARM Optimization Hooks
1502//===----------------------------------------------------------------------===//
1503
1504/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1505static SDOperand PerformFMRRDCombine(SDNode *N,
1506                                     TargetLowering::DAGCombinerInfo &DCI) {
1507  // fmrrd(fmdrr x, y) -> x,y
1508  SDOperand InDouble = N->getOperand(0);
1509  if (InDouble.getOpcode() == ARMISD::FMDRR)
1510    return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1511  return SDOperand();
1512}
1513
1514SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
1515                                               DAGCombinerInfo &DCI) const {
1516  switch (N->getOpcode()) {
1517  default: break;
1518  case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1519  }
1520
1521  return SDOperand();
1522}
1523
1524
1525/// isLegalAddressImmediate - Return true if the integer value can be used
1526/// as the offset of the target addressing mode for load / store of the
1527/// given type.
1528static bool isLegalAddressImmediate(int64_t V, MVT VT,
1529                                    const ARMSubtarget *Subtarget) {
1530  if (V == 0)
1531    return true;
1532
1533  if (Subtarget->isThumb()) {
1534    if (V < 0)
1535      return false;
1536
1537    unsigned Scale = 1;
1538    switch (VT.getSimpleVT()) {
1539    default: return false;
1540    case MVT::i1:
1541    case MVT::i8:
1542      // Scale == 1;
1543      break;
1544    case MVT::i16:
1545      // Scale == 2;
1546      Scale = 2;
1547      break;
1548    case MVT::i32:
1549      // Scale == 4;
1550      Scale = 4;
1551      break;
1552    }
1553
1554    if ((V & (Scale - 1)) != 0)
1555      return false;
1556    V /= Scale;
1557    return V == (V & ((1LL << 5) - 1));
1558  }
1559
1560  if (V < 0)
1561    V = - V;
1562  switch (VT.getSimpleVT()) {
1563  default: return false;
1564  case MVT::i1:
1565  case MVT::i8:
1566  case MVT::i32:
1567    // +- imm12
1568    return V == (V & ((1LL << 12) - 1));
1569  case MVT::i16:
1570    // +- imm8
1571    return V == (V & ((1LL << 8) - 1));
1572  case MVT::f32:
1573  case MVT::f64:
1574    if (!Subtarget->hasVFP2())
1575      return false;
1576    if ((V & 3) != 0)
1577      return false;
1578    V >>= 2;
1579    return V == (V & ((1LL << 8) - 1));
1580  }
1581}
1582
1583/// isLegalAddressingMode - Return true if the addressing mode represented
1584/// by AM is legal for this target, for a load/store of the specified type.
1585bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1586                                              const Type *Ty) const {
1587  if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
1588    return false;
1589
1590  // Can never fold addr of global into load/store.
1591  if (AM.BaseGV)
1592    return false;
1593
1594  switch (AM.Scale) {
1595  case 0:  // no scale reg, must be "r+i" or "r", or "i".
1596    break;
1597  case 1:
1598    if (Subtarget->isThumb())
1599      return false;
1600    // FALL THROUGH.
1601  default:
1602    // ARM doesn't support any R+R*scale+imm addr modes.
1603    if (AM.BaseOffs)
1604      return false;
1605
1606    int Scale = AM.Scale;
1607    switch (getValueType(Ty).getSimpleVT()) {
1608    default: return false;
1609    case MVT::i1:
1610    case MVT::i8:
1611    case MVT::i32:
1612    case MVT::i64:
1613      // This assumes i64 is legalized to a pair of i32. If not (i.e.
1614      // ldrd / strd are used, then its address mode is same as i16.
1615      // r + r
1616      if (Scale < 0) Scale = -Scale;
1617      if (Scale == 1)
1618        return true;
1619      // r + r << imm
1620      return isPowerOf2_32(Scale & ~1);
1621    case MVT::i16:
1622      // r + r
1623      if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1624        return true;
1625      return false;
1626
1627    case MVT::isVoid:
1628      // Note, we allow "void" uses (basically, uses that aren't loads or
1629      // stores), because arm allows folding a scale into many arithmetic
1630      // operations.  This should be made more precise and revisited later.
1631
1632      // Allow r << imm, but the imm has to be a multiple of two.
1633      if (AM.Scale & 1) return false;
1634      return isPowerOf2_32(AM.Scale);
1635    }
1636    break;
1637  }
1638  return true;
1639}
1640
1641
1642static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1643                                   bool isSEXTLoad, SDOperand &Base,
1644                                   SDOperand &Offset, bool &isInc,
1645                                   SelectionDAG &DAG) {
1646  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1647    return false;
1648
1649  if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1650    // AddressingMode 3
1651    Base = Ptr->getOperand(0);
1652    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1653      int RHSC = (int)RHS->getValue();
1654      if (RHSC < 0 && RHSC > -256) {
1655        isInc = false;
1656        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1657        return true;
1658      }
1659    }
1660    isInc = (Ptr->getOpcode() == ISD::ADD);
1661    Offset = Ptr->getOperand(1);
1662    return true;
1663  } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1664    // AddressingMode 2
1665    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1666      int RHSC = (int)RHS->getValue();
1667      if (RHSC < 0 && RHSC > -0x1000) {
1668        isInc = false;
1669        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1670        Base = Ptr->getOperand(0);
1671        return true;
1672      }
1673    }
1674
1675    if (Ptr->getOpcode() == ISD::ADD) {
1676      isInc = true;
1677      ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1678      if (ShOpcVal != ARM_AM::no_shift) {
1679        Base = Ptr->getOperand(1);
1680        Offset = Ptr->getOperand(0);
1681      } else {
1682        Base = Ptr->getOperand(0);
1683        Offset = Ptr->getOperand(1);
1684      }
1685      return true;
1686    }
1687
1688    isInc = (Ptr->getOpcode() == ISD::ADD);
1689    Base = Ptr->getOperand(0);
1690    Offset = Ptr->getOperand(1);
1691    return true;
1692  }
1693
1694  // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1695  return false;
1696}
1697
1698/// getPreIndexedAddressParts - returns true by value, base pointer and
1699/// offset pointer and addressing mode by reference if the node's address
1700/// can be legally represented as pre-indexed load / store address.
1701bool
1702ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1703                                             SDOperand &Offset,
1704                                             ISD::MemIndexedMode &AM,
1705                                             SelectionDAG &DAG) {
1706  if (Subtarget->isThumb())
1707    return false;
1708
1709  MVT VT;
1710  SDOperand Ptr;
1711  bool isSEXTLoad = false;
1712  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1713    Ptr = LD->getBasePtr();
1714    VT  = LD->getMemoryVT();
1715    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1716  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1717    Ptr = ST->getBasePtr();
1718    VT  = ST->getMemoryVT();
1719  } else
1720    return false;
1721
1722  bool isInc;
1723  bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1724                                        isInc, DAG);
1725  if (isLegal) {
1726    AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1727    return true;
1728  }
1729  return false;
1730}
1731
1732/// getPostIndexedAddressParts - returns true by value, base pointer and
1733/// offset pointer and addressing mode by reference if this node can be
1734/// combined with a load / store to form a post-indexed load / store.
1735bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1736                                                   SDOperand &Base,
1737                                                   SDOperand &Offset,
1738                                                   ISD::MemIndexedMode &AM,
1739                                                   SelectionDAG &DAG) {
1740  if (Subtarget->isThumb())
1741    return false;
1742
1743  MVT VT;
1744  SDOperand Ptr;
1745  bool isSEXTLoad = false;
1746  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1747    VT  = LD->getMemoryVT();
1748    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1749  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1750    VT  = ST->getMemoryVT();
1751  } else
1752    return false;
1753
1754  bool isInc;
1755  bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1756                                        isInc, DAG);
1757  if (isLegal) {
1758    AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1759    return true;
1760  }
1761  return false;
1762}
1763
1764void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1765                                                       const APInt &Mask,
1766                                                       APInt &KnownZero,
1767                                                       APInt &KnownOne,
1768                                                       const SelectionDAG &DAG,
1769                                                       unsigned Depth) const {
1770  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1771  switch (Op.getOpcode()) {
1772  default: break;
1773  case ARMISD::CMOV: {
1774    // Bits are known zero/one if known on the LHS and RHS.
1775    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1776    if (KnownZero == 0 && KnownOne == 0) return;
1777
1778    APInt KnownZeroRHS, KnownOneRHS;
1779    DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
1780                          KnownZeroRHS, KnownOneRHS, Depth+1);
1781    KnownZero &= KnownZeroRHS;
1782    KnownOne  &= KnownOneRHS;
1783    return;
1784  }
1785  }
1786}
1787
1788//===----------------------------------------------------------------------===//
1789//                           ARM Inline Assembly Support
1790//===----------------------------------------------------------------------===//
1791
1792/// getConstraintType - Given a constraint letter, return the type of
1793/// constraint it is for this target.
1794ARMTargetLowering::ConstraintType
1795ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1796  if (Constraint.size() == 1) {
1797    switch (Constraint[0]) {
1798    default:  break;
1799    case 'l': return C_RegisterClass;
1800    case 'w': return C_RegisterClass;
1801    }
1802  }
1803  return TargetLowering::getConstraintType(Constraint);
1804}
1805
1806std::pair<unsigned, const TargetRegisterClass*>
1807ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1808                                                MVT VT) const {
1809  if (Constraint.size() == 1) {
1810    // GCC RS6000 Constraint Letters
1811    switch (Constraint[0]) {
1812    case 'l':
1813    // FIXME: in thumb mode, 'l' is only low-regs.
1814    // FALL THROUGH.
1815    case 'r':
1816      return std::make_pair(0U, ARM::GPRRegisterClass);
1817    case 'w':
1818      if (VT == MVT::f32)
1819        return std::make_pair(0U, ARM::SPRRegisterClass);
1820      if (VT == MVT::f64)
1821        return std::make_pair(0U, ARM::DPRRegisterClass);
1822      break;
1823    }
1824  }
1825  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1826}
1827
1828std::vector<unsigned> ARMTargetLowering::
1829getRegClassForInlineAsmConstraint(const std::string &Constraint,
1830                                  MVT VT) const {
1831  if (Constraint.size() != 1)
1832    return std::vector<unsigned>();
1833
1834  switch (Constraint[0]) {      // GCC ARM Constraint Letters
1835  default: break;
1836  case 'l':
1837  case 'r':
1838    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1839                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1840                                 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1841                                 ARM::R12, ARM::LR, 0);
1842  case 'w':
1843    if (VT == MVT::f32)
1844      return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1845                                   ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1846                                   ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1847                                   ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1848                                   ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1849                                   ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1850                                   ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1851                                   ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1852    if (VT == MVT::f64)
1853      return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1854                                   ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1855                                   ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1856                                   ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1857      break;
1858  }
1859
1860  return std::vector<unsigned>();
1861}
1862